Datasheet SL4502BD, SL4502BN Datasheet (SLS)

Semiconductor

Strobed Hex Inverter/Buffer

High-Voltage Silicon-Gate CMOS

The SL4502B consists of six inverter/buffers with 3-state outputs. A logic “1” on the OUTPUT ENABLE input produces a high impedance state in all six outputs. This feature permits common busing of the outputs, thus simplifying system design. A logic “1” on the DIRECTION input switches all six outputs to logic “0” if the OUTPUT ENABLE input is a logic “0”.

• Operating Voltage Range: 3.0 to 18 V

• Maximum input current of 1 µA at 18 V over full package-

temperature range; 100 nA at 18 V and 25°C

• Noise margin (over full package temperature range):

1.0 V min @ 5.0 V supply

2.0 V min @ 10.0 V supply

2.5 V min @ 15.0 V supply

SL4502B

ORDERING INFORMATION

SL4502BN Plastic

SL4502BD SOIC

TA = -55° to 125° C for all packages

LOGIC DIAGRAM

PIN ASSIGNMENT

FUNCTION TABLE

Inputs Output

Output

Enable

L L L H L L H L

Direction A Y

SLS

System Logic

PIN 16=VCC

PIN 8= GND

L H X L

H X X Z

Z = high impedance X = don’t care

SL4502B

Semiconductor

MAXIMUM RATINGS*

Symbol Parameter Value Unit

VCC DC Supply Voltage (Referenced to GND) -0.5 to +20 V VIN DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V

V

DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V

OUT

IIN DC Input Current, per Pin ±10 mA PD Power Dissipation in Still Air, Plastic DIP+

SOIC Package+

PD Power Dissipation per Output Transistor 100 mW

Tstg Storage Temperature -65 to +150 °C

TL Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP or SOIC Package)

*

Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C

SOIC Package: : - 7 mW/°C from 65° to 125°C

750 500

260 °C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

VCC DC Supply Voltage (Referenced to GND) 3.0 18 V

VIN, V

DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

OUT

TA Operating Temperature, All Package Types -55 +125 °C

mW

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper opera tion, VIN and V GND≤(VIN or V

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

OUT

)≤VCC.

should be constrained to the range

OUT

System Logic

SLS

Semiconductor

DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)

VCC Guaranteed Limit

SL4502B

Symbol Parameter Test Conditions V ≥-55°C 25°C ≤125

°C

VIH Minimum High-Level

Input Voltage

VIL Maximum Low -Level

Input Voltage

VOH Minimum High-Level

Output Voltage

VOL Maximum Low -Level

Output Voltage

IIN Maximum Input

V

=0.5 V

OUT

V

=1 V

OUT

V

=1.5

OUT

V

= V = V = V

- 0.5V

CC

- 1.0 V

CC

- 1.5V

CC

OUT

V

OUT

V

OUT

VIN=GND 5.0

VIN= VCC 5.0

5.0 10 15

10 15

3.5 7

11

1.5 3 4

4.95

9.95

14.95

0.05

3.5 7

11

1.5 3 4

4.95

9.95

14.95

0.05

3.5 7

11

1.5 3 4

4.95

9.95

14.95

0.05

VIN= GND or VCC 18 ±0.1 ±0.1 ±1.0 µA

Leakage Current

ICC Maximum Quiescent

Supply Current (per Package)

IOL Minimum Output Low

(Sink) Current

VIN= GND or VCC 5.0

10 15 20

VIN= GND or VCC UOL=0.4 V UOL=0.5 V UOL=1.5 V

5.0 10 15

1 2 4

20

3.84

9.6

25.2

1 2 4

20

3.06

7.8

20.4

30

60 120 600

2.16

5.4

14.4

Unit

V

µA

mA

IOH Minimum Output High

(Source) Current

IOZ Maximum Tree-State

Leakage Current

System Logic

SLS

VIN= GND or VCC UOH=2.5 V UOH=4.6 V UOH=9.5 V UOH=13.5 V

Output in High-Impedance State VIN= GND or VCC V

= GND or VCC

OUT

5.0

5.0 10 15

-2

-0.64

-1.6

-4.2

-1.6

-0.51

-1.3

-3.4

-1.15

-0.36

-0.9

-2.4

mA

18 ±0.4 ±0.4 ±12 µA

SL4502B

Semiconductor

AC ELECTRICAL CHARACTERISTICS(C

=50pF, RL=200kΩ unless otherwise specified, Input

L

tr=tf=20 ns)

VCC Guaranteed Limit

Symbol Parameter V ≥-55°C 25°C ≤125°C Unit

t

Maximum Propagation Delay, Input A or

PHL

Direction to Output Y (Figure 1)

t

Maximum Propagation Delay, Input A or

PLH

Direction to Output Y (Figure 1)

t

Maximum Propagation Delay, Output Enable to

PHZ

Output Y (Figure 2) RL = 1 kΩ

t

Maximum Propagation Delay, Output Enable to

PZH

Output Y (Figure 2) RL = 1 kΩ

t

Maximum Propagation Delay, Output Enable to

PLZ

Output Y (Figure 2) RL = 1 kΩ

t

Maximum Propagation Delay, Output Enable to

PZL

Output Y (Figure 2) RL = 1 kΩ

5.0 10 15

270 120

80

380 180 130

120

80 60

220 100

80

250 130 110

250 110

80

270 120

80

380 180 130

120

80 60

220 100

80

250 130 110

250 110

80

540 240 160

760 360 260

240 160 120

440 200 160

500 260 220

500 220 160

ns

t

Maximum Output Transition Time, Any Output

TLH

(Figure 1)

t

Maximum Output Transition Time, Any Output

THL

(Figure 1)

5.0 10 15

200 100

80

120

60 40

200 100

80

120

60 40

400 200 160

240 120

80

CIN Maximum Input Capacitance - 7.5 pF

C

Maximum Tree-State Output Capacitance

OUT

- 15 pF

(Output in High-Impedance State)

ns

SLS

System Logic

SL4502B

Semiconductor

Figure 1. Switching Waveforms Figure 2. Switching Waveforms

EXPANDED LOGIC DIAGRAM

(1/6 of the Device)

SLS

System Logic