Page 1
SL4081B
Semiconductor
Quad 2-Input AND Gate
High-Voltage Silicon-Gate CMOS
The SL4081B AND gates provide the system designer with direct
emplementation of the AND function.
• Operating Voltage Range: 3.0 to 18 V
• Maximum input current of 1 µA at 18 V over full package-
temperature range; 100 nA at 18 V and 25°C
• Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
LOGIC DIAGRAM
ORDERING INFORMATION
SL4081BN Plastic
SL4081BD SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
PIN 14 =VCC
PIN 7 = GND
FUNCTION TABLE
Inputs Output
A B Y
L L L
L H L
H L L
H H H
System Logic
SLS
Page 2
SL4081B
Semiconductor
MAXIMUM RATINGS*
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) -0.5 to +20 V
VIN DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V
V
DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
OUT
IIN DC Input Current, per Pin ±10 mA
PD Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
PD Power Dissipation per Output Transistor 100 mW
Tstg Storage Temperature -65 to +150 °C
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond whi ch damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
750
500
260 °C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 3.0 18 V
VIN, V
DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
OUT
TA Operating Temperature, All Package Types -55 +125 °C
mW
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and V
GND≤(VIN or V
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.
System Logic
SLS
OUT
)≤VCC.
should be constrained to the range
OUT
Page 3
SL4081B
Semiconductor
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC Guaranteed Limit
Symbol Parameter Test Conditions V ≥-55°C 25°C ≤125
°C
VIH Minimum High-Level
Input Voltage
VIL Maximum Low -Level
Input Voltage
VOH Minimum High-Level
Output Voltage
VOL Maximum Low -Level
Output Voltage
IIN Maximum Input
V
=0.5V or V
OUT
V
=1.0V or VCC - 1.0V
OUT
V
=1.5V or VCC - 1.5V
OUT
V
=0.5V
OUT
V
=1.0V
OUT
V
=1.5V
OUT
VIN=VCC 5.0
VIN=GND or VCC 5.0
- 0.5V
CC
5.0
10
15
5.0
10
15
10
15
10
15
3.5
7
11
1.5
3
4
4.95
9.95
14.95
0.05
0.05
0.05
3.5
7
11
1.5
3
4
4.95
9.95
14.95
0.05
0.05
0.05
3.5
7
11
1.5
3
4
4.95
9.95
14.95
0.05
0.05
0.05
VIN= GND or VCC 18 ±0.1 ±0.1 ±1.0 µA
Leakage Current
ICC Maximum Quiescent
Supply Current
(per Package)
IOL Minimum Output Low
(Sink) Current
VIN= GND or VCC 5.0
10
15
20
VIN= GND or VCC
UOL=0.4 V
UOL=0.5 V
UOL=1.5 V
5.0
10
15
0.25
0.5
1.0
5.0
0.64
1.6
4.2
0.25
0.5
1.0
5.0
0.51
1.3
3.4
7.5
15
30
150
0.36
0.9
2.4
Unit
V
V
V
V
µA
mA
IOH Minimum Output High
(Source) Current
VIN= GND or VCC
UOH=2.5 V
UOH=4.6 V
UOH=9.5 V
UOH=13.5 V
5.0
5.0
10
15
-2.0
-0.64
-1.6
-4.2
-1.6
-0.51
-1.3
-3.4
SLS
-1.15
-0.36
-0.9
-2.4
System Logic
mA
Page 4
SL4081B
Semiconductor
AC ELECTRICAL CHARACTERISTICS(C
VCC Guaranteed Limit
Symbol Parameter V ≥-55°C 25°C ≤125°C Unit
t
, t
PLH
t
TLH
Maximum Propagation Delay, Input A or B to
PHL
Output Y (Figure 1)
, t
Maximum Output Transition Time, Any Output
THL
(Figure 1)
CIN Maximum Input Capacitance - 7.5 pF
Figure 1. Switching Waveforms
=50pF, RL=200kΩ, Input tr=tf=20 ns)
L
5.0
10
15
5.0
10
15
250
120
90
200
100
80
250
120
90
200
100
80
500
240
180
400
200
160
EXPANDED LOGIC DIAGRAM
(1/4 of the Device)
ns
ns
SLS
System Logic
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