Page 1
SL4070B
System Logic
Semiconductor
SLS
Quad Exclusive-OR Gate
High-Voltage Silicon-Gate CMOS
The SL4070B types consist of four independent Exclusive-OR
gates. The SL4070B provides the system designer with a means for
direct implementation of the Exlusive-OR function.
• Operating Voltage Range: 3.0 to 18 V
• Maximum input current of 1 µA at 18 V over full package-
temperature range; 100 nA at 18 V and 25°C
• Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
ORDERING INFORMATION
SL4070BN Plastic
SL4070BD SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN 14 =VCC
PIN 7 = GND
PIN ASSIGNMENT
FUNCTION TABLE
Inputs Output
A B Y
L L L
L H H
H L H
H H L
Page 2
SL4070B
System Logic
Semiconductor
SLS
MAXIMUM RATINGS*
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) -0.5 to +20 V
VIN DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V
V
OUT
DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
IIN DC Input Current, per Pin ±10 mA
PD Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
PD Power Dissipation per Output Transistor 100 mW
Tstg Storage Temperature -65 to +150 °C
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260 °C
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 3.0 18 V
VIN, V
OUT
DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
TA Operating Temperature, All Package Types -55 +125 °C
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and V
OUT
should be constrained to the range
GND≤(VIN or V
OUT
)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.
Page 3
SL4070B
System Logic
Semiconductor
SLS
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC Guaranteed Limit
Symbol Parameter Test Conditions V ≥-55°C 25°C ≤125
°C
Unit
VIH Minimum High-Level
Input Voltage
V
OUT
=0.5V or V
CC
- 0.5V
V
OUT
=1.0V or VCC - 1.0V
V
OUT
=1.5V or VCC - 1.5V
5.0
10
15
3.5
7
11
3.5
7
11
3.5
7
11
V
VIL Maximum Low -Level
Input Voltage
V
OUT
=0.5V or V
CC
- 0.5V
V
OUT
=1.0V or VCC - 1.0V
V
OUT
=1.5V or VCC - 1.5V
5.0
10
15
1.5
3
4
1.5
3
4
1.5
3
4
V
VOH Minimum High-Level
Output Voltage
VIN=GND or VCC 5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
4.95
9.95
14.95
V
VOL Maximum Low -Level
Output Voltage
VIN=GND or VCC 5.0
10
15
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
V
IIN Maximum Input
Leakage Current
VIN= GND or VCC 18 ±0.1 ±0.1 ±1.0 µA
ICC Maximum Quiescent
Supply Current
(per Package)
VIN= GND or VCC 5.0
10
15
20
0.25
0.5
1.0
5.0
0.25
0.5
1.0
5.0
7.5
15
30
150
µA
IOL Minimum Output Low
(Sink) Current
VIN= GND or VCC
UOL=0.4 V
UOL=0.5 V
UOL=1.5 V
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.36
0.9
2.4
mA
IOH Minimum Output High
(Source) Current
VIN= GND or VCC
UOH=2.5 V
UOH=4.6 V
UOH=9.5 V
UOH=13.5 V
5.0
5.0
10
15
-2.0
-0.64
-1.6
-4.2
-1.6
-0.51
-1.3
-3.4
-1.15
-0.36
-0.9
-2.4
mA
Page 4
SL4070B
System Logic
Semiconductor
SLS
AC ELECTRICAL CHARACTERISTICS(C
L
=50pF, RL=200kΩ, Input tr=tf=20 ns)
VCC Guaranteed Limit
Symbol Parameter V ≥-55°C 25°C ≤125°C Unit
t
PLH
, t
PHL
Maximum Propagation Delay, Input A or B to
Output Y (Figure 1)
5.0
10
15
280
130
100
280
130
100
560
260
200
ns
t
TLH
, t
THL
Maximum Output Transition Time, Any Output
(Figure 1)
5.0
10
15
200
100
80
200
100
80
400
200
160
ns
CIN Maximum Input Capacitance - 7.5 pF
Figure 1. Switching Waveforms
EXPANDED LOGIC DIAGRAM
(1/4 of the Device)
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