Page 1
Semiconductor
14-Stage Ripple-Carry Binary
Counter/Divider and Oscillator
High-Voltage Silicon-Gate CMOS
The SL4060B consists of an oscillator section and 14 ripple -carry
binary counter stages. The oscillator configuration allows design of
either RC or crystal oscillator circuits. A RESET input is provided
which resets the counter to the all-Q’s state and disables the oscillator.
A high level on the RESET line accomplishes the reset function. All
counter stages are master-slave flip -flops. The state of the counter is
advanced one step in binary order on the negative transition of OSC In
(and OSC Out). Schmitt trigger action on the input-pulse line permits
unlimited input-pulse rise and fall times.
• Operating Voltage Range: 3.0 to 18 V
• Maximum input current of 1 µA at 18 V over full package-
temperature range; 100 nA at 18 V and 25°C
• Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
SL4060B
ORDERING INFORMATION
SL4060BN Plastic
SL4060BD SOIC
TA = -55° to 125° C for all
packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 16=VCC
PIN 8= GND
FUNCTION TABLE
Inputs Outputs
Osc In Reset Q
L No change
L Advance to
X H All Outputs
X = don’t care
next state
are low
SLS
System Logic
Page 2
SL4060B
Semiconductor
MAXIMUM RATINGS*
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) -0.5 to +20 V
VIN DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V
V
DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
OUT
IIN DC Input Current, per Pin ±10 mA
PD Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
PD Power Dissipation per Output Transistor 100 mW
Tstg Storage Temperature -65 to +150 °C
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
750
500
260 °C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 3.0 18 V
VIN, V
DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
OUT
TA Operating Temperature, All Package Types -55 +125 °C
mW
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and V
GND≤(VIN or V
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.
OUT
)≤VCC.
should be constrained to the range
OUT
System Logic
SLS
Page 3
Semiconductor
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC Guaranteed Limit
SL4060B
Symbol Parameter Test Conditions V ≥-55°C 25°C ≤125
°C
VIH Minimum High-Level
Input Voltage
VIL Maximum Low -Level
Input Voltage
VOH Minimum High-Level
Output Voltage
VOL Maximum Low -Level
Output Voltage
IIN Maximum Input
V
= 0.5 V or V
OUT
V
= 1.0 V or V
OUT
V
= 1.5 V V
OUT
V
= 0.5 V or V
OUT
V
= 1.0 V or V
OUT
V
= 1.5 V V
OUT
VIN=GND or VCC 5.0
VIN=GND or VCC 5.0
CC
CC
- 0.5V
CC
- 1.0 V
CC
- 1.5V
- 0.5V
CC
- 1.0 V
CC
- 1.5V
5.0
10
15
5.0
10
15
10
15
10
15
3.5
7
11
1.5
3
4
4.95
9.95
14.95
0.05
0.05
0.05
3.5
7
11
1.5
3
4
4.95
9.95
14.95
0.05
0.05
0.05
3.5
7
11
1.5
3
4
4.95
9.95
14.95
0.05
0.05
0.05
VIN= GND or VCC 18 ±0.1 ±0.1 ±1.0 µA
Leakage Current
ICC Maximum Quiescent
Supply Current
(per Package)
IOL Minimum Output Low
(Sink) Current
VIN= GND or VCC 5.0
10
15
20
VIN= GND or VCC
UOL=0.4 V
UOL=0.5 V
UOL=1.5 V
5.0
10
15
5
10
20
100
0.64
1.6
4.2
5
10
20
100
0.51
1.3
3.4
150
300
600
3000
0.36
0.9
2.4
Unit
V
V
V
V
µA
mA
IOH Minimum Output High
(Source) Current
System Logic
SLS
VIN= GND or VCC
UOH=2.5 V
UOH=4.6 V
UOH=9.5 V
UOH=13.5 V
5.0
5.0
10
15
-2
-0.64
-1.6
-4.2
-1.6
-0.51
-1.3
-3.4
-1.15
-0.36
-0.9
-2.4
mA
Page 4
SL4060B
Semiconductor
AC ELECTRICAL CHARACTERISTICS(C
=50pF, RL=200kΩ, Input tr=tf=20 ns)
L
VCC Guaranteed Limit
Symbol Parameter V ≥-55°C 25°C ≤125°C Unit
f
Maximum Clock Frequency (50% Duty Cycle)
max
(Figure 1)
t
, t
PHL
Maximum Propagation Delay, Clock to Q4
PLH
(Figure 1)
t
, t
PHL
Maximum Propagation Delay, Qn to Q
PLH
2)
t
Maximum Propagation Delay, Reset to Any Q
PHL
(Figure 3)
t
, t
THL
Maximum Output Transition Time, Any Output
TLH
(Figure 1)
(Figure
n+1
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
3.5
8
12
740
300
200
200
100
80
360
160
100
200
100
80
3.5
8
12
740
300
200
200
100
80
360
160
100
200
100
80
1.75
4
6
1480
600
400
400
200
160
720
320
200
400
200
160
CIN Maximum Input Capacitance - 7.5 pF
TIMING REQUIREMENTS(C
=50pF, RL=200 kΩ, Input tr=tf=20 ns)
L
MHz
ns
ns
ns
ns
VCC Guaranteed Limit
Symbol Parameter V ≥-55°C 25°C ≤125°C Unit
tw Minimum Pulse Width, Clock (Figure 1) 5.0
10
15
tw Minimum Pulse Width, Reset (Figure 3) 5.0
10
15
tf, tr Maximum Input Rise and Fall Times (Figure 1) 5.0
10
100
40
30
120
60
40
100
40
30
120
60
40
Unlimited
200
80
60
240
120
80
ns
ns
ns
15
System Logic
SLS
Page 5
SL4060B
Semiconductor
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms Figure 3. Switching Waveforms
EXPANDED LOGIC DIAGRAM
* R = HIGH DOMINATES (RESETS ALL STAGES)
** COUNTER ADVANCES ONE BINARY COUNT ON EACH NEGATIVE - GOING TRANSITION OF CLOCK
(AND OSC OUT)
System Logic
SLS
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