Page 1
Semiconductor
Analog Multiplexer Demultiplexer
High-Performance Silicon-Gate CMOS
The SL4052B analog multiplexer/demultiplexer is digitally controlled
analog switches having low ON impedance and very low OFF leakage
current. Control of analog signals up to 20V peak-to-peak can be
achieved by digital signal amplitudes of 4.5 to 20V (if VCC - GND = 3V, a
VCC - VEE of up to 13 V can be controlled; for VCC - VEE level differences
above 13V a VCC - GND of at least 4.5V is required).
These multiplexer circuits dissipate extremely low quiescent power
over the full V
independent of the logic state of the control signals. When a logic
“1”is present at the ENABLE input terminal all channels are off.
The SL4052 is a differential 4-channel multiplexer having two binary
control inputs. A and B, and an enable input. The two binary input
signals select 1 of 4 pairs of channels to turned on and connect the
analog inputs to the outputs.
• Operating Voltage Range: 3.0 to 18 V
• Maximum input current of 1
µA at 18 V over full package-temperature range; 100 nA at 18 V and
25°C
• Noise margin (over full package temperature range):
-GND and VCC - VEE supply-voltage ranges,
CC
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
SL4052B
ORDERING INFORMATION
SL4052BN Plastic
SL4052BD SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
SLS
LOGIC DIAGRAM
Double-Pole, 4-Position
System Logic
Plus Common Off
PIN 16 =V
PIN 7 = VEE
PIN 8 = GND
CC
FUNCTION TABLE
Control Inputs ON
Enable Select Channels
B A
L L L Y0 X0
L L H Y1 X1
L H L Y2 X2
L H H Y3 X3
H X X None
X = don’t care
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SL4052B
Semiconductor
MAXIMUM RATINGS*
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) -0.5 to +20 V
VIN DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V
V
DC Output V oltage (Referenced to GND) -0.5 to VCC +0.5 V
OUT
IIN DC Input Current, per Pin ±10 mA
PD Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
PD Power Dissipation per Output Transistor 100 mW
Tstg Storage Temperature -65 to +150 °C
TL Lead Temperature, 1 mm from Case for 10 Seconds
260 °C
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 3.0 18 V
VIN, V
*
In certain applications, the external load-resistor current may include both VCC and signal -line components.
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and V
GND≤(VIN or V
Analog I/O pins may be left open or terminated.
DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
OUT
TA Operating Temperature, All Package Types -55 +125 °C
I Multiplexer Switch Input Current Capability* - 25 mA
ROH Output Load Resistance 100 - Ω
This device contains protection circuitry to guard against damage due to high static voltages or electric
should be constrained to the range
OUT
)≤VCC.
OUT
Unused digital pins must be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
SLS
System Logic
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SL4052B
Semiconductor
DC ELECTRICAL CHARACTERISTICS Digital Section
VCC Guaranteed Limit
Symbol Parameter Test Conditions V ≥ -55
VIH Minimum High-Level
Input Voltage, Channel Select or Enable Inputs
VIL Maximum Low -Level
Input Voltage, Channel Select or Enable Inputs
IIN Maximum Input
Leakage Current,
Channel-Select or
Enable Inputs
ICC Maximum Quiescent
Supply Current (per
Package)
VIS=VCC thru 1kΩ
VEE=GND
IIS<2µA on all OFF Chanels
RL=1kΩ to GND
VIS=VCC thru 1kΩ
VEE=GND
IIS<2µA on all OFF Chanels
RL=1kΩ to G ND
VIN=VCC or GND 18 ±0.1 ±0.1 ±1.0 µA
Channel Select = VCC or GND
5
10
15
5
10
15
5
10
15
20
°C
3.5
7
11
1.5
3
4
5
10
20
100
≤ 25
°C
3.5
7
11
1.5
3
4
5
10
20
100
≤ 125
°C
3.5
7
12
1.4
3
4
150
300
600
3000
Unit
V
V
µA
DC ELECTRICAL CHARACTERISTICS Analog Section
VCC Guaranteed Limit
Symbol Parameter Test Conditions V ≥ -55
°C
RON Maximum “ON” Resistance VEE=GND=0
V
= GND to VCC
IS
∆RON Maximum Difference in
“ON” Resistance Between
Any Two Channels in the
Same Package
I
Maximum Off- Channel
OFF
Leakage Current, Any One
Channel
Maximum Off- Channel
Leakage Current, Common
Channel
VEE=GND=0 5
VEE=GND=0 18 ±100 ±100 ±1000 nA
VEE=GND=0 18 ±100 ±100 ±1000
5
10
15
10
15
800
310
200
-
-
-
≤ 25
°C
1050
400
240
10
15
5
≤ 125
°C
1300
550
320
-
-
-
Unit
Ω
Ω
SLS
System Logic
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SL4052B
Semiconductor
AC ELECTRICAL CHARACTERISTICS(C
=50pF,Input tr=tf=20.0 ns)
L
VCC Guaranteed Limit
Symbol Parameter V ≥ -55
°C
t
, t
t
PLH
PLZ
Maximum Propagation Delay , Analog Input to
PHL
Analog Output (Figure 1)
RL=200kΩ
, t
Maximum Propagation Delay , Address to Analog
PHZ
Output (Figure 2) RL=10kΩ
VEE=GND=0
5
10
15
5
10
15
60
30
20
720
320
240
≤ 25
°C
60
30
20
720
320
240
VEE=-5V 5 450 450 900
t
,
t
PLZ
PZL
Maximum Propagation Delay, Enable to Analog
Output (Figure 2) RL=10kΩ
VEE=GND=0
5
10
15
720
320
240
720
320
240
VEE=-10V 5 400 400 800
t
,
PHZ
t
PZH
Maximum Propagation Delay, Enable to Analog
Output (Figure 2) RL=10kΩ
VEE=GND=0
5
10
15
450
210
160
450
210
160
VEE=-10V 5 300 300 600
CIN Maximum Input Capacitance, Channel -Select or
- 7.5 7.5 7.5 pF
Enable Inputs
≤ 125
°C
120
60
40
1440
640
480
1440
640
480
900
420
320
Unit
ns
ns
ns
ns
C
Maximum Capacitance
I/O
VEE=GND=-5V
CIS
5
-
5
COS 5 - 18 -
Feedthrough C
5 - 0.2 -
IOS
-
pF
SLS
System Logic
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SL4052B
Semiconductor
(peak)
ADDITIONAL APPLICATION CHARACTERISTICS
VCC VIS Limit*
Symbol Parameter Test Conditions V V 25 °C Unit
BW Maximum On-
Channel
Bandwidth or
Minimum
Frequency
Response (-3db)
VOS at Any Channel 10 5* 60
(-40db)
Feedthrough
Frequency (All
Channels OFF)
VOS at Any Channel 10 5* 8
(-40db)
Signal Crosstalk
Frequency
THD Total Harmonic
Distortion
- Address-or
Enable to Signal
Crosstalk
VEE=GND
RL=1kΩ
20 log(VOS/VIS)=-3db
VOS at Common OUT/IN
VEE=GND
RL=1kΩ
20 log(VOS/VIS)=-40db
VOS at Common OUT/IN
VEE=GND
RL=1kΩ
20 log(VOS/VIS)=-40db
Between Sections :
Measured on Common
Measured on Any Chanel
VEE=GND
fIS=1kHz sine wave
VEE=GND
RL=10kΩ**
tr,tf=20ns
Square Wave
10
10
5
10
15
10 - 65 mv
5*
5*
2*
3*
5*
25
10
6
10
0.3
0.2
012
MHz
%
* Peak -to-peak voltage symmetrical about (VDD-VEE)/2
** Both ends of channel
System Logic
SLS
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SL4052B
Semiconductor
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
EXPANDED LOGIC DIAGRAM
System Logic
SLS
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