Page 1
Semiconductor
Hex Buffer/Converter
High-Voltage Silicon-Gate CMOS
The SL4050B is noninverting hex buffers and feature logic-level
conversion using only one supply (voltage (VCC). The input-signal high
level (VIH) can exceed the VCC supply voltage when these devices are
used for logic-level conversions. These devices are intended for use as
CMOS to DTL/TTL converters.
• Operating Voltage Range: 3.0 to 18 V
• Maximum input current of 1 µA at 18 V over full package-
temperature range; 100 nA at 18 V and 25°C
• Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
• High-to-low level conversion
SL4050B
ORDERING INFORMATION
SL4050BN Plastic
SL4050BD SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PINS 13, 16 = NO CONNECTION
PIN 1 =VCC
PIN 8 = GND
PIN ASSIGNMENT
NC = NO CONNECTION
FUNCTION TABLE
Inputs Output
A Y
L L
H H
SLS
System Logic
Page 2
SL4050B
Semiconductor
MAXIMUM RATINGS*
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) -0.5 to +20 V
VIN DC Input Voltage (Referenced to GND) V
V
DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
OUT
IIN DC Input Current, per Pin ±10 mA
**
to +18 V
CC
PD Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
PD Power Dissipation per Output Transistor 100 mW
Tstg Storage Temperature -65 to +150 °C
TL Lead Temperature, 1 mm from Case for 10 Seconds
260 °C
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur .
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
**
The IW4050B has high-to-low level voltage conversion capability but not low -to-high level; therefore it is
recommended that VIN ≥ VCC
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 3.0 18 V
VIN DC Input Voltage (Referenced to GND) V
V
DC Output Voltage (Referenced to GND) 0 VCC V
OUT
TA Operating Temperature, All Package Types -55 +125 °C
**
The IW4050B has high-to-low level voltage conversion capability but not low -to-high level; therefore it is
recommended that VIN ≥ VCC
**
18 V
CC
mW
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and V
GND≤(VIN or V
OUT
)≤VCC.
should be constrained to the range
OUT
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.
System Logic
SLS
Page 3
Semiconductor
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC Guaranteed Limit
SL4050B
Symbol Parameter Test Conditions V ≥-55°C 25°C ≤125
°C
VIH Minimum High-Level
Input Voltage
VIL Maximum Low -Level
Input Voltage
VOH Minimum High-Level
Output Voltage
VOL Maximum Low -Level
Output Voltage
IIN Maximum Input
V
= V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
- 0.5V
CC
= V
- 1.0 V
CC
= V
- 1.5V
CC
= 0.5V
= 1.0 V
= 1.5V
VIN= VCC 5.0
VIN=GND 5.0
5.0
10
15
5.0
10
15
10
15
10
15
3.5
7
11
1.5
3
4
4.95
9.95
14.95
0.05
0.05
0.05
3.5
7
11
1.5
3
4
4.95
9.95
14.95
0.05
0.05
0.05
3.5
7
11
1.5
3
4
4.95
9.95
14.95
0.05
0.05
0.05
VIN= GND or VCC 18 ±0.1 ±0.1 ±1.0 µA
Leakage Current
ICC Maximum Quiescent
Supply Current
(per Package)
IOL Minimum Output Low
(Sink) Current
VIN= GND or VCC 5.0
10
15
20
VIN= GND or VCC
UOL=0.4 V
UOL=0.4 V
UOL=0.5 V
UOL=1.5 V
4.5
5
10
15
1
2
4
20
3.3
4
10
26
1
2
4
20
2.6
3.2
8
24
30
60
120
600
1.8
2.4
5.6
18
Unit
V
V
V
V
µA
mA
IOH Minimum Output High
(Source) Current
System Logic
SLS
VIN= GND or VCC
UOH=2.5 V
UOH=4.6 V
UOH=9.5 V
UOH=13.5 V
5.0
5.0
10
15
-2.6
-0.81
-2.0
-5.2
-2.1
-0.65
-1.65
-4.3
-1.55
-0.48
-1.18
-3.1
mA
Page 4
SL4050B
Semiconductor
AC ELECTRICAL CHARACTERISTICS(C
VIN VCC Guaranteed Limit
Symbol Parameter V V ≥-55°C 25°C ≤125°C Unit
t
Maximum Propagation Delay, Input A to
PLH
Output Y (Figure 1)
t
Maximum Propagation Delay, Input A to
PHL
Output Y (Figure 1)
t
Maximum Output Transition Time, Any
TLH
Output (Figure 1)
t
Maximum Output Transition Time, Any
THL
Output (Figure 1)
CIN Maximum Input Capacitance - - 7.5 pF
=50pF, RL=200kΩ, Input tr=tf=20 ns)
L
5
10
10
15
15
5
10
10
15
15
5
10
15
5
10
15
5
10
5
15
5
5
10
5
15
5
5
10
15
5
10
15
140
80
90
60
80
110
55
100
30
100
160
80
60
60
40
30
140
80
90
60
80
110
55
100
30
100
160
80
60
60
40
30
280
160
180
120
160
220
110
200
60
200
320
160
120
120
80
60
ns
ns
ns
ns
Figure 1. Switching Waveforms
EXPANDED LOGIC DIAGRAM
(1/6 of the Device)
System Logic
SLS
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