Page 1
SL4043B
Semiconductor
Quad 3-State R/S Latch
High-Voltage Silicon-Gate CMOS
The SL4043B types are quad cross-coupled 3-state CMOS NOR
latces. Each latch has a separate Q output and individual SET and
RESET inputs. The Q outputs are controlled by a common ENABLE
input. A logic “1” or high on the ENABLE input connects the latch
states to the Q outputs. A logic “0” or low on the ENABLE input
disconnects the latch states from the Q outputs, resulting in an open
circuit condition on the Q outputs. The open circuit feature allows
common busing of the outputs.
• Operating Voltage Range: 3.0 to 18 V
• Maximum input current of 1 µA at 18 V over full package-
temperature range; 100 nA at 18 V and 25°C
• Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
ORDERING INFORMATION
SL4043BN Plastic
SL4043BD SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
FUNCTION TABLE
Inputs Outputs
S R OE Q
X X L High
Impedance
L L H No change
PIN 13 = NO CONNECTION
PIN 16=VCC
PIN 8= GND
L H H L
H L H H
H H H H
X = don’t care
System Logic
SLS
Page 2
SL4043B
Semiconductor
MAXIMUM RATINGS*
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) -0.5 to +20 V
VIN DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V
V
DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
OUT
IIN DC Input Current, per Pin ±10 mA
PD Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
PD Power Dissipation per Output Transistor 100 mW
Tstg Storage Temperature -65 to +150 °C
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
750
500
260 °C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 3.0 18 V
VIN, V
DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
OUT
TA Operating Temperature, All Package Types -55 +125 °C
mW
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and V
GND≤(VIN or V
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.
System Logic
SLS
OUT
)≤VCC.
should be constrained to the range
OUT
Page 3
SL4043B
Semiconductor
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC Guaranteed Limit
Symbol Parameter Test Conditions V ≥-55°C 25°C ≤125
°C
VIH Minimum High-Level
Input Voltage
VIL Maximum Low -Level
Input Voltage
VOH Minimum High-Level
Output Voltage
VOL Maximum Low -Level
Output Voltage
IIN Maximum Input
V
= 0.5 V or V
OUT
V
= 1.0 V or V
OUT
V
= 1.5 V or V
OUT
V
= 0.5 V or V
OUT
V
= 1.0 V or V
OUT
V
= 1.5 V or V
OUT
VIN=GND or VCC 5.0
VIN=GND or VCC 5.0
- 0.5V
CC
- 1.0 V
CC
- 1.5V
CC
- 0.5V
CC
- 1.0 V
CC
- 1.5V
CC
5.0
10
15
5.0
10
15
10
15
10
15
3.5
7
11
1.5
3
4
4.95
9.95
14.95
0.05
0.05
0.05
3.5
7
11
1.5
3
4
4.95
9.95
14.95
0.05
0.05
0.05
3.5
7
11
1.5
3
4
4.95
9.95
14.95
0.05
0.05
0.05
VIN= GND or VCC 18 ±0.1 ±0.1 ±1.0 µA
Leakage Current
IOZ Maximum Three State
Leakage Current
Output in High-Impedance
State
18 ±0.4 ±0.4 ±12.0 µA
VIN= GND or VCC
V
= GND or VCC
OUT
ICC Maximum Quiescent
Supply Current
(per Pack age)
VIN= GND or VCC 5.0
10
15
20
1
2
4
20
1
2
4
20
30
60
120
600
Unit
V
V
V
V
µA
IOL Minimum Output Low
(Sink) Current
IOH Minimum Output High
(Source) Current
VIN= GND or VCC
UOL=0.4 V
UOL=0.5 V
UOL=1.5 V
VIN= GND or VCC
UOH=2.5 V
UOH=4.6 V
UOH=9.5 V
UOH=13.5 V
5.0
10
15
5.0
5.0
10
15
0.64
1.6
4.2
-2
-0.64
-1.6
-4.2
0.51
1.3
3.4
-1.6
-0.51
-1.3
-3.4
SLS
0.36
0.9
2.4
-1.15
-0.36
-0.9
-2.4
System Logic
mA
mA
Page 4
SL4043B
Semiconductor
AC ELECTRICAL CHARACTERISTICS(C
=50pF, RL=200kΩ, Input tr=tf=20 ns)
L
VCC Guaranteed Limit
Symbol Parameter V ≥-55°C 25°C ≤125°C Unit
t
, t
t
t
t
PHL
PHZ
PLZ
THL
Maximum Propagation Delay, SET or RESET to
PLH
Q (Figure 1)
, t
Maximum Propagation Delay, Output Enable to
PZH
Q (Figures 2,4)
, t
Maximum Propagation Delay, Output Enable to
PZL
Q (Figures 2,4)
, t
Maximum Output Transition Time, Any Output
TLH
(Figure 1)
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
300
140
100
230
110
80
180
100
70
200
100
80
300
140
100
230
110
80
180
100
70
200
100
80
600
280
200
460
220
160
360
200
140
400
200
160
CIN Maximum Input Capacitance - 7.5 pF
TIMING REQUIREMENTS(C
=50pF, RL=200 kΩ, Input tr=tf=20 ns)
L
ns
ns
ns
ns
VCC Guaranteed Limit
Symbol Parameter V ≥-55°C 25°C ≤125°C Unit
tw Minimum Pulse Width, SET or RESET (Figure 3) 5.0
10
15
160
80
40
160
80
40
320
160
80
ns
Figure 1. Switching Waveforms Figure 2. Switching Waveforms
SLS
System Logic
Page 5
SL4043B
Semiconductor
Figure 3. Switching Waveforms
SLS
System Logic
Page 6
SL4043B
Semiconductor
TEST IN IN A
t
VCC GND GND
PHZ
t
GND VCC VCC
PLZ
t
VCC GND GND
PZH
t
GND VCC VCC
PZL
Figure 4. Test Circuit
EXPANDED LOGIC DIAGRAM
( 1/4 of the Device)
SLS
System Logic
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