Page 1
SL4020B
14 Stage Ripple-Carry Binary Counter/Divider
High-Voltage Silicon-Gate CMOS
The SL4020B is ripple -carry binary counter. All counter stages are
master-slave flip -flops. The state of a counter advances one count on
the negative transition of each input pulse; a high level on the RESET
line resets the counter to its all zeros state. Schmitt trigger action on the
input-pulse line permits unlimited rise and fall times.
• Operating Voltage Range: 3.0 to 18 V
• Maximum input current of 1 µA at 18 V over full package-
temperature range; 100 nA at 18 V and 25°C
• Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
ORDERING INFORMATION
SL4020BN Plastic
SL4020BD SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN 16 =VCC
PIN 8 = GND
PIN ASSIGNMENT
FUNCTION TABLE
Inputs Output
Clock Reset Output state
L No change
X H All Outputs
L Advance to
X=don’t care
next state
are low
System Logic
SLS
Semiconductor
Page 2
SL4020B
MAXIMUM RATINGS*
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) -0.5 to +20 V
VIN DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V
V
DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
OUT
IIN DC Input Current, per Pin ±10 mA
PD Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
PD Power Dissipation per Output Transistor 100 mW
Tstg Storage Temperature -65 to +150 °C
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
750
500
260 °C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 3.0 18 V
VIN, V
DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
OUT
TA Operating Temperature, All Package Types -55 +125 °C
mW
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and V
GND≤(VIN or V
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.
OUT
)≤VCC.
should be constrained to the range
OUT
System Logic
SLS
Semiconductor
Page 3
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC Guaranteed Limit
SL4020B
Symbol Parameter Test Conditions V ≥-55°C 25°C ≤125
°C
VIH Minimum High-Level
Input Voltage
VIL Maximum Low -Level
Input Voltage
VOH Minimum High-Level
Output Voltage
VOL Maximum Low -Level
Output Voltage
IIN Maximum Input
V
=0.5V or V
OUT
V
=1.0V or VCC - 1.0V
OUT
V
=1.5V or VCC - 1.5V
OUT
V
=0.5V or V
OUT
V
=1.0V or VCC - 1.0V
OUT
V
=1.5V or VCC - 1.5V
OUT
VIN=GND or VCC 5.0
VIN=GND or VCC 5.0
- 0.5V
CC
- 0.5V
CC
5.0
10
15
5.0
10
15
10
15
10
15
3.5
7
11
1.5
3
4
4.95
9.95
14.95
0.05
0.05
0.05
3.5
7
11
1.5
3
4
4.95
9.95
14.95
0.05
0.05
0.05
3.5
7
11
1.5
3
4
4.95
9.95
14.95
0.05
0.05
0.05
VIN= GND or VCC 18 ±0.1 ±0.1 ±1.0 µA
Leakage Current
ICC Maximum Quiescent
Supply Current
(per Package)
IOL Minimum Output Low
(Sink) Current
VIN= GND or VCC 5.0
10
15
20
VIN= GND or VCC
UOL=0.4 V
UOL=0.5 V
UOL=1.5 V
5.0
10
15
5
10
20
100
0.64
1.6
4.2
5
10
20
100
0.51
1.3
3.4
150
300
600
3000
0.36
0.9
2.4
Unit
V
V
V
V
µA
mA
IOH Minimum Output High
(Source) Current
System Logic
SLS
Semiconductor
VIN= GND or VCC
UOH=2.5 V
UOH=4.6 V
UOH=9.5 V
UOH=13.5 V
5.0
5.0
10
15
-2.0
-0.64
-1.6
-4.2
-1.6
-0.51
-1.3
-3.4
-1.15
-0.36
-0.9
-2.4
mA
Page 4
SL4020B
AC ELECTRICAL CHARACTERISTICS(C
=50pF, RL=200kΩ, Input tr=tf=20 ns)
L
VCC Guaranteed Limit
Symbol Parameter V ≥-55°C 25°C ≤125°C Unit
f
Maximum Clock Frequency(Figure 1) 5.0
max
t
, t
PLH
Maximum Propagation Delay, Clock to Q1
PHL
(Figure 1)
t
, t
PLH
Maximum Propagation Delay, Qn to Qn+1 (Figure
PHL
3)
t
Maximum Propagation Delay, Reset to Any Q
PHL
(Figure 2)
t
, t
TLH
Maximum Output Transition Tim e, Any Output
THL
(Figure 1)
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
3.5
8
12
360
160
130
330
80
60
280
120
100
200
100
80
3.5
8
12
360
160
130
330
80
60
280
120
100
200
100
80
1.75
4
6
720
320
260
660
160
120
560
240
200
400
200
160
CIN Maximum Input Capacitance - 7.5 pF
TIMING REQUIREMENTS (C
=50pF, RL=200kΩ, Input tr=tf=20 ns)
L
MHz
ns
ns
ns
ns
VCC Guaranteed Limit
Symbol Parameter V ≥-55°C 25°C ≤125°C Unit
tw Minimum Pulse Width, Clock (Figure 1) 5.0
tw Minimum Pulse Width, Reset (Figure 2) 5.0
t
Minimum Removal Time, Reset(Figure 2) 5.0
rem
t
Maximum Input Rise and Fall Times, Clock
r, tf
(Figure 1)
10
15
10
15
10
15
5.0
10
140
60
40
200
80
60
350
150
100
140
60
40
200
80
60
350
150
100
Unlimited
280
120
80
400
160
120
700
300
200
ns
ns
ns
µs
15
System Logic
SLS
Semiconductor
Page 5
SL4020B
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
System Logic
SLS
Semiconductor
Figure 3. Switching Waveforms
Page 6
SL4020B
TIMING DIAGRAM
EXPANDED LOGIC DIAGRAM
`
System Logic
SLS
Semiconductor
Loading...