Datasheet SL4017BD, SL4017BN Datasheet (SLS)

Semiconductor

Counter/Divider

High-Voltage Silicon-Gate CMOS

The SL4017B is 5-stage Johnson counter having 10 decoded outputs. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal. Schmitt trigger action in the CLOCK input circuit provides pulse shaping that allows unlimited clock input pulse rise and fall times.

The counter is advanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter advancement via the clock line is inhibited when the CLOCK INHIBIT signal is high. A high RESET signal clears the counter to its zero count. Use of the Johnson counter configuration permits high-speed operation, 2-input decode-gating and spike-free decoded outputs. Anti-lock gating is provided, thus assuring proper counting sequence. The decoded outputs are normally low and go high only at their respective decoded time slot. Each decoded output remains high for one full clock cycle. A CARRY-OUT signal completes one cycle every 10 clock input cycles in the SL4017B.

• Operating Voltage Range: 3.0 to 18 V

• Maximum input current of 1 µA at 18 V over full

package-temperature range; 100 nA at 18 V and 25°C

SL4017B

ORDERING INFORMATION

SL4017BN Plastic

SL4017BD SOIC

TA = -55° to 125° C for all

packages

PIN ASSIGNMENT

SL

LOGIC DIAGRAM

PIN 16 =V

PIN 8 = GND

System Logic

• Noise margin (over full package temperature range):

1.0 V min @ 5.0 V supply

2.0 V min @ 10.0 V supply

2.5 V min @ 15.0 V supply

CC

SL4017B

Semiconductor

FUNCTION TABLE

Clock Clock

Enable

L X L no change X H L no change X X H reset counter

X L no change

H L Advance to

* Carry Out=H for Q0,Q1,Q2,Q3 or Q4=H Carry Out = L otherwise, X=don’t care

Reset Output State *

Q0=H, Q1Q9=L, C0=H

L L Advance to

next state

X L no change

next state

SL

System Logic

SL4017B

Semiconductor

MAXIMUM RATINGS

*

Symbol Parameter Value Unit

V

CC

V

OUT

I

IN

P

DC Supply Voltage (Referenced to GND) -0.5 to +20 V DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V

IN

DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Input Current, per Pin ±10 mA Power Dissipation in Still Air, Plastic DIP+

D

SOIC Package+ Power Dissipation per Output Transistor 100 mW

D

750 500

mW

Tstg Storage Temperature -65 to +150 °C

T

Lead Temperature, 1 mm from Case for 10

L

260 °C Seconds (Plastic DIP or SOIC Package)

*

Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C

SOIC Package: : - 7 mW/°C from 65° to 125°C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

V

CC

VIN, V

OUT

T

A

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and V

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

DC Supply Voltage (Referenced to GND) 3.0 18 V DC Input Voltage, Output Voltage (Referenced to

0 V

CC

V

GND) Operating Temperature, All Package Types -55 +125 °C

should be constrained to the range GND ≤(VIN or V

OUT

)≤VCC.

SL

System Logic

SL4017B

Semiconductor

DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)

V

Guaranteed Limit

CC

Symbol Parameter Test Conditions V ≥-55°C 25°C ≤125°CUnit

V

OH

Minimum High-

IH

Level Input Voltage

Maximum Low -

IL

Level Input Voltage

Minimum HighLevel Output Voltage

V

=0.5V or V

OUT

V

=1.0V or VCC - 1.0V

OUT

V

=1.5V or VCC - 1.5V

OUT

V

=0.5V or V

OUT

V

=1.0V or VCC - 1.0V

OUT

V

=1.5V or VCC - 1.5V

OUT

VIN=GND or V

CC

- 0.5V

5.0 10 15

3.5 7

11

1.5 3 4

4.95

9.95

14.95

3.5 7

11

1.5 3 4

4.95

9.95

14.95

3.5 7

11

1.5 3 4

4.95

9.95

14.9

V

5

V

I

IN

OL

Maximum LowLevel Output Voltage

Maximum Input

VIN=GND or V

VIN= GND or V

CC

5.0 10 15

0.05

18 ±0.1 ±0.1 ±1.0 µA

V

Leakage Current

I

CC

I

OL

I

OH

Maximum Quiescent Supply Current (per Package)

Minimum Output Low (Sink) Current

Minimum Output High (Source) Current

VIN= GND or V

VIN= GND or V UOL=0.4 V UOL=0.5 V UOL=1.5 V

VIN= GND or V UOH=2.5 V UOH=4.6 V UOH=9.5 V UOH=13.5 V

CC

5.0 10 15 20

5.0 10 15

5.0

5.0 10 15

5 10 20

100

0.64

1.6

4.2

-2.0

-0.64

-1.6

-4.2

5 10 20

100

0.51

1.3

3.4

-1.6

-0.51

-1.3

-3.4

150 300 600

3000

0.36

0.9

2.4

-1.15

-0.36

-0.9

-2.4

µA

mA

SL

System Logic

SL4017B

Semiconductor

AC ELECTRICAL CHARACTERISTICS(C

=50pF, RL=200kΩ, Input tr=tf=20 ns)

L

V

CC

Guaranteed Limit

Symbol Parameter V ≥-55°C 25°C ≤125°CUnit

t

PLH

TLH

PLH

f

max

, t

Maximum Clock Frequency 5.0

Maximum Propagation Delay, Clock to

PHL

Decode Output (Figure 1)

Maximum Propagation Delay, Clock to

PHL

Carry Output (Figure 1)

Maximum Output Transition Time,

THL

Carry Output or Decode Output (Figure

1) Maximum Propagation Delay, Reset to

PHL

Carry Output or Decode Output (Figure

1)

10 15

5.0 10 15

2.5 5

5.5

650 270 170

600 250 160

200 100

80

530 230 170

2.5 5

5.5

650 270 170

600 250 160

200 100

80

530 230 170

1.25

2.5

2.75

1300

540 340

1200

500 320

400 200 160

1060

460 340

MHz

ns

C

TIMING REQUIREMENTS (V

Maximum Input Capacitance - 5 pF

IN

=5.0V±10%, CL=50pF, Input tr=tf=20 ns, RL=200kΩ )

CC

V

CC

Guaranteed Limit

Symbol Parameter V ≥-55°C 25°C ≤125°CUnit

t

w

r, tf

Minimum Pulse Width, Clock (Figure 1) 5.0

10 15

Maximum Input Rise and Fall Times, Clock (Figure 1)

5.0 10

200

90 60

UNLIMITED

200

90 60

400 180 120

15

t

w

rem

Minimum Pulse Width, Reset (Figure

1)

Minimum Removal Time, Reset (Figure 1)

5.0 10 15

260 110

60

400 280 150

260 110

60

400 280 150

520 220 120

800 560 300

ns

µs

ns

SL

System Logic

SL4017B

Semiconductor

t

SU

Minimum Setup Time, Clock Inhibit to Clock (Figure 1)

5.0 10 15

230 100

70

230 100

70

460 200 140

ns

SL

System Logic

Semiconductor

Figure 1. Switching Waveforms

SL4017B

Timing diagram

SL

System Logic

SL4017B

Semiconductor

EXPANDED LOGIC DIAGRAM

SL

System Logic