Datasheet SL4015BD, SL4015BN Datasheet (SLS)

SL4015B

Semiconductor

Dual 4-Stage Static Shift Register

High-Voltage Silicon-Gate CMOS

The SL4015B consists of two identical, independent, 4-stage serialinput/parallel-output registers. Each register has independent CLOCK and RESET inputs as well as a single serial DATA input. “Q” outputs are available from each of the four stages on both registers. All register stages are D-type, master-slave flip-flops. The logic level present at the DATA input is transferred into the first register stage and shifted over one stage at each positive-going clock transition. Resetting of all stages is accomplished by a high level on the reset line. Register expansion to 8 stages using one SL 4015B package, or to more than 8 stages using additional SL4015B’s is possible.

• Operating Voltage Range: 3.0 to 18 V

• Maximum input current of 1 µA at 18 V over full package-

temperature range; 100 nA at 18 V and 25°C

• Noise margin (over full package temperature range):

1.0 V min @ 5.0 V supply

2.0 V min @ 10.0 V supply

ORDERING INFORMATION

SL4015BN Plastic

SL4015BD SOIC

TA = -55° to 125° C for all packages

PIN ASSIGNMENT

LOGIC DIAGRAM

PIN 16=V

PIN 8= GND

2.5 V min @ 15.0 V supply

CC

FUNCTION TABLE

Inputs Outputs

Clock Data Reset Q1 Q

L L L Q H L H Q X L No change

X X H L L X = don’t care

n

n-1

SLS

System Logic

SL4015B

Semiconductor

MAXIMUM RATINGS

*

Symbol Parameter Value Unit

V

CC

V

IN

V

OUT

I

IN

P

DC Supply Voltage (Referenced to GND) -0.5 to +20 V DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Input Current, per Pin ±10 mA Power Dissipation in Still Air, Plastic DIP+

D

SOIC Package+ Power Dissipation per Output Transistor 100 mW

D

750 500

Tstg Storage Temperature -65 to +150 °C

T

Lead Temperature, 1 mm from Case for 10 Seconds

L

260 °C

(Plastic DIP or SOIC Package)

*

Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C

SOIC Package: : - 7 mW/°C from 65° to 125°C

mW

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

V

CC

VIN, V

OUT

T

A

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and V GND≤(VIN or V

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

DC Supply Voltage (Referenced to GND) 3.0 18 V DC Input Voltage, Output Voltage (Referenced to GND) 0 V

CC

Operating Temperature, All Package Types -55 +125 °C

should be constrained to the range

OUT

)≤VCC.

OUT

V

SLS

System Logic

.

SL4015B

Semiconductor

DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)

V

CC

Guaranteed Limit

Symbol Parameter Test Conditions V ≥-55°C 25°C ≤125°CUnit

V

OH

V

I

IN

OL

Minimum High-Level

IH

Input Voltage

Maximum Low -Level

IL

Input Voltage

Minimum High-Level Output Voltage

Maximum Low-Level Output Voltage

Maximum Input

V

= 0.5 V or V

OUT

V

= 1.0 V or V

OUT

V

= 1.5 V or V

OUT

V

= 0.5 V or V

OUT

V

= 1.0 V or V

OUT

V

= 1.5 V or V

OUT

VIN=GND or V

VIN= GND or V

CC

CC CC CC

- 0.5V

- 1.0 V

- 1.5V

- 0.5V

- 1.0 V

- 1.5V

5.0 10 15

3.5 7

11

1.5 3 4

4.95

9.95

14.95

0.05

3.5 7

11

1.5 3 4

4.95

9.95

14.95

0.05

3.5 7

11

1.5 3 4

4.95

9.95

14.95

0.05

18 ±0.1 ±0.1 ±1.0 µA

V

Leakage Current

I

CC

Maximum Quiescent Supply Current (per Package)

VIN= GND or V

CC

5.0 10 15 20

5 10 20

100

5 10 20

100

150 300 600

3000

µA

I

OL

I

OH

Minimum Output Low (Sink) Current

Minimum Output High (Source) Current

VIN= GND or V UOL=0.4 V UOL=0.5 V UOL=1.5 V

VIN= GND or V UOH=2.5 V UOH=4.6 V UOH=9.5 V UOH=13.5 V

CC

5.0 10 15

CC

5.0

5.0 10 15

0.64

1.6

4.2

-2

-0.64

-1.6

-4.2

0.51

1.3

3.4

-1.6

-0.51

-1.3

-3.4

0.36

0.9

2.4

-1.15

-0.36

-0.9

-2.4

mA

SLS

System Logic

SL4015B

Semiconductor

AC ELECTRICAL CHARACTERISTICS(C

=50pF, RL=200kΩ, Input tr=tf=20 ns)

L

V

CC

Guaranteed Limit

Symbol Parameter V ≥-55°C 25°C ≤125°C Unit

t

max

t

, t

PHL

t

PHL

t

, t

THL

C

IN

TIMING REQUIREMENTS(C

Maximum Clock Frequency (Figure 1) 5.0

Maximum Propagation Delay, Clock to Q (Figure1)5.0

PLH

Maximum Propagation Delay, Reset to Q (Figure2)5.0

Maximum Output Transition Time, Any Output

TLH

(Figure 1)

10 15

5.0 10 15

3 6

8.5

320 160 120

400 200 160

200 100

80

3 6

8.5

320 160 120

400 200 160

200 100

80

Maximum Input Capacitance - 7.5 pF

=50pF, RL=200 kΩ, Input tr=tf=20 ns)

L

1.5 3

4.25 640

320 240

800 400 320

400 200 160

MHz

ns

V

CC

Guaranteed Limit

Symbol Parameter V ≥-55°C 25°C ≤125°C Unit

t

tr, t

w

su

Minimum Pulse Width, Clock (Figure 1) 5.0

10 15

Minimum Pulse Width, Reset (Figure 2) 5.0

10 15

Minimum Setup Time, Data to Clock (Figure 3)

5.0 10 15

Minimum Hold Time, Clock to Data

h

(Figure 3)

5.0 10 15

Maximum Input Rise and Fall Time (Figure 1) 5.0

f

10 15

180

80 50

200

80 60

70 40 30

0 0 0

15

6 2

180

80 50

200

80 60

70 40 30

0 0 0

15

6 2

360 160 100

400 160 120

140

80 60

0 0 0

30 12

4

ns

µs

SLS

System Logic

.

SL4015B

Semiconductor

Figure 1. Switching Waveforms Figure 2. Switching Waveforms

Figure 3. Switching Waveforms

EXPANDED LOGIC DIAGRAM

( 1/2 of the Device)

SLS

System Logic