Supersedes October 1996 version in Media IC Handbook HB4599-1.0DS3842 - 4.1 March 1997
The SL1710 is a quadrature downconverter, intended for
use with both Professional and Consumer Digital Satellite
Applications.
The device contains high linearity, low noise amplifiers,
quadrature mixers, plus an on-chip oscillator, operating
between 350MHz and 500MHz, which may be synthesised via
the differential prescaler outputs.
An AGC with 18dB gain control is provided to cope with a
wide range of input signal levels.
I and Q outputs are via low impedance single ended
amplifiers. These may be connected to a dual channel analog
to digital converter such as the PCA916, VP216, VP215 or
VP213, via a suitable anti-alias filter.
AGC
IOUT
VEEA
IFINB
IFIN
VCCA
QOUT
VEEC
1
16
SL1710
VCCB
VCODIS
VCO B
VCO A
VEEB
PSCAL
PSCALB
VCCC
MP16
FEATURES
■ Wide input frequency range (350-500MHz)
■ On chip oscillator with varactor tuning or SAW
resonator operation capability
■ Nominal 40dB conversion gain from IF input to I
and Q outputs
■ AGC amplifier with 18dB gain control range
■ I to Q phase match 90°C to ± 2°, gain match
better than 1dB
■ Low impedance I and Q single ended outputs,
with 15MHz ± 1dB BW
■ Divide by 32 prescaler outputs
■ Suitable for QPSK and up to 64QAM systems
AGC
IFIN
IFINB
Fig. 1 Pin allocation top view
ORDERING INFORMATION
SL1710/KG/MPAS
SL1710/KG/MPAD (Tape and Reel)
ABSOLUTE MAXIMUM RATINGS
Storage temperature-55°C to +150°C
Junction temperature-29°C to +150°C
Supply voltage-0.3 to 7.0V
Voltage at any other pin-0.3 to +7.0V
APPLICATIONS
■ Consumer digital satellite decoders
■ Professional digital satellite decoders
■ Communication systems
AGC
I OUT
VCODIS
VCOA
VCOB
LO
0 deg90 deg
Quadrature
generator
Fig.2. SL1710 block diagram
AGC
÷32
Q OUT
PSCAL
PSCALB
Page 2
SL1710
ELECTRICAL CHARACTERISTICS
T
= 0oC to +80oC, Vee= 0V, Vcc = 4.75 to 5.25 V, Fif = 479.5 MHz, IF bandwidth ± 15 MHz, output amplitude -11dBV
amb
These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature
RF freq range4, 5350500MHz
Impedance4, 575ohm@ 480MHz. Fig. 4
VSWR4, 51.7@ 480MHz. Fig. 4
Noise Figure4, 519dBAGC at maximum gain
Noise Figure variation with4, 50.51dB/dB
gain
VCO
VCO freq (fo) control range13, 14350500MHzExternal tank circuit with varicap
Phase noise13, 14-85dBc/Hz@ 10kHz from fo. but measured in
I or Q output. Note
Fo sensitivity to V
CC
13, 142MHz/Volt Fixed external components and no
control loop
Fo sensitivity to temperature13, 1440KHz/°CUncompensation
Prescaler output, VOH10, 11V
VOL10, 11V
-0.96VoltAt 25°C
CC
-1.65Volt
CC
Prescaler output duty cycle10, 114060%Under maximum load conditions
Fig. 5
AGC
Gain, Vagc = +2.5V40dB
Temp stability of gain1±2dBFor any gain setting 0V to 5V
Gain, Vagc = +0.5V144dBSee Fig.6
Gain, Vagc = + V
-0.5V132dBSee Fig.6
CC
AGC range18dB
I Q outputs480MHz local oscillator, 481 to
495MHz RF input @ -51dBV
Gain set to give -11dBV,
1-15MHz baseband output into
maximum load. Fig. 7
Output impedance2, 78ohmFig. 8
Output clipping level2, 71.5V p-p
I phase lag with respect to Q2, 7889092degs1 -15MHz
IQ crosstalk20dB
Output amplitude match2, 71dBI releative to Q, 1 -15MHz
Baseband flatness2, 7±1dB1-15MHz, 1kΩ 15pF load
Two tone 3rd order intercept2, 7+3dBVReferred to output. @ 1MHz
pointOutput load 1kohm, 15pF, all
AGC settings, 0.7V pk-pk output
Im32, 728dBc
LO, and Sputii in IQ outputs2, 7-30dBV1-100MHz
(1, 2)
2
Page 3
SL1710
ELECTRICAL CHARACTERISTICS (continued)
T
= 0oC to 80oC, Vee= 0V, Vcc = 4.75 to 5.25 V, These characteristics are guaranteed by either production test or design.
amb
They apply within the specified ambient temperature and supply voltage unless otherwise stated.
Value
CharacteristicPinMinTypMaxUnitsConditions
Prescaler sidebands2, 7-50-47dBVMeasured in IQ outputs
Power supply rejection2, 72530dBAttenuation VCC to IQ outputs,
over 0-500kHz
Notes:
1. The choice of L will have an effect on phase noise of the VCO
2. Target value at fo=500MHz, L (tank)=10nH, Q (tank, unloaded)=50, SSB
DESCRIPTION
The SL1710 is a quadrature downconverter, intended for
high linearity, low noise digital satellite applications. It contains
all the elements necessary, with the exception of the VCO
tuning components, to extract baseband I and Q signals from
a QPSK or QAM IF input signal.
A block diagram for the SL1710 is shown in Fig. 2.
In normal consumer digital satellite applications, the device
is fed via a SAW filter, centred at the standard IF of 479.5MHz.
A filtered single channel is therefore presented to the device,
at a typical level of -51dBV. An AGC is included with 18dB of
gain control, which is guaranteed to provide an overall conversion gain between 30 and 45dB from the RF input to the I and
Q outputs.
The quadrature mixers are fed from an on-chip oscillator
which is centred on the incoming IF. The oscillator external
tuning network should be fully symmetric, to ensure optimum
gain and phase match.
Single ended I and Q amplifiers are provided, which output
a 760mV (p/p) signal, assuming a nominal -51dBV input signal
and 40dB gain, suitable for driving a dual channel ADC such as
the PCA 869, PCA 913 and PCA 916 via an anti-alias filter (see
application notes). The ADC is normally AC coupled via two
capacitors (typically 4.7µF).
The SL1710 also includes divide by 32 prescaler output.
These may be fed to an external PLL circuit which can be used
to drive the on-chip oscillator, thus forming a complete control
loop.
The VCO can be disabled by applying 0V to pin 15.
3
Page 4
SL1710
CH PUMP
1
XTAL1
2
XTAL2
3
SDA
4
SCL
5
P76P67P5
8
P4
9
P310NC11Vcc12RF I/P13RF I/P14Vee
15
DRV
16
IC2 SP5611
AGC
1
IOUT
2
VEEA
3
IFINB
4
IFIN
5
VCCA
6
QOUT
7
VEEC
8
VCCC
9
PSCALB
10
PSCAL
11
VEEB
12
VCOA
13
VCOB
14
VCODIS
15
VCCB
16
/32
Oscillator
I Mixer
Q Mixer
IC1 SL1710
L1
12nH
C12
3p9
D1
BB811
C13
3p3
1
42
3
LK2
T2
BCW31
5V
R4
110R
SK4
Q CH O/P
C11
220nF
SW1
VCO DISABLE
R2
4K7
5V
SK1
RF IN
C1
100nF
C2
100nF
R1
75R
L5
4u7
L6
4u7
C3
100nF
C4
100pF
C5
100nF
C6
100pF
C7
100nF
C8
100pF
+
C9
47uF
5V
5V
5V5V
VR1
1K
R5
680R
R6
4K7
R7
680R
T1
BCW31
1
42
3
LK1
R3
110R
SK3
I CH O/P
C10
220nF
C14
10nF
C15
10nF
C19
220nF
C20
47nF
R8
22K
R9
22K
R10
4K7
T3
BCW31
R11
10K
C21
10nF
30V
C18
18pF
X1
4 MHz
C16
10nF
C17
100pF
1
2
3
CN1
DC POWER
30V
5V
SDA5
3
5V04GND5SCL5
6
SK4
I2C
5V
Fig. 3 Demonstration board circuit diagram
4
Page 5
+j1
SL1710
+j0.5
+j0.2
0.50.210
–j0.2
–j0.5
START 350 MHzSTOP 650 MHz
Fig.4 Typical RF input impedance
APPLICATION NOTES
These application notes should be read in conjunction with
the circuit diagram Fig 3. and the PCB layout illustrated in Figs
9 and 10. An alternative oscillator configuration using a SAW
Resonator is shown in the circuit diagram Fig. 11 and the PCB
layout illustrated in Figs 12 and 13. These boards have been
designed to permit the initial evaluation of the SL1710
performance.
VARACTOR TUNED
The application detailed in Fig.3 uses a synthesised VCO.
The tuning range of the oscillator is;
Varactor line Voltage.Oscillator Frequency
5 Volts458MHz
30 Volts504MHz
This configuration gives a VCO sensitivity of 1.84MHz/
Volt. The inductor L1 is a 12nF surface mount component.
Different VCO centre frequencies and sensitivities can be
achieved by changing the values of L1, C12 and C13.
The VCO frequency is controlled by the SP5611
synthesiser which is programmed via an I2C bus. The RF
input to the synthesiser is from the SL1710 prescaler outputs
via RF inductors L3 and L4.
+j2
+j5
25
–j5
–j2
–j1
Marker
Zreal
Zimag
1 480MHz
= 75.7
= –36.4
SAW RESONATOR OSCILLATOR
The application detailed in Fig. 11 shows an SL1710 with
a SAW Resonator controlled oscillator. In this instance the
frequency accuracy and stability of the oscillator are
determined by the Saw Resonator. The PCB detailed in Figs.
12 and 13 is designed to accommodate the following SAWR;
ManufacturerPart No
MURATA SAR479.45MB10X200
PRESCALER OUTPUTS
The VCO frequency/32 is available at the differential
prescaler outputs pins 10 and 11. This enables the on board
VCO to be synthesised via a PLL.
VCO DISABLE
The on-chip oscillator can be disabled by connecting the
VCO Disable (pin 15) to ground and enabled by connecting the
pin to VCC via a 4K7 pull up resistor.
AGC
The DC voltage measured at TP1 should be adjusted using
VR1 to read 2.5 volts with respect to VEE. this voltage equates
to the nominal centre of the AGC control curve. The control
voltage applied to pin 1 can be varied between 0.5 Volts
(maximum gain) and V
-0.5 Volts minimum gain)
CC
5
Page 6
SL1710
I & Q OUTPUTS
The I and Q output stages of the SL1710 are sensitive to the
loads connected to them. To avoid degrading the output
signals resistive loads connected to these pins should always
be 1KΩ or greater with a parallel capacitance of 15pF or less
For evaluation purposes this makes the output unsuitable
for connection to test equipment via normal coaxial cables. To
alleviate this problem the application board is fitted with
emitter follower buffer amplifiers which allow the connection of
loads as low as 50Ω via coaxial cables without loading the
output stages of the SL1710. These buffer amplifiers can be
either connected in circuit, or bypassed by changing the
position of Links 1 and 2.
This technique may be used in a real application where the
SL1710 is used to drive and ADC via an anti-alias filter. Great
care must be taken to ensure that the loading conditions
stated above are not exceeded when designing the anti-alias
filter section. Use of an emitter follower buffer is the easiest
way to alleviate this constraint.
With the AGC voltage adjusted to 2.5 Volts apply an input
signal to the IF IN (pin 5) and monitor the Base Band output
level at the I and Q outputs. Adjust the RF input level until an
output level of 760mV pk-pk is achieved. For best
performance this level should not exceeded.
Vcc 2
2K
PRESCALER
OUTPUT
15pF
Fig.5 Maximum prescaler output load
6
Page 7
50.00
45.00
40.00
33.00
GAIN (dB)
30.00
25.00
IQ OUTPUT
012345
V
agc (V)
Fig. 6 AGC operation
SL1710
Marker
Freq
1 500KHz 3.5
2 15MHz 4.5
3 30MHz 56
Zreal Zimag
Ω 0.5
Ω 32
Ω 92
ART .010 MHz
ST
15pF
1KΩ
Fig. 7 Maximum IQ output load
+j1
Ω
Ω
Ω
+j0.2
–j0.2
+j0.5
1
–j0.5
2
0.50.210
25
–j1
+j2
+j5
3
–j5
–j2
30.MHz
STOP
Fig. 8 Output impedance
7
Page 8
SL1710
Fig. 9 Demonstration PCB top view
Fig. 10 Demonstration PCB bottomview
8
Page 9
T1
+
C7
C9
C8
C12
1nF
BCW31
LK1
47uF
100nF
100pF
SL1710
4
1nF
T2
C13
BCW31
LK2
SW1
R4
110R
423
1
SK3
Q CH OUT
C11
220nF
R2
4K7
5V
3
R3
110R
SAW1
C10
SK2
220nF
4
3
2
1
SL1710
IC1
I CH OUT
100pF
C14
2
13
IOUT
VCOA
SAW
RESONATOR
1
14
VCOB
Osc
7
2
C15
QOUT
5V
100pF
15
VCODIS
CN1
5V
POWER
5V
C6
100nF
5V
C5
100pF
C4
100nF
C3
100pF
1K
VR1
R5
680R
3
2
1
5V
5V
R6
4K7
R7
680R
I Mixer
9
VCCC
16
VCCB
6
VCCA
TP1
AGC VOLTS
C1
SK1
1
AGC
100nF
IF IN
/32
IFINB
IFIN
5
PSCALB
PSCAL
4
11
10
C2
100nF
R1
75R
Q Mixer
VEEC
VEEB
VEEA
VCO DISABLE
8
12
3
Fig. 11 SL1710 I & Q downconverter with saw resonator
9
Page 10
SL1710
Fig. 12
10
Fig. 13
Page 11
Page 12
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