Datasheet SL1062AN Datasheet (SLS)

SL1062A

System Logic

Semiconductor

SLS

Low Voltage Transmission Circuit
with Dialler Interface

The SL1062A is an integrated circuit that perform all speech and line
interface functions required in fully electronic telephone sets. They
perform electronic switching between dialling and speech. The ICs
operate at line voltage down to 1.6 V DC (with reduced performance)
to facilitate the use of more telephone sets connected in parallel.

• Low DC line voltage: operates down to 1.6 V (excluding polarity

guard)

• Voltage regulator with adjustable static resistance

• Provides a supply for external circuits

• Symmertical high-impedance inputs (64 KΩ) for dynamic,

magnetic or piezo-electric microphones

• Asymmetrical high-impedance input (32 KΩ) for electret

microphones

• DTMF signal input with confidence tone

• Mute input for pulse or DTMF dialing:

active LOW (MUTE)

• Receiving amplifier for dynamic, magnetic or piezo-electric

earpieces

• Large gain setting ranges on microphone and earpiece amplifiers

• Line loss compensation (line current dependent) for microphone

and earpiece amplifiers

• Gain control curve adaptable to exchange supply

• DC line voltage adjustment facility

ORDERING INFORMATION

SL1062AN Plastic

TA = -25° to 75° C

for package

PIN ASSIGNMENT

BLOCK DIAGRAM

SL1062A

System Logic

Semiconductor

SLS

PIN DESCRIPTION

Pin No Designation Description

1 LN positive line terminal
2 GAS1 gain adjustment; transmitting amplifier
3 GAS2 gain adjustment; transmitting amplifier
4 QR non-inverting output; receiving amplifier
5 GAR gain adjustment; receiving amplifier
6 MIC- inverting microphone input
7 MIC+ non-inverting microphone input
8 STAB current stabilizer

9 VEE negative line terminal
10 IR receiving amplifier input
11 DTMF dual-tone multi -frequency input
12 MUTE mute input
13 VCC possitive supply decoupling
14 REG voltage regulator decoupling
15 AGC automatic gain control input
16 SLPE slope (DC resistance) adjustment

FUNCTIONAL DESCRIPTION

Supplies VCC, LN, SLPE, REG and STAB

Power for the IC and its peripheral circuits is usually
obtained from the telephone line. The supply voltage
is derived from the line via a dropping resistor and
regulated by the IC. The supply voltage VCC may also
be used to supply external circuits e.g. dialling and
control circuits.

Decoupling of the supply voltage is performed by a
capacitor between VCC and VEE. The internal voltage
regulator is decoupled by a capacitor between REG
and VEE.

The DC current flowing into the set is determined by
the exchange supply voltage V

exch

, the feeding bridge

resistance R

exch

and the DC resistance of the

telephone line R

line

.

The circuit has an internal current stabilizer operating
at a level determined by a 3.6 KΩ resistor connected
between STAB and VEE (see Fig.1).

Figure 1. Supply arrengement

When the line current (I

line

) is more than 0.5 mA
greater than the sum of the IC supply current (ICC)
and the current draw by the peripheral circuitry
connected to VCC (Ip) the excess current is shunted to
VEE via LN.

The regulated voltage on the line terminal (VLN) can
be calculated as:

VLN = V

ref

+ I

SLPE

x R9

VLN = V

ref

+ ((I

line

- ICC - 0.5 x 10-3 A) -Ip) x R9

SL1062A

System Logic

Semiconductor

SLS

V

ref

is an internally generated temperature
compensated reference voltage of 3.7 V and R9 is an
external resistor connected between SLPE and VEE.

In normal use the value of R9 would be 20Ω.
Changing the value of R9 will also affect microphone

gain, DTMF gain, gain control characteristics,
sidetone level, maximum output swing on LN and the
DC characteristics (especially at the lower voltages).

Under normal conditions, when
I

SLPE

>>ICC + 0.5 mA + Ip, the static behaviour of the
circuit is that of a 3.7 V regulator diode with an
internal resistance equal to that of R9. In the audio
frequency range the dynamic impedance is largely
determined by R1. Fig.2 shows the equivalent
impedance of the circuit.

Leq = C3 x R9 x R

P

RP = 16.2 KΩ

Figure 2. Equivalent impedance circuit

At line currents below 9 mA the internal reference
voltage is automatically adjusted to a lower value
(typically 1.6 V at 1 mA) This means that more sets
can be operated in parallel with DC line voltages
(excluding the polarity guard) down to an absolute
minimum voltage of 1.6 V.

At line currents below 9 mA the circuit has limited
sending and receiving levels. The internal reference
voltage can be adjusted by means of an external
resistor (RVA). This resistor when connected between
LN and REG will decrease the internal reference
voltage and when connected between REG and SLPE
will increase the internal reference voltage.

Microphone inputs MIC+ and MIC- and gain pins
GAS1 and GAS2

The circuit has symmetrical microphone inputs. Its
input impedance is 64 KΩ (2 x 32 KΩ) and its voltage
gain is typically 52 dB (when R7 = 68 KΩ, see
Figure 3). Dynamic, magnetic, piezo-electric or
electret (with built-in FET source followers) can be
used.

The gain of the microphone amplifier can be adjusted
between 44 dB and 52 dB to suit the sensitivity of
the transducer in use. The gain is proportional to the
value of R7 which is connected between GAS1 and
GAS2.

Stability is ensured by two external capacitors, C6
connected between GAS1 and SLPE and C8
connected between GAS1 and VEE. The value of C6
is 100 pF but this may be increased to obtain a first­order low-pass filter. The value of C8 is 10 limes the
value of C6. The cut-off frequency corresponds to
the time constant R7 x C6.

Input MUTE

When MUTE is LOW or open circuit, the DTMF
input is enabled and the microphone and receiving
amplifier inputs are inhibited. The reverse is true
when MUTE is HIGH, MUTE switching causes only
negligible clicking on the line and earpiece output. If
the number of parallel sets in use causes a drop in
line current to below 6 mA the DTMF amplifier
becomes active independent to the DC level applied
to the MUTE input.

Dial-tone multi-frequency input DTMF

When the DTMF input is enabled dialling tones may
be sent on to the line. The voltage gain from DTMF
to LN is typically 25.5 dB (when R7 = 68 KΩ) and
varies with R7 in the same way as the microphone
gain. The signalling tones can be heard in the
earpiece at a low level (confidence tone).

Receiving amplifier IR, QR and GAR

The receiving amplifier has one input (IR) and a non­inverting output (QR). The IR to QR gain is typically
31 dB (when R4 = 100 KΩ). It can be adjusted
between 20 and 31 dB to match the sensitivity of the
transducer in use. The gain is set with the value of
R4 which is connected between GAR and QR. The
overall receive gain, between LN and QR, is
calculated by subtracting the anti-sidetone netwo rk
attenuation (32 dB) from the amplifier gain. Two
external capacitors, C4 and C7, ensure stability. C4 is
normally 100 pF and C7 is 10 times the value of C4.
The value of C4 may be increased to obtain a first­order low-pass filter. The cut-off frequency will
depend on the time constant R4 x C4.

The output voltage of the receiving amplifier is
specified for continuous-wave drive. The maximum
output voltage will be higher under speech
conditions where the peak to RMS ratio is higher.

SL1062A

System Logic

Semiconductor

SLS

Automatic gain control input AGC

Automatic line loss compensation is achieved by
connecting a resistor (R6) between AGC and VEE.

The automatic gain control varies the gain of the
microphone amplifier and the receiving amplifier in
accordance with the DC line current. The control
range is 5.8 dB which corresponds to a line length of
5 km for a 0.5 mm diameter twisted-pair copper cable
with a DC resistance of 176 Ω/km and average
attenuation of 1.2 dB/km. Resistor R6 should be
chosen in accordance with the exchange supply
voltage and its feeding bridge resistance (see
Table 1).

Table 1 Values of resistor R6 for optimum line-loss
compensation at various values of exchange supply
voltage (V

exch

) and exchange feeding bridge

resistance (R

exch

); R9 = 20 Ω.

V

exch

(V)

400

R

exch

(Ω)

600

R

exch

(Ω)

800

R

exch

(Ω)

1000

R

exch

(Ω)

R6(KΩ)

36 100 78.7 - ­48 140 110 93.1 82
60 - - 120 102

The ratio of start and stop currents of the AGS curve
is independent of the value of R6. If no automatic
line-loss compensation is required the AGS pin may
be left open-circuit. The amplifiers, in this condition,
will give their maximum specified gain.

Sidetone suppression

The anti-sidetone network, R1//Z

line

, R2, R3, R8,

R9 and Z

bal

(see Fig4) suppresses the transmitted
signal in the earpiece. Maximum compensation is
obtained when the following conditions are fulfilled:

R9 x R2 = R1 x ( R3 + ) (1)

= (2)

It fixed values are chosen for R1, R2, R3 and R9, then
condition (1) will always be fulfilled when
R8//Z

bal

<<R3.

To obtain optimum sidetone suppression, condition
(2) has to be fulfilled which results in:

Z

bal

= x Z

line

= k x Z

line

Where k is a scale factor; k =

The scale factor k, dependent on the value of R8, is
chosen to meet the following criteria:

• compatibility with a standard capacitor from the
E6 or E12 range for Z

bal

• Z

bal

// R8<<R3 fulfilling condition (a) and thus

ensuring correct anti -sidetone bridge operation

• Z

bal

+ R8>>R9 to avoid influencing the transmit

gain.
In practise Z

line

varies considerably with the line type

and length. The value chosen for Z

bal

should
therefore be for an average line length thus giving
optimum setting for short or long lines.

MAXIMUM RATINGS*

Symbol Parameter Condition Min Max Unit

VLN Positive continuous line voltage - 12 V

V

LN(R)

Repetitive line voltage during

switch-on or line interruption

- 13.2 V

V

LN(RM)

Repetitive peak line voltage for a

1 ms pulse per 5 s

R9 = 20 Ω; R10 = 13 Ω;
see Fig.5

- 28 V

I

line

Line current R9 = 20 Ω - 140 mA

VIN positive input voltage - VCC+0.7 V

negative input voltage - -0.7 V

PD Total power dissipation R9 = 20 Ω; note 1 - 666 mW

Tstg Storage temperature -40 +125 °C

*

Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.
Note 1. Calculated for the maximum operating temperature specified (T

amb

= 75°C) and a maximum junction

temperature of 125°C.

R8 x Z

bal

R8 +Z

bal

R8
R1

Z

bal

Z

bal

+ R8

R8
R1

Z

line

Z

line

+ R1

Input voltage on all other pins

SL1062A

System Logic

Semiconductor

SLS

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Conditions Min Typ Max Unit

I

line

Operating line current

normal operation
with reduced performance

11

1

-

-

140

11

mA
mA

VCC Supply voltage for

peripherals

I

line

= 15 mA
Ip = 1.2 mA; MUTE = LOW
Ip = 0 mA; MUTE = LOW

2.2

-

-

3.4

-

-

V
V

GV Voltage gain

microphone amplifier
receiving amplifier

44
20

-

-

52
31

dB
dB

T

amb

Operating ambient

temperature

-25 - +75 °C

Line loss compensation

∆GV Gain control - 5.8 - dB

V

exch

Exchange supply voltage 36 - 60 V

R

exch

Exchange feeding bridge

resistance

0.4 - 1 KΩ

This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and V

OUT

should be constrained to the range

GND≤(VIN or V

OUT

)≤VCC.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.

ELECTRICAL CHARACTERISTICS(I

line

= 11 to 140 mA; VEE = 0 V; f = 800 Hz;T

amb

= 25°C; unless

other specified)

Symbol Parameter Test Conditions Guaranteed Limits Unit

Min Typ Max

Supplies LN and VCC (pins 1 and 13)

VLN Voltage Drop Over Circuit

between LN and VEE

MIC Inputs Open-Circuit
I

line

= 1 mA

I

line

= 4 mA

I

line

= 15 mA

I

line

= 100 mA

I

line

= 140 mA

-

-

3.56

4.9

-

1.6

1.9

-

-

-

-

-

4.25

6.5

7.5

V

∆VLN/∆T Variation with Temperature I

line

= 15 mA - -0.3 - mV/K

VLN Voltage Drop Over Circuit

between LN and VEE with
External Resistor RVA

I

line

= 15 mA
RVA (LN to REG)=68KΩ
RVA (LN to SLPE)=39KΩ

3.5

4.5

V

ICC Supply Current VCC = 2.8 V 1.35 mA

(continued)

SL1062A

System Logic

Semiconductor

SLS

ELECTRICAL CHARACTERISTICS(I

line

= 11 to 140 mA; VEE = 0 V; f = 800 Hz;T

amb

= 25°C; unless

other specified)

Symbol Parameter Test Conditions Guaranteed Limits Unit

Min Typ Max

Microphone inputs MIC- and MIC+ (pins 6 and 7)

Zi Input Impedance

differential
single-ended

between MIC- and MIC+
MIC- or MIC+ to VEE

-

-

64
32

-

-

KΩ

CMRR Common Mode Rejection

Ratio

- 82 - dB

Gv Voltage Gain MIC+ or MIC-

to LN

I

line

= 15 mA
R7 = 68 KΩ

50.5 53.5 dB

∆Gvf Gain Variation with

Frequency Reference to 800
Hz

f = 300 and 3400 Hz - ±0.2 - dB

∆GvT Gain Variation with

Temperature Referenced to
25°C

without R6; I

line

=50 mA;

T

amb

= -25 and +75°C

- ±0.2 - dB

DTMF input (pin 11)

Zi Input Impedance - 20.7 - KΩ

Gv Voltage Gain from DTMF to

LN

I

line

15 mA; R7 = 68 KΩ 24.0 - 27.0 dB

∆Gvf Gain Variation with

Frequency Reference to
800 Hz

f = 300 and 3400 Hz - ±0.2 - dB

∆GvT Gain Variation with

Temperature Referenced to
25°C

I

line

=50 mA;
T

amb

= -25 and +75°C

- ±0.2 - dB

Gain Adjustment Inputs GAS1 and GAS2 (pins 2 and 3)

∆Gv Transmitting Amplifier Gain

Variation by Adjustment of
R7 between GAS1 and GAS2

-8 - 0 dB

Sending Amplifier Output LN (pin 1)

V

LN(rms)

Output Voltage (RMS value) THD = 10%

I

line

= 4 mA

I

line

= 15 mA

-

1.7

0.8

-

-

-

V

V

no(rms)

Noise Output Voltage (RMS

value)

I

line

= 15 mA; R7 =68KΩ
200 Ω between MI C- and
MIC+

- -69 - dBmp

Receiving Amplifier Input IR (pin 10)

Zi Input Impedance - 21 - KΩ

Receiving amplifier output QR (pin 4)

Zo Output Impedance - 4 - Ω

Gv Voltage Gain from IR to QR I

line

15 mA; RL = 300 Ω
(from pin 9 to pin 4)

29.5 - 32.5 dB

(continued)

SL1062A

System Logic

Semiconductor

SLS

ELECTRICAL CHARACTERISTICS(I

line

= 11 to 140 mA; VEE = 0 V; f = 800 Hz;T

amb

= 25°C; unless

other specified)

Symbol Parameter Test Conditions Guaranteed Limits Unit

Min Typ Max

∆Gvf Gain Variation with

Frequency Reference to
800 Hz

f = 300 and 3400 Hz - ±0.2 - dB

∆GvT Gain Variation with

Temperature Referenced to
25°C

without R6; I

line

=50 mA;

T

amb

= -25 and +75°C

- ±0.2 - dB

V

o(rms)

Output Voltage (RMS value) THD = 2%; sine wave drive:

R4 = 100 KΩ;
I

line

= 15 mA; Ip = 0 mA
RL = 150 Ω
RL = 450 Ω

0.22

0.3

-

-

-

-

V

V

o(rms)

Output Voltage (RMS value) THD=10%; R4=100 KΩ; I

line

= 4 mA; RL = 150 Ω

- 15 - mV

V

no(rms)

Noise Output Voltage (RMS

value)

I

line

= 15 mA; R4=100KΩ
IR open-circuit
psophometrically weighted;
RL =300 Ω

- 50 - µV

Gain Adjustment Input GAR (pin 5)

∆Gv Receiving Amplifier Gain

Variation by Adjustment of
R4 between GAR and OR

-11 - 0 dB

Mute Input (pin 12)

VIH HIGH Level Input Voltage 1.5 - VCC V

VIL LOW Level Input Voltage - - 0.3 V

I

MUTE

Input Current - - 15 µA

Raduction of Gain

∆Gv MIC+ or MIC- to LN MUTE = LOW - 70 - dB

Gv Voltage Gain from DTMF to

QR

R4 = 100 KΩ
RL = 300 Ω

- -17 - dB

Automatic Gain Control Input AGC (pin 15)

∆Gv Controlling the Gain from IR

to QR and the Gain from
MIC+, MIC- to LN
Gain Control Range

R6 = 110 KΩ
(between AGC and VEE)
I

line

= 70 mA

-

-5.8

-

dB

I

lineH

Highest Line Current for

Maximum Gain

- 23 - mA

I

lineL

Lowest Line Current for

Minimum Gain

- 61 - mA

SL1062A

System Logic

Semiconductor

SLS

Voltage gain is defined as GV = 20 log

For measuring gain from MIC+ and MIC- the MUTE input should be HIGH.
For measuring the DTMF input, the MUTE input should be LOW or open-circuit.
Inputs not being tested should be open-circuit.

Figure 3. Test circuit for defining SL1062A voltage gain of MIC+, MIC- and DTMF inputs.

Figure 4. Equivalent circuit of SL1062A anti-sidetone bridge

VO
VI

SL1062A

System Logic

Semiconductor

SLS

The diode bridge, the Zener diode and R10 limit the current into, and the voltage across, the circuit during line
transients.
A different protaction arrangement is required for pulse dialling or register recall.
The DC line voltage can be set to a higher value by the resistor RVA (REG to SLPE).

Figure 5. Typical application of SL1062A, with piezo -electric earpiece and DTMF dialling.