Datasheet SK100LVE111E, SK10LVE111E Datasheet (Semtech Corporation)

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Low Voltage 1:9 Differential ECL/PECL
Clock Driver with Enable Input

SK10LVE111E
SK100LVE111E

Preliminary Information

This document contains information on a new product. The parametric
information, although not fully characterized, is the result of testing
initial devices.

Features

• 200 ps Part-to-Part Skew

• 50 ps Output-to-Output Skew

• Differential Design

•VBB Output

• Enable Input

• Voltage and Temperature Compensated Outputs

• Low Voltage VEE Range of –3,0 to –3.8V

• 75KΩ Internal Pulldown Resistors

• Fully Compatible with Motorola MC100LVE111

• Specified Over Industrial Temperature Range:
–40˚C to 85˚C

• ESD Protection of >2000V

• Available in 28-pin PLCC Package

Description

The SK10/1000LVE111E is a low skew 1-to-9 differential driver
designed with clock distribution in mind. The SK10/
100LVE111E’s function and performance are similar to the
SK100E111, with the added feature of low voltage operation.
It accepts one signal input which can be either differential or
single-ended if the VBB output is used. The signal is fanned
out to 9 identical differential outputs. An enable input is also
provided. A High disables the device by focing all Q outputs
Low and all Q* outputs High.

The device is specifically designed, modeled, and produced
with low skew as the key goal. Optimal design and layout serve
to minimize gate-to-gate skew within a device, and
characterization is used to determine process control limits that
ensure consistent tpd distributions from lot to lot. The net result
is a dependable, guaranteed low skew device.

October 6, 1999

Low Voltage 1:9 Differential

ECL / PECL Clock Driver

28 Pin

PLCC Package

of the output(s) being used which, while not being
catastrophic to most designs, will mean a loss of
skew margin.

The SK10/100LVE111E, as with most other ECL
devices, can be operated from a positive VCC
supply in PECL mode. This allows the LVE111E
to be used for high performance clock distribution
in +3.3V systems. Designers can take advantage
of the LVE111E’s performance to distribute low
skew clocks across the backplane or the board.
In a PECL environment, series or Thevenin line
terminations are typically used as they require no
additional power supplies. For systems
incorporating GTL, parallel termination offers the
lowest power by taking advantage of the 1.2V
supply as a terminating voltage.

To ensure that the tight skew specification is met, it is necessary
that both sides of the differential output are terminated into 50Ω,
even if only one side is being used. In most applications, all
nine differential pairs will be used and therefore terminated. In
the case where fewer than nine pairs are used, it is necessary
to terminate at least the output pairs on the same package
side as the pair(s) being used on that side in order to maintain
minimum skew. Failure to do this will result in small
degradations of propagation delay (on the order of 10–20ps)

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Low Voltage 1:9 Differential ECL/PECL
Clock Driver with Enable Input

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SK10LVE111E
SK100LVE111E

EN*

Q0
Q0*

Q1
Q1*

Q2
Q2*

Q3
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Q4

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28

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28 Lead PLCC

(Top View)

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Q5

12

Q5*

Absolute Maximum Ratings (Note 3)

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Low Voltage 1:9 Differential ECL/PECL
Clock Driver with Enable Input

SK10LVE111E
SK100LVE111E

SK10LVE111E ECL DC Electrical Characteristics

(VEE = VEE (min) to VEE (max); VCC = GND) (Notes 1 and 4)

TA = –40˚C TA = 0˚C TA = +25˚C TA = +85˚C

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SK10LVE111E PECL DC Electrical Characteristics

(VCC = VCC (min) to VCC (max); VEE = GND) (Notes 1 and 4)

TA = –40˚C TA = 0˚C TA = +25˚C TA = +85˚C

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Low Voltage 1:9 Differential ECL/PECL
Clock Driver with Enable Input

SK100LVE111E ECL DC Electrical Characteristics

(VEE = VEE (min) to VEE (max); VCC = GND) (Notes 2 and 4)

SK10LVE111E
SK100LVE111E

TA = –40˚C TA = 0˚C TA = +25˚C

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SK100LVE111E PECL DC Electrical Characteristics

(VCC = VCC (min) to VCC (max); VEE = GND) (Notes 2 and 4)

TA = –40˚C

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Low Voltage 1:9 Differential ECL/PECL
Clock Driver with Enable Input

SK10LVE111E
SK100LVE111E

AC Characteristics

(VEE = VEE (min) to VEE (max); VCC = V

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Notes:

1. 10LVE111E circuits are designed to meet the DC specifications shown in the table after thermal equilibrium has been

established.
The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
Outputs are termionated through a 50Ω resistor to –2.0V.

2. The same DC parameter values apply across the full VEE range of –3.0 to –3.8V. Outputs are terminated through a 50Ω

resistor to –2.0V. 100LVE111E circuits are designed to meet the DC specifications shown in the table where transverse airflow
greater than 500 lfpm is maintained.

3. Absolute maximum rating, beyond which device life may be impaired unless otherwise specificed on an individual data sheet.

4. Parametric values specified at:

10LVE111E Series: –3.0 to –3.8V
100 LVE111E Series: –3.0 to –3.8V; PECL Power Supply: +3.0V to +3.8V

5. Guaranteed HIGH signal for all inputs.

6. Guaranteed LOW signal for all inputs.

7. These values are for VCC = 3.3V. Level Specifications will vary 1:1 with VCC.

8. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing

point of the differential output signals.

9. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of theoutput

signal.

10. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device.

11. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The

VPP(min) is AC limited for the E111 as a differential input as low as 50 mV will still produce full ECL levels at the output.

12. V

is defined as the range within which the V

CMR

level may vary, with the device still meeting the propagation delay

IH

specification. The VIL level must be such that the peak-to-peak voltage is less than 1.0V and greater than or equal to
VPP(min).

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B

G1

0.007 (0.180) T L – M N

M

S

S

0.007 (0.180) T L – M N

M

S

S

0.010 (0.250) T L – M N

S

S

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Package Information

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Low Voltage 1:9 Differential ECL/PECL
Clock Driver with Enable Input

SK10LVE111E
SK100LVE111E

–L–

28 1

Z

C

+

G1

0.010 (0.250) T L – M N

–N–

Y BRK

D

–M–

VIEW D-D

W

V

0.007 (0.180) T L – M N

A

0.007 (0.180) T L – M N

R

E

+

G

S

S

S

J

–T–

VIEW S

D

M

M

0.004 (0.100)

SEATING PLANE

S

0.007 (0.180) T L – M N

S

S

S

S

K

H

K1

0.007 (0.180) T L – M N

F

M

VIEW S

M

S

S

S

NOTES:

1. Datums -L-, -M-, and -N- determined where top of lead

shoulder exits plastic body at mold parting line.

2. DIM G1, true position to be measured at Datum -T-,

Seating Plane.

3. DIM R and U do not include mold flash. Allowable mold flash

is 0.010 (0.250) per side.

4. Dimensioning and tolerancing per ANSI Y14.5M, 1982.

5. Controlling Dimension: Inch.

6. The package top may be smaller than the package bottom by

up to 0.012 (0.300). Dimensions R and U are determined at
the outermost extremes of the plastic body exclusive of mold
flash, tie bar burrs, gate burrs and interlead flash, but including
any mismatch betweeen the top and bottom of the plastic body.

7. Dimension H does not include Dambar protrusion or intrusion.

The Dambar protrusion(s) shall not cause the H dimension
to be greater than 0.037 (0.940). The Dambar intrusion(s)
shall not cause the H dimension to be smaller than 0.025
(0.635).

INCHES

MID NIM XAM NIM XAM

A584.0594.023.2175.21
B584.0594.023.2175.21
C561.0081.002.475.4
E090.0011.092.297.2
F310.0910.033.084.0
G050.0CSB72.1CSB
H620.0230.066.018.0

J020.0--15.0-­K520.0--46.0-­R054.0654.034.1185.11
U054.0654.034.1185.11
V240.0840.070.112.1

W240.0840.070.112.1

X240.0650.070.124.1
Y--020.0--05.0
Z2

o

1G014.0034.024.0129.01
1K040.0--20.1--

MILLIMETERS

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