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Low-Voltage 1:10 Differential
ECL/PECL/HSTL Clock Driver
SK10EP111
Preliminary Information
This document contains information on a new product. The
parametric information, although not fully characterized, is the result
of testing initial devices.
Features
• 100 ps Part-to-Part Skew
• 35 ps Output-to-Output Skew
• Differential Design
• VBB Output
• Low Voltage VEE Range of –2.375 to –3.8V for ECL
• Low Voltage VCC Range of +2.375 to +3.8V for PECL and HSTL
• 75 KΩ Input Pulldown Resistors
• ECL/PECL Outputs
Description
The SK10EP111 is a low skew 1-to-10 diffferential driver, designed
with clock distribution in mind. It accepts two clock sources into an
input multiplexer. The ECL/PECL input signals can be either
differential or single-ended if the VBB output is used. HSTL inputs
can be used when the EP111 is operating under PECL conditions.
The selected signal is fanned out to 10 identical differential outputs.
October 4, 1999
Low-Voltage 1:10
Differential ECL/PECL/HSTL
Clock Driver
32 Lead
LQFP Package
Logic Symbol
CLK0
CLK0*
CLK1
CLK1*
CLK_SEL
0
1
10
VBB
Pinout
Q3
Q3*Q4Q4*Q5Q5*Q6Q6*
Q0:9
Q0*:9*
The SK10EP111 is specifically designed, modeled, and produced
with low skew as the key goal. Optimal design and layout serve to
minimize gate-to-gate skew within a device, and characterization is
used to determine process control limits that ensure consistent tpd
distributions from lot to lot. The net result is a dependable,
guaranteed low skew device.
To ensure that the tight skew specification is met, it is necessary
that both sides of the differential output are terminated into 50Ω,
even if only one side is being used. In most applications, all ten
differential pairs will be used and therefore terminated. In the case
where fewer than ten pairs are used, it is necessary to terminate at
least the output pairs on the same package side as the pair(s) being
used on that side in order to maintain minimum skew. Failure to do
this will result in small degradations of propagation delay (on the
order of 10–20 ps) of the output(s) being used which, while not
being catastrophic to most designs, will mean a loss of skew margin.
The SK10EP111, as with most other ECL devices, can be operated
from a positive VCC supply in PECL mode. This allows the EP111
to be used for high performance clock distribution in +3.3V or +2.5V
systems. Designers can take advantage of the EP111’s performance
to distribute low skew clocks across the backplane or the board. In
a PECL environment, series or Thevenin line terminations are
typically used as they require no additional power supplies.
VCC0
Q2*
Q1*
Q0*
VCC0
Pin Names
niP noitcnuF
*0KLC,0KLC
*1LKC,1KLC
*9:*0Q,9:0Q
LES_KLC
BBV
Function
LES_KLC tupnIevitcA
0
1
24 23 22 21 20 19 18 17
25
26
27
Q2
28
SK10EP111
29
Q1
30
31
Q0
32
1 2 3 4 5 6 7 8
CLK0
CLK_SEL
tuptuOBBV
CLK0*
VBB
CLK1
CLK1*
VCC
VEE
VCC0
16
Q7
15
Q7*
14
Q8
13
Q8*
12
Q9
11
Q9*
10
VCC0
9
riaPtupnILCEP/LCElaitnereffiD
riaPtupnILTSHlaitnereffiD
stuptuOLCEPlaitnereffiD
tupnItceleSkcolCevitcA
*0KLC,0KLC
*1KLC,1KLC
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ECL/PECL/HSTL Clock Driver
ECL DC Characteristics
-04oC 0oC 52oC 58oC
lobmyS citsiretcarahC niM pyT xaM niM pyT xaM niM pyT xaM niM pyT xaM tinU
Low-Voltage 1:10 Differential
SK10EP111
V
HO
V
LO
V
HI
V
LI
V
BB
V
EE
I
HI
I
EE
V
RMC
V
PP
egatloVHGIHtuptuO5311-098-0801-048-0201-018-019-027-Vm
egatloVWOLtuptuO0591-0561-0591-0361-0591-0361-0591-5951-Vm
egatloVHGIHtupnI0321-098-0711-048-0311-018-0601-027-Vm
egatloVWOLtupnI0591-0051-0591-0841-0591-0841-0591-5441-Vm
egatloVecnerefeRtuptuO34.1-03.1-83.1-72.1-53.1-52.1-13.1-91.1-V
egatloVylppuSrewoP573.2-8.3-573.2-8.3-573.2-8.3-573.2-8.3-V
tnerruCHGIHtupnI051051051051Aµ
tnerruCylppuSrewoP
V8.3-ot573.2-=EEV
egnaRedoMnommoC
gniwStupnImuminiM005005005005Vm
08801088010880108801Am
+EEV
7.1
-CCV
3.0
+EEV
7.1
-CCV
3.0
+EEV
7.1
-CCV
3.0
+EEV
7.1
-CCV
3.0
V
HSTL DC Characteristics
-04oC 0oC 52oC 58oC
lobmyS citsiretcarahC niM pyT xaM niM pyT xaM niM pyT xaM niM pyT xaM tinU
V
RMC
V
PP
egnaRedoMnommoC
gniwStupnImuminiM005005005005Vm
+EEV
9.0
-CCV
1.1
+EEV
9.0
-CCV
1.1
+EEV
9.0
-CCV
1.1
+EEV
9.0
-CCV
V
1.1
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ECL/PECL/HSTL Clock Driver
PECL DC Characteristics
-04oC 0oC 52oC 58oC
lobmyS citsiretcarahC niM pyT xaM niM pyT xaM niM pyT xaM niM pyT xaM tinU
Low-Voltage 1:10 Differential
SK10EP111
V
HO
V
LO
V
HI
V
LI
V
BB
V
EE
I
HI
I
EE
V
RMC
V
PP
tnerruCHGIHtupnI051051051051Aµ
)1etoN(egatloVHGIHtuptuO56120123022202420822094209320852Vm
)1etoN(egatloVWOLtuptuO05310561053107610531076105315071Vm
)1etoN(egatloVHGIHtupnI07620142031206420712014204220852Vm
)1etoN(egatloVWOLtupnI05310081053102810531028105315581Vm
)1etoN(egatloVecnerefeRtuptuO78.100.229.130.259.150.299.111.2V
egatloVylppuSrewoP573.28.3573.28.3573.28.3573.28.3V
tnerruCylppuSrewoP
V8.3+ot573.2+=CCV
egnaRedoMnommoC
gniwStupnImuminiM005005005005Vm
08801088010880108801Am
+EEV
7.1
-CCV
3.0
+EEV
7.1
-CCV
3.0
Note 1: These values are for VCC = 3.3V. Level Specifications will vary 1:1 withVCC.
+EEV
7.1
-CCV
3.0
+EEV
7.1
-CCV
V
3.0
AC Characteristics (V
lobmyS citsiretcarahC niM pyT xaM niM pyT xaM niM pyT xaM niM pyT xaM tinU
t
t
t
f
t
HLP
LHP
weks
xam
rt,f
porPLCEP/LCE
tuptuOotyaleD
porPLTSH
tuptuOotyaleD
wekSeciveD-nihtiW
wekStraP-ot-traP
ycneuqerFtupnIxaM0051005100510051zHM
emiTllaF/esiRtuptuO002006002006002006002006sp
= –2.375V to –3.8V; VCC = V
EE
-04oC 0oC 52oC 58oC
013
083
093
043
055
51
054
024
044
514
584
085
006
03
001
541
= GND)
CC0
053
504
083
585
514
574
044
573
064
034
054
015
026
51
03
001
014
046
016
031
544
064
084
046
51
001
015
084
575
086
094
064
094
545
025
076
03
531
516
046
076
51
03
001
sp
025
sp
027
sp
007
sp
sp
051
sp
SE
MID NIM XAM NIM XAM
A000.7CSB672.0CSB
1A005.3CSB831.0CSB
B000.7CSB672.0CSB
1B005.3CSB831.0CSB
C004.1006.1550.0360.0
D003.0054.0210.0810.0
E053.1054.1350.0750.0
F003.0004.0210.0610.0
G008.0CSB130.0CSB
H050.0051.0200.0600.0
J090.0002.0400.0800.0
K005.0007.0020.0820.0
M21
o
FER21
o
FER
N090.0061.0400.0600.0
P004.0CSB610.0CSB
Q1
o
5
o
1
o
5
o
R
051.0052.0600.0010.0
S000.9CSB453.0CSB
1S005.4CSB771.0CSB
V000.9CSB453.0CSB
1V005.4CSB771.0CSB
W002.0FER800.0FER
X000.1FER930.0FER
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Package Information
C
H
Low-Voltage 1:10 Differential
ECL/PECL/HSTL Clock Driver
SK10EP111
–T, U, Z –
–AB–
–AC–
32 25
1
8
9
8x M
˚
A1,
B1
A, B
G
0.10 (0.004) AC
4 X
24
17
16
SEE DETAIL "Y"
R
0.20 (0.008) AB ZT–U
S, V
S1,V1
SEE DETAIL "AD"
NOTES:
1. Dimensioning and tolerancing per ANSI
Y14.5M, 1982.
2. Controlling Dimension: Millimeter
3. Datum Plane –AB– is located at bottom
of lead and is coincident with the lead
where the lead exits the plastic body at
the bottom of the parting line.
4. Datums –T–, –U–, and –Z– to be
determined at Datum Plane –AB–.
5. Dimensions S and V to be determined at
Seating Plane –AC–.
6. Dimensions A and B do not include mold
protrusion. Allowable protrusion is 0.250
(0.010) per side. Dimensions A and B
do not include mold mismatch and are
determined at Datum Plane –AB–.
7. Dimension D does not include Dambar
protrusion. Dambar protrusion shall not
cause the D dimension to exceed
0.520 (0.020).
8. Minimum solder plate thickness shall be
0.0075 (0.0003).
9. Exact shape of each corner may vary
from depiction.
MILLIMETERS
INCHES
E
C
H
P
DETAIL Y
DETAIL AD
W
X
Q
˚
0.250 (0.010)
GAUGE PLANE
Base Metal
K
N
–T–, –Ü–, –Z–
AE
AE
F
0.20 (0.008)
N
M
D
AC T–U Z
SECTION AE
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