Datasheet SK100EL15WD, SK100EL15WDT, SK100EL15WU, SK10EL15WD, SK10EL15WDT Datasheet (Semtech Corporation)

HIGH-PERFORMANCE PRODUCTS

1

www.semtech.com

Revision 1/February 12, 2001

SK10/100EL15W

1:4 Clock

Distribution

Description

Features

Functional Block Diagram

The SK10/100EL15W is a low skew 1:4 clock distribution
chips designed explicitly for low skew clock distribution
applications. This device is fully compatible with
MC10EL15 & MC100EL15. The device can be driven by
either a differential or single-ended ECL or, if positive power
supplies are used, PECL input signal. If a single-ended
input is to be used, the VBB output should be connected
to the CLK* input and bypassed to VCC via a 0.01 µF
capacitor. The EL15W provides a VBB output for either
single-ended use or as a DC bias for AC coupling to the
device. The VBB pin should be used only as a bias for
EL15W as its current sink/source capability is limited.
Whenever used, the VBB pin should be bypassed to VCC
via a 0.01 µF capacitor.

The EL15W features a multiplexed clock input to allow for
the distribution of a lower speed scan or test clock along
with the high speed system clock. When LOW (or left
open and pulled LOW by the input pull-down resistor) the
SEL pin will select the differential clock input.

The common enable (EN*) is synchronous so that the
outputs will only be enabled/disabled when they are already
in the LOW state. This avoids any chance of generating a
runt clock pulse when the device is enabled/disabled as
can happen with an asynchronous control. The internal
flip-flop is clocked on the falling edge of the input clock,
therefore, all associated specification limits are referenced
to the negative edge of the clock input.

• Extended Supply Voltage Range: (VEE = –5.5V to
–3.0V, VCC = 0V) or (VCC = + 3.0V to +5.5V,
VEE=0V)

• 50 ps Output-to-Output Skew

• Synchronous Enable/Disable

• Multiplexed Clock Input

• 75KΩ Internal Input Pull-Down Resistors

• Fully Compatible with MC10EL15 and

MC100EL15

• Specified Over Industrial Temperature Range:

–40

o

C to +85oC

• ESD Protection of >4000V

• Available in 16-Pin SOIC Package

PIN Description

emaNniPnoitcnuF

KLCstupnIkcolClaitnereffiD

KLCStupnIkcolCsuonorhcnyS

*NEelbanEsuonorhcnyS

LEStupnItceleSkcolC

V

BB

egatloVtuptuOecnerefeR

*3Q-*0Q,3Q0QstuptuOkcolClaitnereffiD

KLCKLCSLES*NEQ

LXLLL

HX L LH

XLHLL

XHHLH

XXXH *L

Truth Table

*On next negative transition of CLK or SCLK.

Q0

Q0*

Q2

Q2*

Q3

Q3*

Q1

Q1*

V

CC

EN*

CLK*

V

BB

SEL

V

EE

SCL

K

CLK

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

Q D

1

0

2

www.semtech.com

HIGH-PERFORMANCE PRODUCTS

SK10/100EL15W

Revision 1/February 12, 2001

Package Information

J

F

R

x 45

˚

M

D

C

K

–T–

168 PL

SEATING
PLANE

0.25 (0.010) M T B S A S

G

–A–

P

–B

8 PL

0.25 (0.010) M B S

16

9

18

NOTES:

1. Dimensioning and tolerancing per ANSI Y14.5M,

1982.

2. Controlling dimension: millimeter.

3. Dimensions A and B do not include mold protrusion.

4. Maximum mold protrusion 0.150 (0.006) per side.

5. Dimension D does not include Dambar protrusion.
Allowable Dambar protrusion shall be 0.13 (0.005)
total in excess of d dimension at maximum material
condition.

16 Pin SOIC Package

SRETEMILLIMSEHCNI

MIDNIMXAMNIMXAM

A08/900.01683.0393.0

B08.300.4051.0751.0

C53.157.1450.0860.0

D53.094.0410.0910.0

F04.052.1610.0940.0

G72.1CSB050.0CSB

J91.052.0800.0900.0

K01.052.0400.0900.0

M0

o

7

o

0

o

7

o

P08.502.6922.0442.0

R52.005.0010.0910.0

3

www.semtech.com

HIGH-PERFORMANCE PRODUCTS

SK10/100EL15W

Revision 1/February 12, 2001

DC Characteristics

SK10/100EL15W DC Electrical Characteristics (Notes 1, 2)

lobmyScitsiretcarahCniMpyTxaMniMpyTxaMniMpyTxaMniMpyTxaMtinU

I

NI

)ffiD(tnerruCtupnI
)ES(

051-051

051

051-051

051

051-051

051

051-051

051

Aµ
Aµ

I

EE

tnerruCylppuSrewoP

LE01

LE001

02
12

53
53

12
12

63
63

12
22

63
83

22
42

83
14

Am
Am

V

BB

egatloVecnerefeRtuptuO

5

LE01

LE001

34.1

83.1

03.1

62.1

83.1

83.1

72.1

62.1

53.1

83.1

52.1

62.1

13.1

83.1

91.1

62.1

Vm
Vm

V

CC

V

EE

egatloVylppuSrewoP0.35.50.35.50.35.50.35.5V

(V

CC – VEE

= +3.0V to +5.5V ; V

OUT

loaded 50Ω to V

CC

– 2.0V)

TA = –40oC TA = 0oC TA = +25oC TA = +85oC

SK10/100EL15W AC Electrical Characteristics

lobmyScitsiretcarahCniMxaMniMxaMniMxaMniMxaMtinU

t

HLP

t

LHP

yaleDnoitagaporP
)ffiD(QotKLC

)ES(QotKLC

QotKLCS

065
074
564

056
017
586

085
005
594

576
596
007

195
015
015

596
086
507

026
545
665

047
527
547

sp
sp
sp

t

weks

wekStraP-ot-traP

WekSeciveD-nihtiW

002

05

002

05

002

05

002

05

sp
sp

t

S

*NEemiTputeS051051051051sp

t

H

*NEemiTdloH004004004004sp

V

PP

KLCgniwStupnImuminiM

3

0520001052000105200010520001Vm

V

RMC

KLCegnaRedoMnommoC

4
Vm005<PPV
Vm005>PPV

3.1+EEV

5.1+EEV

4.0CCV

4.0CCV

3.1+EEV

5.1+EEV

4.0CCV

4.0CCV

3.1+EEV

5.1+EEV

4.0CCV

4.0CCV

3.1+EEV

5.1+EEV

4.0CCV

4.0CCV

V
V

t

rt,f

semiTllaF/esiRtuptuO

)%08ot%02(*nQ,nQ

591043502053012063522083sp

TA = –40oC TA = 0oC TA = +25oC TA = +85oC

(V

CC – VEE

= +3.0V to +5.5V ; V

OUT

loaded 50Ω to V

CC

– 2.0V)

AC Characteristics

4

www.semtech.com

HIGH-PERFORMANCE PRODUCTS

SK10/100EL15W

Revision 1/February 12, 2001

Ordering Information

edoCgniredrODIegakcaPegnaRerutarepmeT

DW51LE01KSCIOS-61lairtsudnI

TDW51LE01KSCIOS-61lairtsudnI

DW51LE001KSCIOS-61lairtsudnI

TDW51LE001KSCIOS-61lairtsudnI

UW51LE01KSeiD

UW51LE001KSeiD

Notes:

1. 10EL circuits are designed to meet the DC specifications shown in the table after thermal equilibrium
has been established. The circuit is in a test socket or mounted on a printed circuit board and
transverse airflow greater than 500 lfpm is maintained. Outputs are terminated through a 50Ω resistor
to VCC –2.0V.

2. 100K circuits are designed to meet the DC specification shown in the table where transverse airflow
greater than 500 lfpm is maintained.

3. Minimum input swing for which AC parameters guaranteed.

4. CMR range is referenced to the most positive side of the differential input signal. Normal operation is
obtained if the high level falls within the specified range and the peak-to-peak voltage lies between
VPP

(min)

and 1V. The lower end of the CMR range varies 1:1 with VEE and is equal to VEE + 1.3V for

VPP < 500 mV and VEE + 1.5V for VPP > 500 mV.

5. Voltages referenced to VCC = 0V (ECL mode).

6. For standard ECL DC specifications, refer to the ECL Logic Family Standard DC Specifications Data

Sheet.

7. For part ordering descriptions, see HPP Part Ordering Information Data Sheet.

Division Headquarters
10021 Willow Creek Road
San Diego, CA 92131
Phone: [phone]
FAX: [phone]

Marketing Group

1111 Comstock Street

Santa Clara, CA 95054

Phone: [phone]

FAX: [phone]

Semtech Corporation

High-Performance Products Division

Contact Information

AC Characteristics (continued)