Datasheet SK100EL14WD, SK100EL14WDT, SK100EL14WU, SK10EL14WD, SK10EL14WDT Datasheet (Semtech Corporation)

HIGH-PERFORMANCE PRODUCTS

1

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Revision 1/February 12, 2001

SK10/100EL14W

1:5 Clock Distribution Chip

Description

Features

Pin Descriptions

Functional Block Diagram

The SK10/100EL14W is a 1:5 Clock Distribution Chip
designed specifically for low skew clock distribution
applications. This device is fully compatible with
MC100EL14 and MC100LVEL14.

The device can be driven by either differential or single­ended ECL/PECL input signals. The SK10/100EL14W
provides a V

BB

output for either single-ended use or DC
bias for AC coupling to the device. VBB is an output pin
and should be used as a bias for the EL14W as its current
sink/source capability is limited. Whenever used, V

BB

should be bypassed to VCC via a 0.01 µF capacitor.

The EL14W features a multiplexed clock input to allow for
the distribution of a lower speed scan or test clock along
with the high speed system clock. When LOW (or left
open and pulled LOW by the input pulldown resistor) the
SEL pin will select the differential clock input. The Common
Enable pin (EN*) is synchronous so that the outputs will
only be enabled/disabled when they are already in the
LOW state. This avoids the chance of generating a runt
clock pulse when the device is enabled/disabled as can
happen with an asynchronous control. The internal flip­flops are clocked on the falling edge of the input clock;
therefore, all associated specification limits are referenced
to the negative edge of the clock input.

• Extended Supply Voltage Range: (VEE = –5.5V to
–3.0V, VCC = 0V) or (VCC = + 3.0V to +5.5V,
VEE=0V)

• High Bandwidth Output Transition

• Max. 50 ps Output-to-Output Skew (Typ. 30 ps)

•V

BB

Output

• Synchronous Enable/Disable

• Multiplexed Clock Input

• 75 KΩ Internal Input Pulldown Resistors

• New Differential Input Common Mode Range

• Fully Compatible with MC100EL14 and
MC100LVEL14

• ESD Protection of >4000 V

• Industrial Temperature Range: –40oC to +85oC

• Available in 20-Pin SOIC (150 mils) Package

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Function Table

Q0

Q1*

Q0*

Q2

Q2*

Q3

Q4

Q4*

Q1

Q3*

V

CC

CLK*

EN*

CLK

V

BB

SEL

V

EE

V

CC

NC

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

DQ

1
0

SCLK

* On next negative transition of CLK or SCLK

2

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HIGH-PERFORMANCE PRODUCTS

SK10/100EL14W

Revision 1/February 12, 2001

Package Information

PIN Descriptions

20 Pin SOIC Package

J

F

R

x 45

˚

M

D

–A

P

–B

10 X

20 X

0.010 (0.25) M B M

20 11

0.010 (0.25) M T A S B S

G

C

K

–T

18 X

SEATING
PLANE

NOTES:

1. Dimensions and tolerances per ANSI Y14.5M,

1982.

2. Controlling dimension: millimeter.

3. Dimensions A and B do not include mold protrusion.

4. Maximum mold protrusion 0.150 (0.006) per side.

5. Dimension D does not include Dambar protrusion.
Allowable Dambar protrusion shall be 0.13 (0.005)
total in excess of d dimension at maximum material
condition.

Millimeters

SRETEMILLIM

MID NIM XAM

A53.157.1

1A01.052.0

B33.015.0

C91.052.0

D08.400.5

E08.300.4

e72.1CSB

H08.502.6

h52.005.0

L04.072.1

θ

0

o

8

o

3

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HIGH-PERFORMANCE PRODUCTS

SK10/100EL14W

Revision 1/February 12, 2001

SK10/100EL14W DC Electrical Characteristics (Notes 1, 2)

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LE01

LE001

22
22

82
82

83
83

32
32

03
03

93
04

42
42

03
13

04
14

52
72

23
43

24
64

Am
Am

V

BB

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3

LE01

LE001

34.1-

83.1-

03.1-

62.1-

83.1-

83.1-

72.1-

62.1-

53.1-

83.1-

52.1-

62.1-

13.1-

83.1-

91.1-

62.1-

V
V

I

NI

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051-051

051

051-051

051

051-051

051

051-051

051

Aµ

µA

TA = –40oC TA = 0oC TA = +25oC TA = +85oC

(V

CC – VEE

= +3.0V to +5.5V ; V

OUT

loaded 50Ω to V

CC

– 2.0V)

DC Characteristics

AC Characteristics

SK10/100EL14W AC Electrical Characteristics

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025

557
017
567

056
075
055

587
047
087

066
085
075

508
067
097

596
506
026

068
518
038

sP
sP
sP

t

weks

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4

002

05

002

05

002

05

002

05

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sp

t

S

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H

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V

PP

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RMC

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6

Vm005<PPV

Vm005>PPV

3.1+EEV

5.1+EEV

4.0-CCV

4.0-CCV

3.1+EEV

5.1+EEV

4.0-CCV

4.0-CCV

3.1+EEV

5.1+EEV

4.0-CCV

4.0-CCV

3.1+EEV

5.1+EEV

4.0-CCV

4.0-CCV

V
V

t

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TA = –40oC TA = 0oC TA = +25oC TA = +85oC

(V

CC – VEE

= +3.0V to +5.5V ; V

OUT

loaded 50Ω to V

CC

– 2.0V)

4

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HIGH-PERFORMANCE PRODUCTS

SK10/100EL14W

Revision 1/February 12, 2001

Notes:

1. 10EL circuits are designed to meet the DC specifications shown in the table after thermal equilibrium
has been established. The circuit is in a test socket or mounted on a printed circuit board and
transverse airflow greater than 500 lfpm is maintained. Outputs are terminated through a 50Ω resistor
to VCC –2.0V.

2. 100K circuits are designed to meet the DC specification shown in the table where transverse airflow
greater than 500 lfpm is maintained.

3. Voltages are referenced to VCC = 0V.

4. Skews are specified for identical LOW-to-HIGH or HIGH-to-LOW transitions.

5. Minimum input swing for which AC parameters guaranteed.

6. CMR range is referenced to the most positive side of the differential input signal. Normal operation is
obtained if the high level falls within the specified range and the peak-to-peak voltage lies between
VPP

(min)

and 1V. The lower end of the CMR range varies 1:1 with VEE and is equal to VEE + 1.3V for

VPP < 500 mV, and VEE + 1.5 for VPP > 500 mV.

7. For standard ECL DC specifications, refer to the ECL Logic Family Standard DC Specifications Data

Sheet.

8. For part ordering descriptions, see HPP Part Ordering Information Data Sheet.

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FAX: [phone]

Marketing Group

1111 Comstock Street

Santa Clara, CA 95054

Phone: [phone]

FAX: [phone]

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High-Performance Products Division

Contact Information

AC Characteristics (continued)

Ordering Information

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DW41LE01KSCIOS-02lairtsudnI

TDW41LE01KSCIOS-02lairtsudnI

DW41LE001KSCIOS-02lairtsudnI

TDW41LE001KSCIOS-02lairtsudnI

UW41LE01KSeiD

UW41LE001KSeiD