Datasheet SK100LVE111, SK10LVE111 Datasheet (Semtech Corporation)

SE

M

Today's Results

TE

...

Tomorrow's Vision

C

H

Low Voltage 1:9 Differential
ECL/ PECL Clock Driver

SK10LVE111
SK100LVE111

Preliminary Information

This document contains information on a new product. The parametric
information, although not fully characterized, is the result of testing
initial devices.

Features

• 200 ps Part-to-Part Skew

• 50 ps Output-to-Output Skew

• Differential Design

•VBB Output

• Voltage and Temperature Compensated Outputs

• Low Voltage VEE Range of –3,0 to –3.8V

• 75KΩ Internal Pulldown Resistors

• Fully Compatible with Motorola MC100LVE111

• Specified Over Industrial Temperature Range:
–40˚C to 85˚C

• ESD Protection of >2000V

• Available in 28-pin PLCC Package

Description

October 6, 1999

Low Voltage 1:9 Differential

ECL / PECL Clock Driver

28 Pin

PLCC Package

The SK100LVE is a low skew 1-to-9 differential driver designed
with clock distribution in mind. The SK100LVE111’s function
and performance are similar to the SK100E111, with the added
feature of low voltage operation. It accepts one signal input
which can be either differential or single-ended if the VBB output
is used. The signal is fanned out to 9 identical differential
outputs.

The device is specifically designed, modeled, and produced
with low skew as the key goal. Optimal design and layout serve
to minimize gate-to-gate skew within a device, and
characterization is used to determine process control limits that
ensure consistent tpd distributions from lot to lot. The net result
is a dependable, guaranteed low skew device.

To ensure that the tight skew specification is met, it is necessary
that both sides of the differential output are terminated into 50Ω,
even if only one side is being used. In most applications, all
nine differential pairs will be used and therefore terminated. In
the case where fewer than nine pairs are used, it is necessary
to terminate at least the output pairs on the same package
side as the pair(s) being used on that side in order to maintain
minimum skew. Failure to do this will result in small
degradations of propagation delay (on the order of 10–20ps)
of the output(s) being used which, while not being catastrophic
to most designs, will mean a loss of skew margin.

The SK100LVE111, as with most other ECL
devices, can be operated from a positive VCC
supply in PECL mode. This allows the LVE111 to
be used for high performance clock distribution in
+3.3V systems. Designers can take advantage
of the LVE111’s performance to distribute low skew
clocks across the backplane or the board. In a
PECL environment, series or Thevenin line
terminations are typically used as they require no
additional power supplies. For systems
incorporating GTL, parallel termination offers the
lowest power by taking advantage of the 1.2V
supply as a terminating voltage.

SE

M

Today's Results

TE

...

Tomorrow's Vision

C

H

Low Voltage 1:9 Differential
ECL/ PECL Clock Driver

SK10LVE111
SK100LVE111

Q0
Q0*

Q1
Q1*

Q2
Q2*

Q3
Q3*

Q4

IN
IN*

V

BB

Q4*

Q5
Q5*

Q6
Q6*

Q7
Q7*

Q8
Q8*

Absolute Maximum Ratings (Note 3)

niP noitcnuF

*NI,NI

*0Q,0Q − *8Q,8Q

BBV

Q0

Q0*Q1VCC0

25 24 23 22 21 20 19

VEE

26

N/C

27

IN

VCC

VBB

28

1

IN*

2

3

N/C

4

28 Lead PLCC

567891011

Q8

Q7

Q8*

(Top View)

VCC0

tuptuOBBV

Q1*Q2Q2*

Q7*Q6Q6*

riaPtupnIlaitnereffiD

stuptuOlaitnereffiD

18

Q3

17

Q3*

16

Q4

15

VCC0

14

Q4*

13

Q5

12

Q5*

lobmyS retemaraP gnitaR tinU

V

EE

V

I

:tnerruCtuptuO

I

TUO

suounitnoC

egruS

T

A

V

EE

T

)4eton(egnaRgnitarepO8.3-ot0.3-V

erots

)V0=CCV(ylppuSrewoP5.4-0otV

)V0=CCV(egatloVtupnIot00.4-V

05

001

egnaRerutarepmeTgnitarepO-58+ot04

egnaRerutarepmeTegarotS-051+ot56

Am
Am

o

C

o

C

SE

M

Today's Results

TE

...

Tomorrow's Vision

C

H

Low Voltage 1:9 Differential
ECL/ PECL Clock Driver

SK10LVE111
SK100LVE111

SK10LVE111 ECL DC Electrical Characteristics

(VEE = VEE (min) to VEE (max); VCC = GND) (Notes 1 and 4)

TA = –40˚C TA = 0˚C TA = +25˚C TA = +85˚C

lobmyS citsiretcarahC niM pyT xaM niM pyT xaM niM pyT xaM niM pyT xaM tinU

V

HO

V

LO

V

HI

V

LI

V

BB

I

HI

I

LI

I

EE

egatloVHGIHtuptuO-5311098-0801-048-0201-018-019-027-Vm

egatloVWOLtuptuO0591-0561-0591-0361-0591-0361-0591-5951-Vm

egatloVHGIHtupnI0321-098-0711-048-0311-018-0601-027-Vm

egatloVWOLtupnI0591-0051-0591-0841-0591-0841-0591-5441-Vm

egatloVecnerefeRtuptuO-34.103.1-83.1-72.1-53.1-52.1-13.1-91.1-V

tnerruCHGIHtupnI051051051051Aµ

tnerruCWOLtupnI5.05.05.03.0Aµ

tnerruCylppuSrewoP5356535653565356Am

SK10LVE111 PECL DC Electrical Characteristics

(VCC = VCC (min) to VCC (max); VEE = GND) (Notes 1 and 4)

TA = –40˚C TA = 0˚C TA = +25˚C

lobmyS citsiretcarahC niM pyT xaM niM pyT xaM niM pyT xaM niM pyT xaM tinU

V

HO

7

egatloVHGIHtuptuO

56120123022202420822094209320852Vm

TA = +85˚C

V

LO

V

HI

V

LI

V

BB

I

HI

I

LI

I

EE

7

egatloVWOLtuptuO

7

egatloVHGIHtupnI

7

egatloVWOLtupnI

egatloVecnerefeRtuptuO

tnerruCHGIHtupnI051051051051Vµ

tnerruCWOLtupnI5.05.05.03.0Aµ

tnerruCylppuSrewoP66666666Am

05310561053107610531076105315071Vm

07620142031206420712014204220852Vm

05310081053102810531028105315581Vm

7

78.100.229.130.259.150.299.111.2V

SE

M

Today's Results

TE

...

Tomorrow's Vision

C

H

Low Voltage 1:9 Differential
ECL/ PECL Clock Driver

SK100LVE111 ECL DC Electrical Characteristics

(VEE = VEE (min) to VEE (max); VCC = GND) (Notes 2 and 4)

SK10LVE111
SK100LVE111

TA = –40˚C TA = 0˚C TA = +25˚C

lobmyS citsiretcarahC niM pyT xaM niM pyT xaM niM pyT xaM niM pyT xaM tinU

V

HO

V

LO

V

HI

V

LI

V

BB

V

EE

I

HI

I

EE

egatloVHGIHtuptuO-41.1500.1--088.0-80.1-559.0-088.080.1--559.0-088.080.1--559.0-088.0V

egatloVWOLtuptuO-38.1-596.1-555.1-018.1-507.1-026.1-018.1-507.1-026.1-018.1-507.1-026.1V

egatloVHGIHtupnI-561.1-088.0-561.1-088.0-561.1-088.0-561.1-088.0V

egatloVWOLtupnI-018.1-574.1-018.1-574.1-018.1-574.1-018.1-574.1V

egatloVecnerefeRtuptuO-83.1-62.1-83.1-62.1-83.1-62.1-83.1-62.1V

egatloVylppuSrewoP-0.3-8.3-0.3-8.3-0.3-8.3-0.3-8.3V

tnerruCHGIHtupnI051051051051Aµ

tnerruCylppuSrewoP5566556655665687Am

TA = +85˚C

SK100LVE111 PECL DC Electrical Characteristics

(VCC = VCC (min) to VCC (max); VEE = GND) (Notes 2 and 4)

TA = –40˚C TA = 0˚C TA = +25˚C

lobmyS citsiretcarahC niM pyT xaM niM pyT xaM niM pyT xaM niM pyT xaM tinU

V

HO

V

LO

V

HI

V

LI

V

BB

V

CC

I

HI

I

EE

7

egatloVHGIHtuptuO

7

egatloVWOLtuptuO

7

egatloVHGIHtupnI

7

egatloVWOLtupnI

egatloVecnerefeRtuptuO

egatloVylppuSrewoP0.38.30.38.30.38.30.38.3V

tnerruCHGIHtupnI051051051051Aµ

tnerruCylppuSrewoP5566556655665687Am

61.2592.2024.222.2543.2024.222.2543.2024.222.2543.2024.2V

74.116.157.1094.1595.1086.1094.1595.1086.1094.1595.1086.1V

531.2024.2531.2024.2531.2024.2531.2024.2V

094.1528.1094.1528.1094.1528.1094.1528.1V

7

29.140.229.140.229.140.229.140.2V

TA = +85˚C

SE

M

Today's Results

TE

...

Tomorrow's Vision

C

H

Low Voltage 1:9 Differential
ECL/ PECL Clock Driver

SK10LVE111
SK100LVE111

AC Characteristics

(VEE = VEE (min) to VEE (max); VCC = V

-04oC 0oC 52oC 58oC

lobmyS citsiretcarahC niM pyT xaM niM pyT xaM niM pyT xaM niM pyT xaM tinU dnoC

= GND) (Note 4)

CCO

t
t

t

V

V

t

rt,f

HLP

LHP

weks

PP

RMC

tuptuO

otyaleDnoitagaporP

)laitnereffiD(NI

)dednE-elgniS(NI

wekSeciveD-nihtiW

gniwStupnImuminiM005005005005Vm.11

emiTllaF/esiR
%08ot%02

004

053

)ffiD(wekStraP-ot-traP

egnaRedoMnommoC-5.1-4.0-5.1-4.0-5.1-4.0-5.1-4.0V .21

002006002006002006002006sp%02-%08

056

534

007

583

05

052

526

044

576

093

05

052

036

544

086

593

05

052

536
586

05

052

sp

sp

.8
.9

.01

1. 10LVE circuits are designed to meet the DC specifications shown in the table after thermal equilibrium has been established.

The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
Outputs are termionated through a 50Ω resistor to –2.0V.

2. The same DC parameter values apply across the full VEE range of –3.0 to –3.8V. Outputs are terminated through a 50Ω

resistor to –2.0V. 100LVE circuits are designed to meet the DC specifications shown in the table where transverse airflow
greater than 500 lfpm is maintained.

3. Absolute maximum rating, beyond which device life may be impaired unless otherwise specificed on an individual data sheet.

4. Parametric values specified at:

10LVE Series: –3.0 to –3.8V
100 LVE Series: –3.0 to –3.8V; PECL Power Supply: +3.0V to +3.8V.

5. Guaranteed HIGH signal for all inputs.

6. Guaranteed LOW signal for all inputs.

7. These values are for VCC = 3.3V. Level Specifications will vary 1:1 with VCC.

8. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing

point of the differential output signals.

9. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of theoutput

signal.

10. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device.

11. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The

VPP(min) is AC limited for the E111 as a differential input as low as 50 mV will still produce full ECL levels at the output.

12. V

is defined as the range within which the V

CMR

level may vary, with the device still meeting the propagation delay

IH

specification. The VIL level must be such that the peak-to-peak voltage is less than 1.0V and greater than or equal to
VPP(min).

SE

+

+

Z

X

U

B

G1

0.007 (0.180) T L – M N

M

S

S

0.007 (0.180) T L – M N

M

S

S

0.010 (0.250) T L – M N

S

S

S

M

Today's Results

TE

...

Tomorrow's Vision

Package Information

C

H

Low Voltage 1:9 Differential
ECL/ PECL Clock Driver

SK10LVE111
SK100LVE111

–L–

28 1

Z

C

+

G1

0.010 (0.250) T L – M N

–N–

Y BRK

D

–M–

VIEW D-D

W

V

0.007 (0.180) T L – M N

A

0.007 (0.180) T L – M N

R

E

+

G

S

S

S

J

–T–

VIEW S

D

M

M

0.004 (0.100)

SEATING PLANE

S

0.007 (0.180) T L – M N

S

S

S

S

K

H

K1

0.007 (0.180) T L – M N

F

M

VIEW S

M

S

S

S

NOTES:

1. Datums -L-, -M-, and -N- determined where top of lead

shoulder exits plastic body at mold parting line.

2. DIM G1, true position to be measured at Datum -T-,

Seating Plane.

3. DIM R and U do not include mold flash. Allowable mold flash

is 0.010 (0.250) per side.

4. Dimensioning and tolerancing per ANSI Y14.5M, 1982.

5. Controlling Dimension: Inch.

6. The package top may be smaller than the package bottom by

up to 0.012 (0.300). Dimensions R and U are determined at
the outermost extremes of the plastic body exclusive of mold
flash, tie bar burrs, gate burrs and interlead flash, but including
any mismatch betweeen the top and bottom of the plastic body.

7. Dimension H does not include Dambar protrusion or intrusion.

The Dambar protrusion(s) shall not cause the H dimension
to be greater than 0.037 (0.940). The Dambar intrusion(s)
shall not cause the H dimension to be smaller than 0.025
(0.635).

INCHES

MID NIM XAM NIM XAM

A584.0594.023.2175.21
B584.0594.023.2175.21
C561.0081.002.475.4
E090.0011.092.297.2
F310.0910.033.084.0
G050.0CSB72.1CSB
H620.0230.066.018.0

J020.0--15.0-­K520.0--46.0-­R054.0654.034.1185.11
U054.0654.034.1185.11
V240.0840.070.112.1

W240.0840.070.112.1

X240.0650.070.124.1
Y--020.0--05.0
Z2

o

1G014.0034.024.0129.01
1K040.0--20.1--

MILLIMETERS

o

01

2

o

o

01