Datasheet SK100E445PJ, SK100E445PJT, SK10E445PJ, SK10E445PJT Datasheet (Semtech Corporation)

HIGH-PERFORMANCE PRODUCTS

1

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Revision 1/February 21, 2001

SK10/100E445

4-Bit Serial/Parallel Converter

Description

Features

Functional Block Diagram

• On-Chip Clock ÷ 4 and ÷8

• 2.0 Gb/s Data Rate Capability

• Differential Clock and Serial Inputs

•V

BB

Output for Single-Ended Input Applications

• Asynchronous Data Synchronization

• Mode Select to Expand to 8-Bits

• Internal 75 kΩ Input Pulldown Resistors

• ESD Protection of >4000V

• Extended 100E VEE Range of –4.2V to –5.46V

• Fully Compatible with MC10/100E445

• Available in 28-Pin PLCC Package

DQD

Q

Q

Q

Q3

Q2

Q1

Q0

SOUT

SOUT*

Q

Q

Q

Q

*

Q

Out

Q

CL/4*

CL/4

CL/8*

CL/8

0

¸

4

Out

¸

2

Out

Lat

ch

In

RESET

SYNC

CLK*

CLK

MODE

SEL

SINA*

SINA

SINB*

SINB

The SK10/100E445 is an integrated 4-bit serial-to­parallel data converter. The device is designed to operate
for NRZ data rates of up to 2.0 Gb/s. The chip generates
a divide by 4 and a divide by 8 clock for both 4-bit
conversion and a two chip 8-bit conversion function. The
conversion sequence was chosen to convert the first
serial bit to Q0, the second to Q1, etc.

Two selectable serial inputs provide a loopback capability
for testing purposes when the device is used in
conjunction with the R446 parallel to serial converter.

The start bit for conversion can be moved using the SYNC
input. A single pulse applied asynchronously for at least
two input clock cycles shifts the start bit for conversion
from Qn to Qn–1. For each additional shift required, an
additional pulse must be applied to the SYNC input.
Asserting the SYNC input will force the internal clock
dividers to “swallow” a clock pulse, effectively shifting a
bit from the Qn to the Qn–1 output (see Timing Diagram
B).

The MODE input is used to select the conversion mode
of the device. With the MODE input LOW, or open, the
device will function as a 4-bit converter. When the mode
input is driven HIGH, the data on the output will change
on every eighth clock cycle, thus allowing for an 8-bit
conversion scheme using two E445’s. When cascaded
in an 8-bit conversion scheme, the devices will not
operate at the 2.0 Gb/s data rate of a single device.
Refer to the applications section of this data sheet for
more information on cascading the E445.

For lower data rate applications, a VBB reference voltage
is supplied for single-ended inputs. When operating at
clock rates above 500 MHz, differential input signals
are recommended. For single-ended inputs, the VBB pin
is tied to the inverting differential input and bypassed
via a 0.01 µF capacitor. The VBB provides the switching
reference for the input differential amplifier. The V

BB

can also be used to AC couple an input signal.

Upon power-up, the internal flip-flops will attain a random
state. To synchronize multiple E445’s in a system, the
master reset must be asserted.

2

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HIGH-PERFORMANCE PRODUCTS

SK10/100E445

Revision 1/February 21, 2001

PIN Description

niPnoitcnuF

*ANIS,AniSAtupnIataDlaireSlaitnereffiD

*BNIS,BNISBtupnIataDlaireSlaitnereffiD

LESniProtceleStupnIlaireS

3Q-0QstuptuOataDlellaraP

*KLC,KLCstupnIkcolClaitnereffiD

*4/LC,4/LClaitnereffiD4tuptuOkcolC

*8/LC,8/LClaitnereffiD8tuptuOkcolC

EDOMtiB8/tiB-4edoMnoisrevnoC

HCNYStupnIgnizinorhcnySnoisrevnoC

edoMnoisrevnoCLEStupnIlaireS

LtiB-4HA

HtiB-8LB

Pin Names

Function Table

SOUT

SOUT*

V

CC

Q0

Q1

V

CC0

Q2

SINB

SINB*

SEL

V

EE

CLK

CLK*

V

BB

CL/8*

CL/8

V

CC0

CL/4

CL/4*

V

CC0

Q3

SINA

SINA*

SYNC

RESET

MODENCV

CCO

1

2

3

4

25 24 23 22 21 20 19

567891011

26

27

28

18

17

16

15

14

13

12

28 Lead PLCC

(Top View)

Pinout

3

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HIGH-PERFORMANCE PRODUCTS

SK10/100E445

Revision 1/February 21, 2001

Application Information

The SK10/100E445 is an integrated 4-bit serial-to­parallel data converter. The chip is designed to work
with the E446 device to provide both transmission and
receiving of a high speed serial data path. The E445
can convert up to a 2.0 GB/s NRZ data stream into 4-bit
parallel data. The device also provides a divide by four
clock output to be used to synchronize the parallel data
with the rest of the system.

The E445 features multiplexed dual serial inputs to
provide test loop capability when used in conjunction
with the E446. Figure 1 illustrates the loop test
architecture. The architecture allows for the electrical
testing of the link without requiring actual transmission
over the serial data path medium. The SINA serial input
of the E446 has an extra buffer delay and should be
used as the loopback serial input.

Figure 1. Loopback Test Architecture

The E445 features a differential serial output and a divide
by 8 clock output to facilitate the cascading of two devices
to build a 1:8 demultiplexer. Figure 2 illustrates the
architecture for a 1:8 demultiplexer using two E445’s;
the timing diagram for this configuration can be found in
Figure 6. Notice the serial outputs (SOUT of the lower
order converter feed the serial inputs of the higher order
device. This feedthrough of the serial inputs bounds
the upper end of the frequency of operation. The clock
to serial output propagation delay plus the setup time of
the serial input pins must fit into a single clock period
for the cascade architecture to function properly. Using
the worst case values for these two parameters from
the datasheet, TPD CLK to SOUT = 1150 ps and tS for
SIN = –100 ps, yields a minimum period of 1050 ps or a
clock frequency of 950 MHz.

The clock frequency is significantly lower than that of
a single converter. To increase this frequency, some
games can be played with the clock input of the higher
order E445. By delaying the clock feeding the second
E445 relative to the clock of the first E445, the
frequency of operation can be increased. The delay
between the two clocks can be increased until the
minimum delay of clock to serial out would potentially
cause a serial bit to be swallowed (Figure 3).

Figure 2. Cascaded 1:8 Converter Architecture

With a minimum delay of 800 ps on this output, the
clock for the lower order E445 cannot be delayed more
than 800 ps relative to the clock of the first E445 with­out potentially missing a bit of information. Because
the setup time on the serial input pin is negative, coinci­dent excursions on the data and clock inputs of the E445
will result in correct operation.

Figure 3. Cascade Frequency Limitation

PARALLEL

DATA

PARALLEL

DATA

TO SERIAL

MEDIUM

FROM SERIAL

MEDIUM

SOUT

SOUT*

SINA

SINA*

SERIAL

INPUT

DATA

SIN
SIN*

SOUT

SOUT*

E445a

Q3 Q2 Q1 Q0

Q7 Q6 Q5 Q4

SIN
SIN*

E445b

Q3 Q2 Q1 Q0

Q3 Q2 Q1 Q0

CLOCK

CLOCK*

CLOCK

Tpd CLK
to SOUT

PARALLEL OUTPUT DATA

800 ps

100 ps

115 0 ps

CLOCK A

CLOCK B

Tpd CLK
to SOUT

800 ps

1150 ps

4

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HIGH-PERFORMANCE PRODUCTS

SK10/100E445

Revision 1/February 21, 2001

Application Information (continued)

Perhaps the easiest way to delay the second clock relative
to the first is to take advantage of the differential clock
inputs on the E445. By connecting the clock for the
second E445 to the complimentary clock input pin, the
device will clock a half a clock period after the first E445
(Figure 5). Utilizing this simple technique will raise the
potential conversion frequency up to 1.4 GHz. The divide

by eight clock of the second E445 should be used to
synchronize the parallel data to the rest of the system
as the parallel data of the two E445’s will no longer by
synchronized. This skew problem between the outputs
can be worked around as the parallel information will be
static for eight more clock pulses.

Figure 7. Extended Frequency 1:8 Demultiplexer

Figure 8. Timing Diagram A: 1:8 Serial to Parallel Conversion

SERIAL

INPUT

DATA

SIN
SIN*

SOUT

SOUT*

E445a

Q3 Q2 Q1 Q0

Q7 Q6 Q5 Q4

SIN
SIN*

E445b

Q3 Q2 Q1 Q0

Q3 Q2 Q1 Q0

CLOCK

CLOCK*

CLOCK A

CLOCK B

Tpd CLK
to SOUT

PARALLEL OUTPUT DATA

800 ps

100 ps

1150 ps

Dn-4

Dn-3 Dn-2 Dn-1 Dn Dn+1 Dn+2

Dn+3

Dn-4

Dn-3 Dn-2 Dn-1 Dn Dn+1 Dn+2

Dn+3

CLK

SIN

Q0

SOUTa

Dn-4

Dn-3 Dn-2 DnÐ1DnDn+1

SOUTa

CL/8a

CL/8b

CL/4a

CL/4b

Dn–4

Q1 Dn–3

Q2 Dn–2

Q3 Dn–41

Q4 (Q0 a)

Q5 (Q1 a)

Q6 (Q2 a)

Q7 (Q3 a)

Dn

Dn+1

Dn+2

Dn+3

5

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HIGH-PERFORMANCE PRODUCTS

SK10/100E445

Revision 1/February 21, 2001

Package Information

PIN Descriptions

MIDNIMXAMNIMXAM

A584.0594.023.2175.21

B584.0594.023.2175.21

C561.0081.002.475.4

E090.0011.092.297.2

F310.0910.033.084.0

G050.0CSB72.1CSB

H620.0230.066.018.0

J020.0--15.0--

K520.0--46.0--

R054.0654.034.1185.11

U054.0654.034.1185.11

V240.0840.070.112.1

W240.0840.070.112.1

X240.0650.070.124.1

Y--020.0--05.0

Z2

o

01

o

2

o

01

o

1G014.0034.024.0129.01

1K040.0--20.1--

MILLIMETERS

INCHES

NOTES:

1. Datums -L-, -M-, and -N- determined where top of lead
shoulder exits plastic body at mold parting line.

2. DIM G1, true position to be measured at Datum -T-,
Seating Plane.

3. DIM R and U do not include mold flash. Allowable mold flash
is 0.010 (0.250) per side.

4. Dimensioning and tolerancing per ANSI Y14.5M, 1982.

5. Controlling Dimension: Inch.

6. The package top may be smaller than the package bottom by
up to 0.012 (0.300). Dimensions R and U are determined at
the outermost extremes of the plastic body exclusive of mold
flash, tie bar burrs, gate burrs and interlead flash, but
including any mismatch between the top and bottom of the
plastic body.

7. Dimension H does not include Dambar protrusion or
intrusion. The Dambar protrusion(s) shall not cause the H
dimension to be greater than 0.037 (0.940). The Dambar
intrusion(s) shall not cause the H dimension to be smaller
than 0.025 (0.635).

–L–

–M–

–N–

28 1

V

W

Y BRK

D

D

Z

0.007 (0.180) T L – M N

S

S

0.007 (0.180) T L – M N

M

S

S

J

A

R

EE

C

G1

G

0.004 (0.100)

–T–

SEATING PLANE

VIEW S

0.010 (0.250) T L – M N

S

S

M

++

+

S

K

K1

H

F

0.007 (0.180) T L – M N

M

S

0.007(0.180) T L – M N

M

S

S

S

+

+

Z

X

U

B

G1

0.007 (0.180) T L - M N

S

S

0.007 (0.180) T L - M N

M

S

S

0.010 (0.250) T L - M N

S

S

M

S

VIEW S

6

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HIGH-PERFORMANCE PRODUCTS

SK10/100E445

Revision 1/February 21, 2001

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SK10E445 DC Electrical Characteristics

(VEE = VEE(min) to VEE(max); VCC = VCCO = GND)

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Note 1: The maximum VOH limit was relaxed from standard ECL due to the high frequency output design. All other outputs

are specified with the standard 10E and 100E VOH levels.

TA = 0oC TA = +25oC TA = +85oC

SK100E445 DC Electrical Characteristics

(VEE = VEE(min) to VEE(max); VCC = VCCO = GND)

TA = 0oC

TA = +25

o

C

TA = +85

o

C

DC Characteristics

7

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HIGH-PERFORMANCE PRODUCTS

SK10/100E445

Revision 1/February 21, 2001

Note: 1. For Standard ECL DC Specifications, refer to the ECL Logic Family Standard DC Specification Data
Sheet.

2. For part ordering description, see HPP Part Ordering Information Data Sheet.

AC Characteristics

SK10/100E445 AC Electrical Characteristics

(VEE = VEE(min) to VEE(max); VCC = VCCO = GND)

lobmyScitsiretcarahCniMpyTxaMniMpyTxaMniMpyTxaMtinUnoitidnoC

f

xam

ycneuqerFnoisrevnoCmumixaM0.20.20.2

s/BG

ZRN

t

HLP

t

LHP

tuptuOotyaleDnoitagaporP

QotKLC

TUOSotKLC
4/LCotKLC
8/LCotKLC

0051

008

0011
0011

0081

579

5231
5231

0012
0511
0051
0051

0051

008

0011
0011

0081

579

5231
5231

0012
0511
0051
0051

0051

008

0011
0011

0081

579

5231
5231

0012
0511
0051
0051

sp
sp
sp
sp

t

s

emiTputeS

BNIS,ANIS

LES

001-

0

052­002-

001-

0

052­002-

001-

0

052­002-

sp
sp

t

h

emiTdloH

LES,BNIS,ANIS054003054003054003sp

t

RR

emiTyrevoceRteseR005003005003005003sp

t

WP

htdiWesluPmuminiM

RM,KLC004004004sp

t

rt,f

semiTllaF/esiR

TUOS

8/LC.4/LC

nQ

031
002
073

522
524
094

072
025
007

031
002
073

522
524
094

072
025
007

031
002
073

522
524
094

072
025
007

sp
sp
sp

%08-%02

TA = 0oC TA = +25oC TA = +85oC

Timing Diagram A. 1:4 Serial to Parallel Conversion

Dn-4

Dn-3

Dn-4

Dn-2 Dn-1 DnDnDn+1 Dn+2

Dn+3

Dn-4

Dn-3 Dn-2 Dn-1 Dn Dn+1 Dn+2

Dn+3

Dn-3

Dn+1

Dn-2

Dn+2

Dn-1

Dn+3

CLK

SIN

RESET

Q0

Q1

Q2

Q3

SOUT

CL/4

CL/8

8

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HIGH-PERFORMANCE PRODUCTS

SK10/100E445

Revision 1/February 21, 2001

Ordering Information

edoCgniredrODIegakcaPegnaRerutarepmeT

JP544E01KSCCLP-82lairtsudnI

TJP544E01KSCCLP-82lairtsudnI

JP544E001KSCCLP-82lairtsudnI

TJP544E001KSCCLP-82lairtsudnI

AC Characteristics (continued)

Timing Diagram B. 1:4 Serial to Parallel Conversion with SYNC Pulse

Dn-4

Dn-3

Dn-4

Dn-2 Dn-1 Dn

Dn+1

Dn+1 Dn+2 Dn+3

Dn+4

Dn-4

Dn-3 Dn-2 Dn-1 Dn Dn+1 Dn+2

Dn+3

Dn-3

Dn+2

Dn-2

Dn+3

Dn-1 Dn+4

Dn+4

CLK

SIN

RESET

SYNC

Q0

Q1

Q2

Q3

SOUT

CL/4

CL/8

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