Datasheet SK100E142PJ, SK100E142PJT, SK10E142PJ, SK10E142PJT Datasheet (Semtech Corporation)

HIGH-PERFORMANCE PRODUCTS

1

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Revision 1/February 14, 2001

SK10/100E142

9-Bit Shift Register

Description

Features

Functional Block Diagram

The SK10E/100E142 is a 9-bit shift register, designed
with byte-parity applications in mind. The E142 performs
serial/parallel in and serial/parallel out, shifting in one
direction. The nine inputs D0 – D8 accept parallel input
data, while S-IN accepts serial input data. The Qn outputs
do not need to be terminated for the shift operation to
function. To minimize noise and power, any Q output not
used should be left unterminated.

The SEL (Select) input pin is used to switch between the
two modes of operation – SHIFT and LOAD. The shift
direction is from bit 0 to bit 8. Input data is accepted by
the registers at set-up time before the posiitive going
edge of CLK1 or CLK2. Shifting is also accomplished
on the positive clock edge. A HIGH on the Master Reset
pin (MR) asynchronously resets all the registers to zero.

• 700 MHz Minimum Shift Frequency

• 9-Bit for Byte-Parity Applications

• Asynchronous Master Reset

• Dual Clocks

• Extended 100E V

EE

Range of –4.2 to –5.5V

• 75KΩ Internal Input Pulldown Resistors

• Fully Compatible with MC10E142 and
MC100E142

• Specified over Industrial Temperature Range:
–40oC to 85oC

• ESD Protection of >4000V

• Available in 28-pin PLCC Package

PIN Description

Pin Names

Pinout

Q

7

Q

6

V

CC

Q5

V

CC0

Q

4

Q

3

MR

CLK1

CLK2

V

EE

S-IN

D

0

D

1

D2D3D

4

V

CC0

Q0Q1Q

2

SEL

D8D7D6D5V

CC0

Q

8

1

2

3

4

25 24 23 22 21 20 19

567891011

26

27

28

18

17

16

15

14

13

12

28 Lead PLCC

(Top View)

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0D-8D

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2KLC,1KLC

RM

0Q-8Q

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Functions

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H

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1

0

Q

D

1

0

Q

D

1

0

Q

D

1

0

Q

D

1

0

Q

D

Q

0

Q

1

Q

2

Q

3

D

0

D

1

D

2

D

3

D

8

SEL

CLK1

CLK2

MR

Q

8

S-IN

2

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HIGH-PERFORMANCE PRODUCTS

SK10/100E142

Revision 1/February 14, 2001

Package Information

PIN Descriptions

–L–

–M–

–N–

28 1

V

W

Y BRK

D

D

Z

0.007 (0.180) T L – M N

S

S

0.007 (0.180) T L – M N

M

S

S

J

A

R

EE

C

G1

G

0.004 (0.100)

–T–

SEATING PLANE

VIEW S

0.010 (0.250) T L – M N

S

S

M

++

+

S

+

+

Z

X

U

B

G1

0.007 (0.180) T L - M N

S

S

0.007 (0.180) T L - M N

M

S

S

0.010 (0.250) T L - M N

S

S

S

M

K

K1

H

F

0.007 (0.180) T L – M N

M

S

0.007(0.180) T L – M N

M

S

S

S

View S

MIDNIMXAMNIMXAM

A584.0594.023.2175.21

B584.0594.023.2175.21

C561.0081.002.475.4

E090.0011.092.297.2

F310.0910.033.084.0

G050.0CSB72.1CSB

H620.0230.066.018.0

J020.0--15.0--

K520.0--46.0--

R054.0654.034.1185.11

U054.0654.034.1185.11

V240.0840.070.112.1

W240.0840.070.112.1

X240.0650.070.124.1

Y--020.0--05.0

Z2

o

01

o

2

o

01

o

1G014.0034.024.0129.01

1K040.0--20.1--

MILLIMETERS

INCHES

NOTES:

1. Datums -L-, -M-, and -N- determined where top of lead
shoulder exits plastic body at mold parting line.

2. DIM G1, true position to be measured at Datum -T-,
Seating Plane.

3. DIM R and U do not include mold flash. Allowable
mold flash is 0.010 (0.250) per side.

4. Dimensioning and tolerancing per ANSI Y14.5M,

1982.

5. Controlling Dimension: Inch.

6. The package top may be smaller than the package
bottom by up to 0.012 (0.300). Dimensions R and U
are determined at the outermost extremes of the
plastic body exclusive of mold flash, tie bar burrs,
gate burrs and interlead flash, but including any
mismatch between the top and bottom of the plastic
body.

7. Dimension H does not include Dambar protrusion or
intrusion. The Dambar protrusion(s) shall not cause
the H dimension to be greater than 0.037 (0.940).
The Dambar intrusion(s) shall not cause the H
dimension to be smaller than 0.025 (0.635).

3

Revision 1/February 14, 2001

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HIGH-PERFORMANCE PRODUCTS

SK10/100E142

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Am
Am

TA = –40oC

TA = 0

o

C

TA = +25oC

TA = +85oC

SK10/100E142 DC Electrical Characteristics (Notes 1, 2)

VCC – VEE = 4.2V to 5.5V; V

OUT

Loaded 50

ΩΩ

ΩΩ

Ω to VCC – 2.0V)

DC Characteristics

AC Characteristics

SK10/100E142 AC Electrical Characteristics

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3201

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05

003

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VCC – VEE = 4.2V to 5.5V; V

OUT

Loaded 50

ΩΩ

ΩΩ

Ω to VCC – 2.0V)

TA = 0oC TA = +25oC TA = +85oCTA = –40oC

4

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HIGH-PERFORMANCE PRODUCTS

SK10/100E142

Revision 1/February 14, 2001

Ordering Information

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JP241E01KSCCLP-82lairtsudnI

TJP241E01KSCCLP-82lairtsudnI

JP241E001KSCCLP-82lairtsudnI

TJP241E001KSCCLP-82lairtsudnI

Notes:

1. 10E circuits are designed to meet the DC specifications shown in the table after thermal equilibrium
has been established. The circuit is in a test socket or mounted on a printed circuit board and
transverseairflow greater than 500 lfpm is maintained. Outputs are terminated through a 50Ω
resistor to VCC–2.0V.

2. 100K circuits are designed to meet the DC specification shown in the table where transverse airflow
greater than 500 lfpm is maintained.

3. Within device skew is defined as identical transitions on similar paths through a device.

4. For standard ECL DC specifications, refer to the ECL Logic Family Standard DC Specifications Data

Sheet.

5. For part oredering description, see HPP Part Ordering Information Data Sheet.

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Contact Information

AC Characteristics (continued)