Datasheet SK100E131PJ, SK100E131PJT, SK10E131PJ, SK10E131PJT Datasheet (Semtech Corporation)
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HIGH-PERFORMANCE PRODUCTS
1
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Revision 1/February 13, 2001
SK10/100E131
4-Bit D Flip-Flop
Description
Features
Functional Block Diagram
The SK10E/100E131 is a Quad master-slave D-type flipflop with differential outputs. Each flip-flop may be
clocked separately by holding Common Clock (CC) LOW
and using the Clock Enable (CE*) inputs for clocking.
Common clocking is achieved by holding the CE inputs
LOW and using CC to clock all four flip-flops. In this
case, the CE* inputs perform the function of controlling
the common clock to each flip-flop.
Individual asynchronous resets are provided (R).
Asynchronous set controls (S) are ganged together in
pairs, with the pairing chosen to reflect physical chip
symmetry.
Data enters the master when both CC and CE* are LOW,
and transfers to the slave when either CC or CE (or both)
go HIGH.
• 1100 MHz Minimum Toggle Frequency
• Differential Outputs
• Individual and Common Clocks
• Individual Resets (asynchronous)
• Paired Sets (asynchronous)
• Extended 100E VEE Range of –4.2V to –5.5V
• 75KΩ Internal Input Pulldown Resistors
• Fully Compatible with MC10E131 and
MC100E131
• Specified Over Industrial Temperature Range:
–40
o
C to 85oC
• ESD Protection of >4000V
• Available in 28-pin PLCC Package
Q
Q
D
S
R
Q3
D3
CE3*
R3
D2
CE2*
R2
R1
S03
S12
CC
CE1*
D1
R0
CE0*
D0
Q3*
Q
Q
D
S
R
Q2
Q2*
Q
Q
D
S
R
Q1*
Q1
Q
Q
D
S
R
Q0*
Q0
PIN Description
niPnoitcnuF
0D-3D
*0EC-*3EC
0R-3R
CC
21S,30S
0Q-3Q
*0Q-*3Q
stupnIataD
)laudividni(selbanEkcolC
steseR
kcolCnommoC
)deriap(steS
stuptuOeurT
stuptuOgnitrevnI
Pin Names
Pinout
Q2*
Q2
VCC
Q1*
Q1
Q0*
Q0
CE3*
D3
S12
VEE
CC
S03
D0
CE0*
R0
D1
CE1*
R1
NC
VCC0
R3
D2
CE2*
R2
VCC0
Q3*
Q3
1
2
3
4
25 24 23 22 21 20 19
567891011
26
27
28
18
17
16
15
14
13
12
28 Lead PLCC
(Top View)
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Revision 1/February 13, 2001
www.semtech.com
HIGH-PERFORMANCE PRODUCTS
SK10/100E131
Package Information
PIN Descriptions
–L–
–M–
–N–
28 1
V
W
Y BRK
D
D
Z
0.007 (0.180) T L – M N
S
S
0.007 (0.180) T L – M N
M
S
S
J
A
R
EE
C
G1
G
0.004 (0.100)
–T–
SEATING PLANE
VIEW S
0.010 (0.250) T L – M N
S
S
M
++
+
S
+
+
Z
X
U
B
G1
0.007 (0.180) T L - M N
S
S
0.007 (0.180) T L - M N
M
S
S
0.010 (0.250) T L - M N
S
S
S
M
K
K1
H
F
0.007 (0.180) T L – M N
M
S
0.007(0.180) T L – M N
M
S
S
S
View S
MIDNIMXAMNIMXAM
A584.0594.023.2175.21
B584.0594.023.2175.21
C561.0081.002.475.4
E090.0011.092.297.2
F310.0910.033.084.0
G050.0CSB72.1CSB
H620.0230.066.018.0
J020.0--15.0--
K520.0--46.0--
R054.0654.034.1185.11
U054.0654.034.1185.11
V240.0840.070.112.1
W240.0840.070.112.1
X240.0650.070.124.1
Y--020.0--05.0
Z2
o
01
o
2
o
01
o
1G014.0034.024.0129.01
1K040.0--20.1--
MILLIMETERS
INCHES
NOTES:
1. Datums -L-, -M-, and -N- determined where top of lead
shoulder exits plastic body at mold parting line.
2. DIM G1, true position to be measured at Datum -T-,
Seating Plane.
3. DIM R and U do not include mold flash. Allowable
mold flash is 0.010 (0.250) per side.
4. Dimensioning and tolerances per ANSI Y14.5M,
1982.
5. Controlling Dimension: Inch.
6. The package top may be smaller than the package
bottom by up to 0.012 (0.300). Dimensions R and U
are determined at the outermost extremes of the
plastic body exclusive of mold flash, tie bar burrs,
gate burrs and interlead flash, but including any
mismatch between the top and bottom of the plastic
body.
7. Dimension H does not include Dambar protrusion or
intrusion. The Dambar protrusion(s) shall not cause
the H dimension to be greater than 0.037 (0.940).
The Dambar intrusion(s) shall not cause the H
dimension to be smaller than 0.025 (0.635).
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HIGH-PERFORMANCE PRODUCTS
SK10/100E131
DC Characteristics
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I
HI
tnerruCHGIHtupnI
CC
S
EC,R
D
053
054
003
051
053
054
003
051
053
054
003
051
053
054
003
051
Aµ
Aµ
Aµ
Aµ
I
EE
tnerruCylppuSrewoP
E01
E001
13
43
25
65
33
63
45
06
33
83
55
26
53
24
75
86
Am
Am
SK10/100E131 DC Electrical Characteristics (Notes 1, 2)
(V
CC
– VEE = 4.2V to 5.5V; VOUT Loaded 50
ΩΩ
ΩΩ
Ω to V
CC
– 2.0V)
TA = –40oC TA = 0oC TA = +25oC TA = +85oC
AC Characteristics
SK10/100E131 AC Electrical Characteristics
lobmyScitsiretcarahCniMpyTxaMniMpyTxaMniMpyTxaMniMpyTxaMtinU
f
XAM
ycneuqerFelggoT.xaM00010041001100410011004100110041zHM
t
HLP
t
LHP
tuptuOotyaleDnoitagaporP
EC
CC
R
S
514
572
544
335
816
527
396
447
524
523
454
345
416
576
486
647
234
523
064
055
406
576
376
636
254
523
774
175
185
576
056
517
sp
sp
sp
sp
t
s
emiTputeS
D00202051020510205102sp
t
H
emiTdloH
D522-02571-0257102-57102-sp
t
RR
emiTyrevoceRteseR054051004051004051004051sp
t
WP
htdiWesluPmuminiM
KLC
S,R
004
004
004
004
004
004
004
004
sp
sp
t
WEKS
wekSeciveDnihtiW
3
06060606sp
t
r/tf
semiTllaF/esiR
E01
E001
712
963
523
095
222
543
043
575
522
713
543
525
032
352
563
704
sp
sp
(V
CC
– VEE = 4.2V to 5.5V; VOUT Loaded 50
ΩΩ
ΩΩ
Ω to V
CC
– 2.0V)
TA = –40oC TA = 0oC TA = +25oC TA = +85oC
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Revision 1/February 13, 2001
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HIGH-PERFORMANCE PRODUCTS
SK10/100E131
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JP131E01KSCCLP-82lairtsudnI
TJP131E01KSCCLP-82lairtsudnI
JP131E001KSCCLP-82lairtsudnI
TJP131E001KSCCLP-82lairtsudnI
Notes:
1. 10E circuits are designed to meet the DC specifications shown in the table after thermal equilibrium has
been established. The circuit is in a test socket or mounted on a printed circuit board and transverse
airflow greater than 500 lfpm is maintained.
2. The same DC parameter values apply across the full VEE range of –4.2 to –5.5V. 100E circuits are
designed to meet the DC specifications shown in the table where transverse airflow greater than 500 lfpm
is maintained.
3. Within device skew is defined as identical transitions on similar paths through a device.
4. For standard ECL DC Specifications, refer to the ECL Logic Family Standard DC Data
Sheet.
5. For part ordering description, see HPP Part Ordering Information Data Sheet.
Division Headquarters
10021 Willow Creek Road
San Diego, CA 92131
Phone: (858) 695-1808
FAX: (858) 695-2633
Marketing Group
1111 Comstock Street
Santa Clara, CA 95054
Phone: (408) 566-8776
FAX: (408) 727-8994
Semtech Corporation
High-Performance Products Division
Contact Information
Ordering Information
AC Information (continued)
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