Datasheet SK100E111PJ, SK100E111PJT, SK10E111PJ, SK10E111PJT Datasheet (Semtech Corporation)

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Revision 1 /February 13, 2001

The SK10E/100E111 is a low skew 1-to-9 differential
driver designed with clock distribution in mind. It accepts
one signal input which can be either differential or single­ended if the VBB output is used. The signal is fanned
out to 9 identical differential outputs. An enable input
is also provided. A HIGH disables the device by forcing
all Q outputs LOW and all Q* outputs HIGH.

The device is specifically designed, modeled, and
produced with low skew as the key goal. Optimal design
and layout serve to minimize gate-to-gate skew within­device, and characterization is used to determine process
control limits that ensure consistent tpd distributions
from lot to lot. The net result is a dependable, guaranteed
low skew device.

To ensure that the tight skew specification is met, it is
necessary that both sides of the differential output are
terminated into 50Ω , even if only one side is being used.
In most applications, all nine differential pairs will be
used and therefore terminated. In the case where fewer
than nine pairs are used, it is necessary to terminate at
least the output pairs on the same package side (i.e.
sharing the same V

CCO

) as the pair(s) being used on
that side in order to maintain minimum skew. Failure to
do this will result in small degradations of propagation
delay (on the order of 10–20ps) of the output(s) being
used which, while not being catastrophic to most designs,
will mean a loss of skew margin.

SK10/100E111

1:9 Differential

Clock Driver

Description

Features

Functional Block Diagram

PRELIMINARY

• Low Skew

• Guaranteed Skew Spec

• Differential Design

•V

BB

Output

• Enable Input

• Extended 100E V

EE

Range of –4.2 to –5.5V

• 75KΩ Internal Input Pulldown Resistors

• Fully Compatible with MC10E111 and
MC100E111

• Specified Over Industrial Temperature Range:
–40oC to 85oC

• ESD Protection of >4000V

• Available in 28-pin PLCC Package

Q0

Q0*

Q1

Q

1*

Q2

Q

2*

Q3

Q

3*

Q4

Q

4*

Q5

Q

5*

Q6

Q

6*

Q7

Q

7*

Q8

Q

8*

IN

*

V

BB

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HIGH-PERFORMANCE PRODUCTS

SK10/100E111

Revision 1 /February 13, 2001

PIN Description

Pin Names

Pinout

Q3

Q3*

Q4

VCC0

Q4*

Q5

Q5*

VEE

EN*

IN

VCC

IN*

VBB

N/C

Q8*

Q8

Q7*

VCC0

Q7

Q6*

Q6

Q0

Q0*

Q1

VCC0

Q1*

Q2

Q2*

1

2

3

4

25 24 23 22 21 20 19

567891011

26

27

28

18

17

16

15

14

13

12

28 Lead PLCC

(Top View)

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HIGH-PERFORMANCE PRODUCTS

SK10/100E111

Revision 1 /February 13, 2001

Package Information

PIN Descriptions

MID NIM XAM NIM XAM

A584.0594.023.2175.21

B584.0594.023.2175.21

C561.0081.002.475.4

E090.0011.092.297.2

F310.0910.033.084.0

G050.0CSB72.1CSB

H620.0230.066.018.0

J020.0--15.0--

K520.0--46.0--

R054.0654.034.1185.11

U054.0654.034.1185.11

V240.0840.070.112.1

W240.0840.070.112.1

X240.0650.070.124.1

Y--020.0--05.0

Z2

o

01

o

2

o

01

o

1G014.0034.024.0129.01

1K040.0--20.1--

MILLIMETERSINCHES

NOTES:

1. Datums –L–, –M–, and –N– determined where top of

lead shoulder exits plastic body at mold parting line.

2. DIM G1, true position to be measured at Datum –T–,

Seating Plane.

3. DIM R and U do not include mold flash. Allowable

mold flash is 0.010 (0.250) per side.

4. Dimensioning and tolerancing per ANSI Y14.5M,

1982.

5. Controlling Dimension: Inch.

6. The package top may be smaller than the package

bottom by up to 0.012 (0.300). Dimensions R and U
are determined at the outermost extremes of the
plastic body exclusive of mold flash, tie bar burrs, gate
burrs and interlead flash, but including any mismatch
betweeen the top and bottom of the plastic body.

7. Dimension H does not include Dambar protrusion or

intrusion. The Dambar protrusion(s) shall not cause
the H dimension to be greater than 0.037 (0.940).
The Dambar intrusion(s) shall not cause the H
dimension smaller than 0.025 (0.635).

+

+

Z

X

U

B

G1

0.007 (0.180) T L - M N

S

S

0.007 (0.180) T L - M N

M

S

S

0.010 (0.250) T L - M N

S

S

S

M

K

K1

H

F

0.007 (0.180) T L – M N

M

S

0.007(0.180) T L – M N

M

S

S

S

–L–

–M–

–N–

28 1

V

W

Y BRK

D

D

Z

0.007 (0.180) T L – M N

S

S

0.007 (0.180) T L – M N

M

S

S

J

A

R

EE

C

G1

G

0.004 (0.100)

–T–

SEATING PLANE

VIEW S

0.010 (0.250) T L – M N

S

S

M

++

+

S

VIEW S

4

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HIGH-PERFORMANCE PRODUCTS

SK10/100E111

Revision 1 /February 13, 2001

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SK10/100E111 AC Electrical Characteristics

(V

CC

– VEE = 4.2V to 5.5V; VOUT Loaded 50

ΩΩ

ΩΩ

Ω to V

CC

– 2.0V)

AC Characteristics

SK10/100E111 DC Electrical Characteristics (Notes 1, 2)

(V

CC

– VEE = 4.2V to 5.5V; VOUT Loaded 50

ΩΩ

ΩΩ

Ω to V

CC

– 2.0V)

DC Characteristics

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HIGH-PERFORMANCE PRODUCTS

SK10/100E111

Revision 1 /February 13, 2001

IN

IN*

EN*

Q*

Q

t

h

50%

≤75 mV

≤75 mV

Figure 1. Setup Time

Figure 2. Hold Time

Figure 3. Release Time

IN

IN*

EN*

Q*

Q

t

s

50%

≤75 mV

≤75 mV

IN

IN*

EN*

Q*

Q

t

r

50%

Notes:

1. 10E circuits are designed to meet the DC specifications shown in the table after thermal equilibrium has
been established. The circuit is in a test socket or mounted on a printed circuit board and transverse
airflow greater than 500 lfpm is maintained.

2. 100E circuits are designed to meet the DC specifications shown in the table where transverse airflow
greater than 500 lfpm is maintained.

3. Differential input voltage required to obtain a full ECL swing on the outputs.

4. V

CMR

range is referenced to the most positive side of the differential input signal. Normal operation is
obtained if the high level falls within the specified range and the peak-to-peak voltage lies between
VPP(min) and 1V. The lower end of V

CMR

range varies 1:1 with VEE and is equal to VEE+1.6V.

5. The differential propagation delay is defined as the delay from the crossing points of the differential
input signals to the crossing point of the differential output signals.

6. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to
the 50% point of the output signal.

7. Enable is defined as the propagation delay from the 50% point of a negative transition on EN* to the
50% point of a positive transition on Q (or a negative transition on Q). Disable is defined as the
propagation delay from the 50% point of a positive transition on EN* to the 50% point of a negative
transition on Q (or a positive transition on Q).

8. The within-device skew is defined as the worst case difference between any two similar delay paths
within a single device.

9. The setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to
prevent an output response greater than ±75 mV to that IN/IN transition (see Figure 1).

10. The hold time is the minimum time that EN must remain asserted after a negative going IN or a positive
going IN* to prevent an output response greater than ±75 mV to the IN/IN transition (see Figure 2).

11. The release time is the minimum time that EN must be deasserted prior to the next IN/IN* transition to
ensure an output response that meets the specified IN to Q propagation delay and output transition times
(see Figure 3).

12. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the
propagation delay. The VPP(min) is AC limited for the E111 as a differential input as low as 250 mV
will still produce full ECL levels at the output.

13. Voltages referenced to VCC = 0V.

14. For standard ECL DC specifications, refer to the ECL Logic Family Standard DC Specifications Data

Sheet.

15. For part ordering descriptions, see HPP Part Ordering Information Data Sheet.

AC Characteristics (continued)

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HIGH-PERFORMANCE PRODUCTS

SK10/100E111

Revision 1 /February 13, 2001

Ordering Information

edoCgniredrODIegakcaPegnaRerutarepmeT

JP111E01KSCCLP-82lairtsudnI

TJP111E01KSCCLP-82lairtsudnI

JP111E001KSCCLP-82lairtsudnI

TJP111E001KSCCLP-82lairtsudnI

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