Datasheet SK100E016PJ, SK100E016PJT, SK10E016PJ, SK10E016PJT Datasheet (Semtech Corporation)

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Revision 1/February 13, 2001

SK10/100E016

8-Bit Synchronous
Binary Up Counter

Description

Features

Functional Block Diagram

The SK10/100E016 is a high-speed synchronous,
presettable, cascadable 8-bit binary counter.

The counter features internal feedback of TC*, gated by
the TCLD (terminal count load) pin. When TCLD is LOW
(or left open, in which case it is pulled LOW by the internal
pull-downs), the TC* feedback is disabled, and counting
proceeds continuously, with TC* going LOW to indicate
an all-one state. When TCLD is HIGH, the TC* feedback
causes the counter to automatically reload upon TC* =
LOW, thus functioning as a programmable counter. The
Qn outputs do not need to be terminated for the count
function to operate properly. To minimize noise and
power, unused Q outputs should be left unterminated.

• 700 MHz Min Count Frequency

• 1000 ps CLK to Q, TC*

• Internal TC* Feedback (Gated)

• 8-Bit

• Fully Synchronous Counting and TC* Generation

• Asynchronous Master Reset

• Internal 75 kΩ Input Pulldown Resistors

• Extended 100E V

EE

Range of –4.2V to –5.46V

• Fully Compatible with MC10/100E016

• Available in 28-Pin PLCC Package

• ESD Protection of >4000V

CE*

Q0*

BIT 1

BIT

0

BIT 7

CE*
Q0*
Q1*

Q4*
Q5*
Q6*

Q2*
Q3*

P1 P7

Q0 Q1 Q7

5

TC*

TCL

D

CE*

PO

MR

CLK

MASTE

R

SLAVE

QOM*

QOM

BITS 2-

6

Note that this diagram is provided for understanding of logic operation only. It should not be used for propagation

delays as many gate functions are achieved internally without incurring a full gate delay.

8 Bit Binary Counter - Logic Counter

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HIGH-PERFORMANCE PRODUCTS

SK10/100E016

Revision 1/February 13, 2001

PIN Description

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7P-0PstupnI)teserP(ataDlellaraP

7Q-0QstuptuOataD

*ECtupnIlortnoCelbanEtnuoC

*EPtupnIlortnoCelbanEdaoLlellaraP

RMteseRretsaM

KLCkcolC

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DLCTtupnIlortnoCdaoL-CT

*EC*EPDLCTRMKLCnoitcnuF

XL X LZ P(lellaraPdaoL

n

Qotn)

LH L LZ tnuoCsuounitnoC

LH H LZ WOL=*CTnolellaraPdaoL;tnuoC

HH X L Z dloH

XX X L ZZ

,dnopseRsretsaM

dloHsevalS

XX X HX

,WOL=:nQ(teseR

)HGIH=:*CT

Pin Names

Function Table

Q

7

Q

6

V

CC

Q

5

V

CCO

Q

4

Q

3

MR

CLK

T

CLD

V

EE

NC

P

0

P

1

P2P3P

4

V

CCO

Q0Q1Q

2

PE*

CE*

P7P6P5V

CCO

TC*

1

2

3

4

25 24 23 22 21 20 19

567891011

26

27

28

18

17

16

15

14

13

12

28 Lead PLCC

(Top View)

Pinout

3

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HIGH-PERFORMANCE PRODUCTS

SK10/100E016

Revision 1/February 13, 2001

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daoL LX LX Z HHHL L H HHL LH

tnuoC HLLLZXXXXXHHHLHH

HLLLZXXXXXHHHHLH
HLLLZXXXXXHHHHHL
HLLLZHHHLLHHHLLH

daoL LX LX Z HHHL L H HHL LH

dloH HHLXZXXXXXHHHLLH

HHLXZXXXXXHHHLLH

nOdaoL HL L HZ HL HHL HHHLHH

lanimreT HLLHZHLHHLHHHHLH

tnuoC HL LHZHL HHL HHHHHL

HLLHZHLHHL HLHHLH
HL LHZHL HHL H L HHHH
HLLHZHLHHL HHLLLH

teseR XXHXXXXXXX L LLLLG

Function Table

Cascading Multiple E016 Devices

For applications which call for larger than 8-bit counters,
multiple E016s can be tied together to achieve very
wide bit width counters. The active low terminal count
(TC*) output and count enable input (CE*) greatly
facilitate the cascading of E016 devices. Two E016s
can be cascaded without the need for external gating;
however, for counters wider than 16 bits, external OR
gates are necessary for cascade implementations.

Figure 3 below illustrates the cascading of 4 E016s to
build a 32-bit high frequency counter. Note that the
E101 gates are used to OR the terminal count outputs
of the lower order E016s to control the counting
operation of the higher order bits. When the terminal
count of the preceding device (or devices) goes low
(the counter reaches an all 1s state), the more
significant E016 is set in its count mode and will count
one binary digit upon the next positive clock transition.
In addition, the preceding devices will also count one
bit, sending their terminal count outputs back to a high
state, disabling the count operation of the more
significant counters, and placing them back into hold
modes. Therefore, for an E016 in the chain to count,

all of the lower order terminal count outputs must
be in the low state. The bit width of the counter can
be increased or decreased by simply adding or
subtracting E016 devices from Figure 3 and
maintaining the logic pattern illustrated in the same
figure.

The maximum frequency of operation for the
cascaded counter chain is set by the propagation
delay of the TC* output, the necessary setup time
of the CE* input, and the propagation delay through
the OR gate controlling it (for 16-bit counters the
limitation is only the TC* propagation delay and the
CE* setup time). Figure 3 shows EL01 gates used
to control the count enable inputs; however, if the
frequency of operation is lower, a lower ECL OR gate
can be used. Using the worst case guarantees for
these parameters, the maximum count frequency
for a greater than 16-bit counter is 500 MHz, and
for a 16-bit counter is 625 MHz. Note that this
assumes the trace delay between the TC* outputs
and the CE* inputs are negligible. If this is not the
case, estimates of these delays need to be added
to the calculations.

Application Information

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SK10/100E016

Revision 1/February 13, 2001

Figure 3. 32-Bit Cascaded E016 Counter

Programmable Divider

The E016 has been designed with a control pin which
makes it ideal for use as an 8-bit programmable divider.
The TCLD pin (load on terminal count) when asserted
reloads the data present at the parallel input pin (Pn’s)
upon reaching terminal count (an all 1s state on the
outputs). Because this feedback is built internal to the
chip, the programmable division operation will run at very
nearly the same frequency as the maximum counting
frequency of the device. Figure 4 below illustrates the
input conditions necessary for utilizing the E016 as a
programmable divider set up to divide by 113.

Figure 4. Mod 2 to 256 Programmable Divider

To determine what value to load into the device to
accomplish the desired division, the designer simply
subtracts the binary equivalent of the desired divide ratio
from the binary value for 256. As an example for a divide
ratio of 113:

Pn’s = 256 – 113 = 8F

16

= 1000 1111

where:

PO = LSB and P7 = MSB

Forcing this input condition as per the setup in Figure
4 will result in the waveforms of Figure 5. Note that
the TC* output is used as the divide output and the
pulse duration is equal to a full clock period. For
even divide ratios, twice the desired divide ratio can
be loaded into the E016, and the TC* output can
feed the clock input of a toggle flip-flop to create a
signal divided as desired with a 50% duty cycle.

ediviD

oitaR7P6P5P4P3P2P1P0P

2 HHHHHHHL

3 HHHHHHLH

4 HHHHHHL L

5 HHHHHLHH

l llllllll

l llllllll

211 HLLHLLLL

311 HL L L HHHH

411 HLLLHHHL

l llllllll

l llllllll

452 LLLLLLHL

552 LLLLLLLH

652 LLLLLLLL

Preset Data InputsPreset Data Inputs

Preset Data InputsPreset Data Inputs

Preset Data Inputs

CE*

CLK

PE*

TC*

E016

LSB

CE*

CLK

PE*

TC*

E016

EL01

CE*

CLK

PE*

TC*

E016

CE*

CLK

PE*

TC*

E016
MSB

EL01

LOAD

CLOCK

Q0 ® Q7

P0 ® P7

Q0 ® Q7

P0 ® P7

Q0 ® Q7

P0 ® P7

Q0 ® Q7

P0 ® P7

PE*

CE*

TCLD

CLK

TC*

P7 P6 P5 P4 P3 P2 P1 P0

Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0

H

H

L

H

L LL HHHH

Application Information (continued)

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HIGH-PERFORMANCE PRODUCTS

SK10/100E016

Revision 1/February 13, 2001

A single E016 can be used to divide by any ratio from 2
to 256 inclusive. If divide ratios of greater than 256
are needed, multiple E016s can be cascaded in a
manner similar to that already discussed. When E016s
are cascaded to build larger dividers, the TCLD pin will
no longer provide a means for loading on terminal count.
Because one does not want to reload the counters until
all of the devices in the chain have reached terminal
count, external gating of the TC* pins must be used for
multiple E016 divider chains.

Figure 6 shows a typical block diagram of a 32-bit divider
chain. Once again, to maximize the frequency of
operation, EL01 OR gates were used. For lower
frequency applications, a slower OR gate could replace
the EL01. Note that for a 16-bit divider, the OR function
feeding the PE* (program enable) input CANNOT be
placed by a wire OR tie as the TC* output of the least
significant E016 must also feed the CE* input of the
most significant E016. If the two TC* outputs were OR
tied, the cascaded count operation would not operate
properly. Because, in the cascaded form, the PE*
feedback is external and requires external gating, the
maximum frequency of operation will be significantly less
than the same operation in a single device.

Maximizing E016 Count Frequency

The E016 device produces 9 fast transitioning single­ended outputs, thus VCC noise can become significant
in situations where all of the outputs switch
simultaneously in the same direction. This VCC noise
can negatively impact the maximum frequency of
operation of the device. Since the device does not
need to have the Q outputs terminated to count properly,
it is recommended that if the outputs are not going to
be used in the rest of the system, they should be
terminated. Not terminating the unused outputs will
not only cut down the VCC noise generated, but will
also save in total system power dissipation. Following
these guidelines will allow designers to either be more
aggressive in their designs or provide them with an
extra margin to the published databook specifications.

Figure 5. Divide by 113 E016 Programmable Divider Waveforms

DIVIDE BY 113

CLOCK

PE*

TC*

LOAD LOAD1001 0000 1001 0001 1111 1100 1111 1101 1111 1110 1111 1111

Application Information (continued)

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HIGH-PERFORMANCE PRODUCTS

SK10/100E016

Revision 1/February 13, 2001

Figure 6. 32-Bit Cascaded E016 Programmable Divider

CE*

CLK

PE*

TC*

E016

LSB

CE*

CLK

PE*

TC*

E016

EL01

CE*

CLK

PE*

TC*

E016

CE*

CLK

PE*

TC*

E016

MSB

EL01

CLOCK

Q0 ® Q7

P0 ® P7

Q0 ® Q7

P0 ® P7

Q0 ® Q7

P0 ® P7

Q0 ® Q7

P0 ® P7

EL01

Application Information (continued)

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HIGH-PERFORMANCE PRODUCTS

SK10/100E016

Revision 1/February 13, 2001

Package Information

PIN Descriptions

MILLIMETERS

INCHES

NOTES:

1. Datums -L-, -M-, and -N- determined where top of lead
shoulder exits plastic body at mold parting line.

2. DIM G1, true position to be measured at Datum -T-,
Seating Plane.

3. DIM R and U do not include mold flash. Allowable
mold flash is 0.010 (0.250) per side.

4. Dimensioning and tolerancing per ANSI Y14.5M,

1982.

5. Controlling Dimension: Inch.

6. The package top may be smaller than the package
bottom by up to 0.012 (0.300). Dimensions R and U
are determined at the outermost extremes of the
plastic body exclusive of mold flash, tie bar burrs,
gate burrs and interlead flash, but including any
mismatch between the top and bottom of the plastic
body.

7. Dimension H does not include Dambar protrusion or
intrusion. The Dambar protrusion(s) shall not cause
the H dimension to be greater than 0.037 (0.940).
The Dambar intrusion(s) shall not cause the H
dimension to be smaller than 0.025 (0.635).

–L–

–M–

–N–

28 1

V

W

Y BRK

D

D

+

+

Z

X

U

B

G1

0.007 (0.180) T L - M N

S

S

0.007 (0.180) T L - M N

M

S

S

0.010 (0.250) T L - M N

S

S

M

S

Z

0.007 (0.180) T L – M N

S

S

0.007 (0.180) T L – M N

M

S

S

J

A

R

EE

C

G1

G

0.004 (0.100)

–T–

SEATING PLANE

VIEW S

0.010 (0.250) T L – M N

S

S

M

++

+

S

K

K1

H

F

0.007 (0.180) T L – M N

M

S

0.007(0.180) T L – M N

M

S

S

S

MIDNIMXAMNIMXAM

A584.0594.023.2175.21

B584.0594.023.2175.21

C561.0081.002.475.4

E090.0011.092.297.2

F310.0910.033.084.0

G050.0CSB72.1CSB

H620.0230.066.018.0

J020.0--15.0--

K520.0--46.0--

R054.0654.034.1185.11

U054.0654.034.1185.11

V240.0840.070.112.1

W240.0840.070.112.1

X240.0650.070.124.1

Y--020.0--05.0

Z2

o

01

o

2

o

01

o

1G014.0034.024.0129.01

1K040.0--20.1--

8

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HIGH-PERFORMANCE PRODUCTS

SK10/100E016

Revision 1/February 13, 2001

DC Characteristics

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I

HI

tnerruCHGIHtupnI051051051051Aµ

I

EE

tnerruCylppuSrewoP

E01

E001

151
151

471
581

151
151

471
581

151
151

471
581

151
151

471
581

Am
Am

SK10/100E016 DC Electrical Characteristics (Notes 1, 2)

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f

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ycneuqerFtnuoCmumixaM007009007009007009007009zHM

t

HLP

t

LHP

tuptuOotyaleDnoitagaporP

QotKLC

QotRM

*CTotKLC

*CTotRM

627
666
347
656

558
577
577
837

849
678
629
028

627
666
347
656

558
577
577
837

849
678
629
028

627
666
347
656

558
577
577
837

849
678
629
028

627
666
347
656

558
577
577
837

849
678
629
028

sp
sp
sp
sp

t

s

emiTputeS

nP

*EC
*EP

DLCT

051
006
006
005

03-

004
004
003

051
006
006
005

03-

004
004
003

051
006
006
005

03-

004
004
003

051
006
006
005

03-

004
004
003

sp
sp
sp
sp

t

h

emiTdloH

nP

*EC
*EP

DLCT

053
0
0

001

001
004­004­003-

053
0
0

001

001

004­004­003-

053
0
0

001

001

004­004­003-

053
0
0

001

001

004­004­003-

sp
sp
sp
sp

t

RR

emiTyrevoceRteseR009007009007009007009007sp

t

WP

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RM,KLC004004004004sp

t

rt,f

)%08-02(semiTllaF/esiR132603955132603955532813625442033064sp

(V

CC

– VEE = 4.2V to 5.5V;VCC = V

CCO

; VOUT Loaded 50

ΩΩ

ΩΩ

Ω to V

CC

– 2.0V)

TA = 0oC TA = +25oC TA = +85oCTA = –40oC

TA = 0oC TA = +25oC TA = +85oCTA = –40oC

Notes:

1. 10E circuits are designed to meet the DC specifications shown in the table after thermal equilibrium has
been established. The circuit is in a test socket or mounted on a printed circuit board and transverse
airflow greater than 500 lfpm is maintained.

2. The same DC parameter values apply across the full VEE range of –4.2 to –5.5V. 100E circuits are
designed to meet the DC specifications shown in the table where transverse airflow greater than 500 lfpm
is maintained.

3. For standard ECL DC specifications, refer to the ECL Logic Family Standard DC Specifications Data Sheet.

4. For part ordering descriptions, see HPP Part Ordering Information Data Sheet.

AC Characteristics

SK10/100E016 AC Electrical Characteristics

(V

CC

– VEE = 4.2V to 5.5V;VCC = V

CCO

; VOUT Loaded 50

ΩΩ

ΩΩ

Ω to V

CC

– 2.0V)

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HIGH-PERFORMANCE PRODUCTS

SK10/100E016

Revision 1/February 13, 2001

Ordering Information

edoCgniredrODIegakcaPegnaRerutarepmeT

JP610E01KSCCLP-82lairtsudnI

TJP610E01KSCCLP-82lairtsudnI

JP610E001KSCCLP-82lairtsudnI

TJP610E001KSCCLP-82lairtsudnI

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1111 Comstock Street

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Phone: [phone]

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High-Performance Products Division

Contact Information