Datasheet SIS5595 Datasheet (Silicon Integrated System Corp)

SiS5595 PCI System I/O Chipset

Pentium PCI System I/O Chipset

SiS5595

Preliminary

Rev. 2.0

Nov. 02, 1998

This specification is subject to change without notice. Silicon Integrated Systems
Corporation assumes no responsibility for any errors contained herein.

Copyright by Silicon Integrated Systems Corp., all rights reserved.

SiS5595 PCI System I/O Chipset

Contents

1 FEATURES.......................................................................................................1

1.1 SiS5595 PCI SYSTEM I/O....................................................................1

1.2 FUNCTIONAL BLOCK DIAGRAM ........................................................ 4

2 PIN ASSIGNMENT (TOP VIEW).......................................................................6

2.1 SiS5595 PIN ASSIGNMENT (TOP VIEW)............................................6

2.2 SiS5595 CHIP ALPHABETICAL PIN LIST............................................ 7

3 FUNCTIONAL DESCRIPTION ..........................................................................9

3.1 PCI BUS INTERFACE..........................................................................9

3.1.1 PCI TO ISA BUS BRIDGE ............................................................ 9

3.1.2 DISTRIBUTED DMA (DDMA)...................................................... 11

3.1.3 PC/PCI DMA............................................................................... 12

3.1.4 SERIAL IRQ (SIRQ)....................................................................12

3.2 ACPI /LEGACY PMU.......................................................................... 15

3.2.1 ADVANCED CONFIGURATION AND POWER INTERFACE
(ACPI) …………………………………………………………………..15

3.2.2 POWER MANAGEMENT UNIT...................................................33

3.3 SMBUS FUNCTIONAL DESCRIPTIONS............................................36

3.3.1 SMBUS HOST MASTER INTERFACE........................................36

3.3.2 SMBUS HOST SLAVE INTERFACE...........................................36

3.4 USB INTERFACE............................................................................... 37

3.5 DATA ACQUISITION MODULE (DAM) ............................................... 38

3.5.1 GENERAL DESCRIPTION.......................................................... 38

3.5.2 POWER SUPPLY VOLTAGE MONITORING..............................39

3.5.3 FAN SPEED MONITORING........................................................ 39

3.5.4 THE ROUND-ROBIN SAMPLING CYCLE..................................40

3.5.5 INTERFACE REGISTER BLOCK................................................41

3.5.6 INTERNAL REGISTERS............................................................. 41

3.6 INTEGRATED REAL TIME CLOCK (RTC).........................................41

3.6.1 REAL TIME CLOCK MODULE.................................................... 41

3.7 AUTOMATIC POWER CONTROL MODULE......................................44

3.7.1 APC REGISTERS.......................................................................45

3.7.2 APC FUNCTIONS....................................................................... 45

3.7.3 S3 (STR) FUNCTION RELATED SIGNALS................................50

3.8 INTEGRATED KEYBOARD CONTROLLER.......................................52

3.8.1 STATUS REGISTER...................................................................52

3.8.2 INPUT/OUTPUT BUFFER .......................................................... 53

3.8.3 INTERNAL OUTPUT PORT DEFINITIONS................................. 53

3.8.4 KEYBOARD INTERNAL BIOS COMMANDS ( I/O PORT 64H ).. 54

3.8.5 PASSWORD SECURITY AND KEYBOARD POWER UP

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SiS5595 PCI System I/O Chipset

FUNCTIONS............................................................................... 56

3.8.6 RELATED PCI TO ISA BRIDGE CONFIGURATION REGISTERS
………………………………………………………………………… 58

3.9 ISA BUS INTERFACE ........................................................................ 59

3.9.1 ISA BUS CONTROLLER ............................................................59

3.9.2 DMA CONTROLLER...................................................................59

3.9.3 INTERRUPT CONTROLLER......................................................59

3.9.4 INTERRUPT STEERING ............................................................ 60

3.9.5 TIMER/COUNTER......................................................................61

3.10 SYSTEM RESET................................................................................ 61

4 PIN DESCRIPTIONS.......................................................................................63

4.1 PCI/ISA BUS INTERFACE .................................................................63

4.2 PCI BUS + CPU INTERFACE............................................................. 65

4.3 KBC + MISC.......................................................................................67

4.4 USB CONTROLLER...........................................................................72

4.5 RTC.................................................................................................... 73

4.6 DATA ACQUISITION INTERFACE..................................................... 75

4.7 POWER PINS..................................................................................... 76

5 HARDWARE TRAP.........................................................................................77

6 REGISTER SUMMARY...................................................................................79

6.1 PCI TO ISA BRIDGE CONFIGURATION REGISTERS ...................... 79

6.2 LEGACY ISA REGISTERS.................................................................80

6.2.1 DMA REGISTERS ...................................................................... 80

6.2.2 INTERRUPT CONTROLLER REGISTERS.................................82

6.2.3 TIMER REGISTERS...................................................................82

6.2.4 OTHER REGISTERS .................................................................. 82

6.3 PMU CONFIGURATION REGISTERS ...............................................83

6.4 ACPI CONFIGURATION REGISTERS............................................... 84

6.5 SMBUS IO REGISTERS.....................................................................85

6.6 USB OPENHCI HOST CONTROLLER CONFIGURATION SPACE....85

6.6.1 USB CONFIGURATION SPACE (FUNCTION 2) ........................ 85

6.6.2 HOST CONTROLLER OPERATIONAL REGISTERS.................86

6.7 AUTOMATIC POWER CONTROL (APC) REGISTERS...................... 87

6.7.1 RTC REGISTERS.......................................................................87

6.8 DATA ACQUISITION MODULE (DAM) INTERNAL REGISTERS.......88

7 REGISTER DESCRIPTION............................................................................. 89

7.1 PCI TO ISA BRIDGE CONFIGURATION REGISTERS ...................... 89

7.2 PMU CONFIGURATION REGISTERS ............................................. 111

7.3 ACPI CONFIGURATION REGISTERS............................................. 134

7.4 SMBUS IO REGISTERS................................................................... 153

7.5 THE DATA ACQUISITION MODULE INTERNAL REGISTERS........ 160

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SiS5595 PCI System I/O Chipset

7.6 APC CONTROL REGISTERS .......................................................... 168

7.7 OTHER REGISTERS ....................................................................... 173

7.8 USB OPENHCI HOST CONTROLLER CONFIGURATION SPACE.. 173

7.8.1 CONTROL AND STATUS PARTITION..................................... 174

7.8.2 MEMORY POINTER PARTITION ............................................. 181

7.8.3 BITS FRAME COUNTER PARTITION...................................... 184

7.8.4 ROOT HUB PARTITION...........................................................187

7.8.5 LEGACY SUPPORT REGISTERS............................................194

8 ELECTRICAL CHARACTERISTICS..............................................................198

8.1 SiS5595 INTERNAL POWER PLANES............................................ 198

8.2 ABSOLUTE MAXIMUM RATINGS....................................................199

8.3 DC CHARACTERISTICS.................................................................. 199

8.4 INTERNAL RTC POWER CONSUMPTION...................................... 202

8.5 AC CHARACTERISTICS..................................................................203

8.5.1 SiS5595 DMA CONTROLLER AC CHARACTERISTICS.......... 203

8.5.2 SiS5595 PCI-TO-ISA CYCLES AC CHARACTERISTICS......... 204

8.5.3 SiS5595 MISC. AC CHARACTERISTICS ................................. 206

9 MECHANICAL DIMENSION..........................................................................209

9.1 SiS5595 (PQFP 208-PIN PLASTIC FLAT PACKAGE)...................... 209

10 COPYRIGHT NOTICE................................................................................ 210

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SiS5595 PCI System I/O Chipset

Figures

FIGURE 1.2-1 FUNCTIONAL BLOCK DIAGRAM .................................................... 4

FIGURE 2.1-1 PIN ASSIGNMENT (TOP VIEW) ...................................................... 6

FIGURE 3.1-1 PCI ISA DELAY TRANSACTION....................................................10

FIGURE 3.1-2 START FRAME TIMING WITH SOURCE SAMPLED A LOW PULSE

ON SMI# .......................................................................................... 13

FIGURE 3.1-3 STOP FRAME TIMING WITH HOST USING 17 SIRQ# SAMPLING

PERIOD ........................................................................................... 13

FIGURE 3.2-1 GLOBAL SYSTEM STATE DIAGRAM............................................16

FIGURE 3.2-2 WAKE UP EVENTS IN S1 / S2....................................................... 18

FIGURE 3.2-3 5595'S TIMING DIAGRAM IN S2 STATE ....................................... 18

FIGURE 3.2-4 NORTH BRIDGE/5595'S TIMING DIAGRAM IN S3 STATE ........... 19

FIGURE 3.2-5 STPCLK# THROTTLING & PERFORMANCE................................22

FIGURE 3.2-6 PROCESSOR POWER STATE DIAGRAM.....................................23

FIGURE 3.2-7 STPCLK# SOURCE ....................................................................... 24

FIGURE 3.2-8 THERMAL DETECTION LOGIC..................................................... 25

FIGURE 3.2-9 SCI / SMI# EVENTS OVERVIEW.................................................. 27

FIGURE 3.2-10 GENERAL PURPOSE TIMER LOGIC..........................................28

FIGURE 3.2-11 GPIO LOGIC ................................................................................29

FIGURE 3.4-1 USB SYSTEM BLOCK DIAGRAM..................................................38

FIGURE 3.5-1 DATA ACQUISITION MODULE BLOCK DIAGRAM .......................39

FIGURE 3.6-1 RTC MODULE BLOCK DIAGRAM..................................................42

FIGURE 3.6-2 ADDRESS MAP OF THE STANDARD BANK................................. 43

FIGURE 3.6-3 BLOCK DIAGRAM OF RTC............................................................ 44

FIGURE 3.7-1 TYPICAL TIMING SEQUENCE ON THE POWER CONTROL

RELATED SIGNALS ...................................................................... 45

FIGURE 3.7-2 POWER UP REQUEST EVENTS...................................................47

FIGURE 3.7-3 POWER BUTTON ON EVENT ....................................................... 47

FIGURE 3.7-4 RING UP EVENT............................................................................ 48

FIGURE 3.7-5 POWER MANAGE EVENT 1..........................................................49

FIGURE 3.7-6 POWER MANAGE EVENT 0..........................................................49

FIGURE 3.7-7 POWER DOWN REQUEST EVE.................................................... 50

FIGURE 3.9-1 INTERRUPT ROUTER IRX............................................................61

FIGURE 3.10-1 TIMING SEQUENCE FOR POWER-ON PROCESS..................... 62

FIGURE 3.10-2 TIMING FOR GENERATING INIT#/CPURST#.............................62

FIGURE 5-1 BLOCK DIAGRAM FOR GENERATING CORE FREQUENCY.......78

FIGURE 8.1-1 SiS5595 INTERNAL POWER PLANES........................................198

FIGURE 8.5-1 DMA CYCLES..............................................................................204

FIGURE 8.5-2 THE AC TIMING DIAGRAM OF PCI TO ISA BUS CYCLES......... 206

FIGURE 8.5-3 MISCELLANEOUS TIMING.......................................................... 209

FIGURE 9.2-1 SiS5595 PACKAGE SPECIFICATION.......................................... 209

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SiS5595 PCI System I/O Chipset

Tables

TABLE 1.2-1 MULTI-FUNCTION PINS....................................................................5

TABLE 3.1-1 IRQS MAPPING IN SERIAL IRQ PERIODS ..................................... 14

TABLE 3.2-1 SLEEPING STATE AND CLOCK STATE ......................................... 17

TABLE 3.2-2 SLEEPING STATE AND POWER STATE.......................................17

TABLE 3.2-3 GPIOX RELATIONAL DATA TABLE................................................ 31

TABLE 3.2-4 RELOAD EVENTS FOR EACH TIMER............................................ 34

TABLE 3.2-5 WAKEUP EVENT FROM PMU........................................................35

TABLE 3.3-1 SMBUS INTERRUPRELATED TABLE ............................................. 36

TABLE 3.6-1 THE ACCESS OF STANDARD/EXTEND BANK AND APC

REGISTERS .....................................................................................42

TABLE 3.7-1 ADDRESS MAP OF THE APC CONTROL REGISTERS.................. 45

TABLE 3.9-1 8259 IRQS MAPPING....................................................................... 59

TABLE 7.8-1 LEGACY SUPPORT REGISTERS.................................................. 194

TABLE 7.8-2 EMULATED REGISTERS............................................................... 195

TABLE 8.2-1 MIN .AND MAX. VOLTAGE AND TEMPERATURE TABLE............ 199

TABLE 8.3-1 SiS5595 DC CHARACTERISTICS TABLE ..................................... 199

TABLE 8.4-1 RTC POWER CONSUMPTION TABLE..........................................202

TABLE 8.5-1 DMA CONTROLLER AC CHARACTERISTICS TABLE..................203

TABLE 8.5-2 PCI-TO-ISA CYCLES AC CHARACTERISTICS TABLE.................204

TABLE 8.5-3 MISC. AC CHARACTERISTICS TABLE.........................................206

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SiS5595 PCI System I/O Chipset

1 FEATURES

1.1 SiS5595 PCI SYSTEM I/O

§ Integrated PCI-to-ISA Bridge

− Translates PCI Bus Cycles into ISA Bus Cycles.

− Translates ISA Master or DMA Cycles into PCI Bus Cycles.

− Provides a Dword Post Buffer for PCI to ISA Memory cycles.

− Two 32 bit Prefetch/Post Buffers Enhance the DMA and ISA Master Performance.

− Fully Compliant to PCI 2.1.

§ Supports both Desktop and Mobile Advanced Power Management Logic

− Meets ACPI 1.0 Requirements.

− Supports Both ACPI and Legacy PMU.

− Supports Suspend to RAM.

− Supports Suspend to Hard Disk.

− Optionally Tri-state ISA bus in low power state.

− Supports Battery Management and LB/LLB/AC Indicator.

− Supports CPU's SMM Mode Interface.

− Supports CPU Stop Clock.

− Supports Power Button of ACPI.

− Supports three system timers and SMI# watchdog timer.

− Supports Automatic Power Control.

− Supports Modem Ring-in, RTC Alarm Wake up.

− Supports Thermal Detection.

− Supports GPIOs, and GPOs for External Devices Control.

− Supports Programmable Chip Select.

− Supports PCI Bus Power Management Interface Spec. 1.0 .

− Supports Pentium II Sleep State.

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SiS5595 PCI System I/O Chipset

§ Enhanced DMA Functions

− 8-, 16- bit DMA Data Transfer.

− Two 8237A Compatible DMA Controllers with Seven Independent Programmable

Channels.

− Provide the Readability of the two 8237 Associated Registers.

− Support Distributed DMA.

− Support PC/PCI DMA.

− Per DMA channel programmable in legacy, DDMA or PC/PCI DMA mode

operation.

§ Integrated Two 8259A Interrupt Controllers

− 14 Independently Programmable Channels for Level- or Edge-triggered Interrupts.

− Provide the Readability of the two 8259A Associated Registers.

− Support Serial IRQ.

− Support the Reroutability for the PCI Interrupts.

§ Three Programmable 16-bit Counters compatible with 8254

− System Timer Interrupt.

− Generate Refresh Request.

− Speaker Tone Output.

− Provide the Readability of the 8254 Associated Registers.

§ Integrated Keyboard Controller

− Hardwired Logic Provides Instant Response.

− Supports PS/2 Mouse Interface.

− Supports Keyboard Password Security or Hot Key Power On Function.

− Supports Hot Key "Sleep" Function.

− Programmable Enable and Disable for Keyboard Controller and PS/2 Mouse.

§ Integrated Real Time Clock(RTC) with 256B CMOS SRAM

− Supports ACPI Day of Month Alarm/Month Alarm.

− Supports various Power Up events, such as Button Up, Alarm Up, Ring Up,

GPIO5/PME0# Up, GPIO10/ PME1# Up, Password Security Up, and Hotkey Up.

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SiS5595 PCI System I/O Chipset

− Supports various Power Down Events, like Software Power-down, Button Power­down, and ACPI S3 Power-down.

− Supports Power Supply ’98.

− Provides RTC year 2000 solution.

§ Integrated Frequency Ratio Control Logic for Pentium II CPU

§ Universal Serial Bus Host Controller

− Open HCI Host Controller with Root Hub.

− Two USB Ports.

− Supports Legacy Devices.

− Supports Over Current Detection.

§ Integrated Hardware Monitor Logic

− Up to 5 Positive Voltage Monitoring Inputs.

− Two Fan Speed Monitoring Inputs.

− One Temperature Sensings.

− Supports thermister- or diode- temperature sensing for Pentium II CPU.

− Threshold Comparison of all Monitored Values.

§ Supports I2C Serial Bus/ SMBUS

§ Supports 2MB Flash ROM Interface

§ 208 pins PQFP Package

§ 5V CMOS Technology

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SiS5595 PCI System I/O Chipset

1.2 FUNCTIONAL BLOCK DIAGRAM

PCLK

PHOLD#

PHLDA#

SERR#

INT[A:D]#

AD[31:0]

C/BE[3:0]#

FRAME#

IRDY#

DEVSEL#

TRDY#
STOP#

GPIO0/PAR

GPIO17/SIRQ

PCIRST#

CPURST

INIT

A20M#

SMI#

STPCLK#

INTR

NMI

IGNE#

FERR#

GPIO3/CPU_STOP#/SLP#

BM_REQ#

EXTSMI#

GPCS0#

UCLK48M

GPIO7/OC0#/PPS

GPIO8/OC1#

UV0+

UV0-

UV1+

UV1-

KBVDD

KBDAT/IRQ1
GPIO2/KBCLK
PMDAT/IRQ12

GPIO1/PMCLK

GPCS1#/KLOCK#

PCI

INTERFACE

CPU

INTERFACE

ACPI/LEGACY

PMU

USB

INTERFACE

KBC

DATA

ACQUISITION

INTERFACE

RTC

ISA BUS

INTERFACE

DXP/VIN4
DXN
GPI[15:12]/

VIN[3:0]
GPIO4/FAN1
GPIO11/FAN2

GPIO9/THERM#/BTI/SMIALERT#

DDCCLK
DDCDAT

RTCVDD
RTCVSS
PWRGD
PSRSTB#
PWRBT#
RING
OSC32KHI/IRQ8#
OSC32KHO/RTCCS#
PS_ON#/RTCALE

GPIO5/PME0#/DUAL_ON#

GPO6/CKE_S/ACPILED
GPIO10/PME1#/ACPILED

SD[15:0]
SA[16:0]
LA[23:17]
SBHE#
IO16#
M16#
BALE
IORC#
IOWC#
MRDC#
MWTC#
SMRDC#
SMWTC#
BCLK
RFH#
ZWS#
GPIO16/IOCHK#

IOCHRDY
AEN
TC
DRQ[7:5,3:0]
DACK[7:5,3:0]#
IRQ[15:14,11:9,7:3]
SPKR
ROMKBCS#
CLK14M
PDMAREQ0#

PDMAREQ1#

Figure 1.2-1 Functional Block Diagram

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SiS5595 PCI System I/O Chipset

Table 1.2-1 Multi-Function Pins

GPIO0/PAR GPIO8/OC1# GPIO16/IOCHK#
GPIO1/PMCLK GPIO9/THERM#/

BTI/SMBALERT#
GPIO2/KBCLK GPIO10/PME1#/ACPILED GPCS1#/KLOCK#
GPIO3/CPU_STOP#/SLP# GPIO11/FAN2 OSC32KHI/IRQ8#
GPIO4/FAN1 GPI12/VIN0 OSC32KHO/RTCCS#
GPIO5/PME0#/DUAL_ON# GPI13/VIN1 PS_ON#/RTCALE
GPO6/CKE_S/ACPILED GPI14/VIN2 KBDAT/IRQ1
GPIO7/OC0#/PPS GPI15/VIN3 PMDAT/IRQ12
DXP/VIN4

GPIO17/SIRQ

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SiS5595 PCI System I/O Chipset

GPIO9/THERM#/BTI/SMBALERT#

2 PIN ASSIGNMENT (TOP VIEW)

2.1 SiS5595 PIN ASSIGNMENT (TOP VIEW)

SA13

SA14

DACK3#

SA15

DRQ3

PDMAREQ0#

OVSS

IORC#

IOWC#

SA16

IRQ15

SMRDC#

SMWTC#

IRQ14

SD0

IOCHRDY

SD5

SD2

AEN

SD1

ZWS#

SD4

SD3

SD7

DRQ2

SD6

PDMAGNT0#

EXTSMI#

GPIO3/CPU_STOP#/SLP#

BM_REQ#

PCIRST#

PHLDA#

GPIO8/OC1#

DVSS

GPIO7/OC0#/PPS

DVDD

UCLK48M

USBVDD

UV1-

UV1+

UV0-

UV0+

USBVSS

PHOLD#

AD31

AD30

AD29

OVSS

AD28

AD27

AD26

AD25

DACK1#

DRQ1
RFH#

SA12
SA11

BCLK

SA10

OVDD

DACK2#

DVSS

DVDD

BALE

IO16#

SBHE#

M16#

LA23
LA22
LA21
LA20
LA19

OVSS

LA18
LA17

DRQ0

DACK0#

MRDC#

DACK5#

MWTC#

DACK6#

DRQ5

SD10

DRQ6

SD11
SD12

DRQ7

DACK7#

SD13
SD14
SD15

156

155

157

160

SA9
SA8
SA7
SA6

SA4
SA5

TC
SA3
SA2

SA1
SA0

SD8
SD9

165

170

175

180

185

190

195

200

205

208

1

145

150

SiS5595

5

10

15

135

140

20

25

125

130

30

35

115

120

40

45

105

110

104

100

95

90

85

80

75

70

65

60

55

53

50

52

OVDD
AD24
C/BE3#
AD23
AD22
OVSS
AD21
AD20
AD19
AD18
AD17
AD16
IRDY#
C/BE2#
DVSS
DEVSEL#
DVDD
FRAME#
TRDY#
OVSS
STOP#
SERR#
C/BE1#
OVDD
AD15
AD14
AD13
AD12
C/BE0#
AD11
AD10
OVSS
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
OVSS
AD1
OVDD
AD0
INTD#
INTC#
PCLK
INTB#
INTA#
GPCS0#
GPIO17/SIRQ
GPIO0/PAR

INIT

IRQ9

IRQ7

IRQ6

IRQ5

GPIO16/IOCHK#

IRQ3

IRQ4

IRQ11

IRQ10

DXP/VIN4

DXN

AVDD

GPI15/VIN3

GPI14/VIN2

GPI13/VIN1

GPI12/VIN0

AVSS

PWRGD

RTCVSS

OSC32KHO/RTCCS#

RING

RTCVDD

PWRBT#

PSRSTB#

OSC32KHI/IRQ8#

PS_ON#/RTCALE

KBVDD

CLK14M

KBDAT/IRQ1

GPIO2/KBCLK

PMDAT/IRQ12

GPIO1/PMCLK

GPO6/CKE_S/ACPILED

GPIO10/PME1#/ACPILED

GPIO5/PME0#/DUAL_ON#

SPKR

ROMKBCS#

GPIO4/FAN1

GPIO11/FAN2

DDCDAT

DDCCLK

FERR#

STPCLK#

IGNE#

NMI

INTR

SMI#

A20M#

CPURST

GPCS1#/KLOCK#

Figure 2.1-1 pin assignment

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SiS5595 PCI System I/O Chipset

2.2 SiS5595 CHIP ALPHABETICAL PIN LIST

SIGNAL
NAME

A20M# 51
AD0 61
AD1 63
AD2 65
AD3 66
AD4 67
AD5 68
AD6 69
AD7 70
AD8 71
AD9 72
AD10 74
AD11 75
AD12 77
AD13 78
AD14 79
AD15 80
AD16 93
AD17 94
AD18 95
AD19 96
AD20 97
AD21 98
AD22 100
AD23 101
AD24 103
AD25 105
AD26 106
AD27 107
AD28 108
AD29 110
AD30 111
AD31 112
AEN 138
AVDD 12
BALE 176
BCLK 162
BM_REQ# 127
C/BE0# 76

SiS5595
PIN NO.

SIGNAL

NAME

C/BE1# 82
C/BE2# 91
C/BE3# 102
CLK14M 35
CPURST 50
DACK0# 192
DACK1# 157
DACK2# 169
DACK3# 154
DACK5# 194
DACK6# 198
DACK7# 205
DDCCLK 42
DDCDAT 41
DEVSEL# 89
DRQ0 191
DRQ1 158
DRQ2 132
DRQ3 152
DRQ5 199
DRQ6 201
DRQ7 204
DVDD 88
DVDD 121
DVDD 174
DVSS 17
DVSS 90
DVSS 123
DVSS 172
DXP/VIN4 10
DXN 11
EXTSMI# 129
FERR# 43
FRAME# 87
GPCS0# 55
GPI12/VIN0 16
GPI13/VIN1 15
GPI14/VIN2 14
GPI15/VIN3 13

SiS5595
PIN NO.

SIGNAL
NAME

GPIO0/PAR 53
GPIO1/PMCLK 32
GPIO2/KBCLK 31
GPIO3/CPU_STO

P#/SLP#
GPIO4/ FAN1 38
GPIO5/PME0#/

DUAL_ON#
GPIO7/OC0#/PPS 122
GPIO8/OC1# 124
GPIO9/THERM#/B

TI/SMBALERT#
GPIO10/PME1#/A

CPILED
GPIO11/FAN2 39
GPIO16/IOCHK# 1
GPIO17/SIRQ 54
GPO6/CKE_S/
ACPILED
IGNE# 46
INIT 45
INITA# 56
INITB# 57
INITC# 59
INITD# 60
INTR 48
IO16# 180
IOCHRDY 141
IORC# 149
IOWC# 148
IRDY# 92
IRQ3 6
IRQ4 7
IRQ5 5
IRQ6 4
IRQ7 3
IRQ9 2
IRQ10 9
IRQ11 8
IRQ14 143

SiS5595
PIN NO.

128

29

40

27

28

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SiS5595 PCI System I/O Chipset

SIGNAL
NAME

IRQ15 146
KBDAT/ IRQ1 33
KBVDD 30
KLOCK#/CPCS1# 52
LA17 190
LA18 189
LA19 187
LA20 186
LA21 185
LA22 184
LA23 183
M16# 182
MRDC# 193
MWTC# 195
NMI 47
OSC32KHI/IRQ8# 21
OSC32KHO/
RTCCS#
OVDD 62
OVDD 81
OVDD 104
OVDD 168
OVSS 64
OVSS 73
OVSS 85
OVSS 99
OVSS 109
OVSS 150
OVSS 188
PCIRST# 126
PCLK 58
PDMAGNT0# 130
PDMAREQ0# 151
PHLDA# 125
PHOLD# 113
PMDAT/ IRQ12 34
PS_ON#/
RTCALE
PSRSTB# 23
RFH# 159
RING 24
PWRBT# 26
PWRGD 18

SiS5595
PIN NO.

20

25

SIGNAL

NAME

ROMKBCS# 36

RTCVDD 22
RTCVSS 19
SA0 179
SA1 178
SA2 177
SA3 175
SA4 170
SA5 171
SA6 167
SA7 166
SA8 165
SA9 164
SA10 163
SA11 161
SA12 160
SA13 156
SA14 155
SA15 153
SA16 147
SBHE# 181
SD0 142
SD1 137
SD2 139
SD3 134
SD4 135
SD5 140
SD6 131
SD7 133
SD8 196
SD9 197
SD10 200
SD11 202
SD12 203
SD13 206
SD14 207
SD15 208
SERR# 83
SMI# 49
SMRDC# 145
SMWTC# 144
SPKR 37
STOP# 84

SiS5595
PIN NO.

SIGNAL
NAME

STPCLK# 44
TC 173
TRDY# 86
UCLK48M 120
USBVDD 119
USBVSS 114
UV0- 116
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SiS5595
PIN NO.

Preliminary V2.0 Oct.6, 1998 8 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

3 FUNCTIONAL DESCRIPTION

SiS5595 is a highly integrated system I/O that constitutes a high performance, rich featured,
yet glueless solution for both Pentium and Pentium II systems.

The SiS5595 PCI system I/O integrates the PCI-to-ISA bridge with the DDMA and PC/PCI
DMA, Serial IRQ capability, the ACPI/Legacy PMU, the Data Acquisition Interface, the
Universal Serial Bus host/hub interface, and the ISA bus interface, which contains the ISA
bus controller, the DMA controllers, the interrupt controllers, and the Timers. It also
integrates the Keyboard controller, and the Real Time Clock (RTC). The built-in USB
controller, which is fully compliant to OHCI (Open Host Controller Interface), provides two
USB ports capable of running full/low speed USB devices. The Data Acquisition Interface
offers the ability of monitoring and reporting the environmental condition of the PC. It could
monitor 5 positive analog voltage inputs, 2 Fan speed inputs, and one external temperature
inputs. It also integrates the automatic power control logic to control the power ON/OFF for
ATX power supply. In addition, SiS5595 also integrates the thermal detection and frequency
ratio control logic for Pentium II CPU.

3.1 PCI BUS INTERFACE

3.1.1 PCI TO ISA BUS BRIDGE

As a PCI slave device, the PCI-to-ISA Bridge responds to both I/O and memory transfers. It
always target-terminates after the first data phase for any bursting cycle.

The PCI-to-ISA Bridge is assigned as the subtractive decoder in the Bus 0 of the PCI/ISA
system by accepting all accesses not positively decoded by some other agents. In reality, it
only subtractively responds to low 64K I/O or low 16M memory accesses. It also positively
decodes BIOS memory space by asserting DEVSEL# signal on the medium timing. It is
optional to do positive or subtractive decode on I/O addresses for some internal registers.

As a PCI master device, the PCI master bridge on behalf of DMA devices or ISA Master
devices drives the AD bus, C/BE[3:0]# and PAR signals. When MEMR# or MEMW# is
asserted, the PCI-to-ISA bridge will generate FRAME#, and IRDY# to PCI bus if the targeted
memory is not on the ISA side. The valid address and command are driven during the
address phase, and PAR signal is asserted one clock after that phase. It always activates
FRAME# for 2 PCLKs because it does not conduct any bursting cycle.

The ISA address decoder is used to determine the destination of ISA master devices or DMA
devices. This decoder provides the following options as they are defined in registers 48h to
4Bh of PCI to ISA Bridge configuration space.

a. Memory: 0-512K
b. Memory: 512K-640K
c. Memory: 640K-768K (video buffer)
d. Memory: 768K-896K in eight 16K sections (Expansion ROM)
e. Memory: 896K-960K (lower BIOS area)

Preliminary V2.0 Nov. 2, 1998 9 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

f. Memory: 1M-XM-16M within which a hole can be opened. Access to the hole is not

forwarded to PCI bus.

g. Memory: >16M automatically forward to PCI.

Delayed transaction is a mechanism used when the target, like PCI-to-ISA bridge in SiS5595
on behalf of the ISA devices, cannot complete the transaction within the initial latency of 16
PCI clocks. To support delayed transaction function, the PCI-to-ISA bridge would latch all the
information required to complete the transaction and then terminate the master with a retry.
The PCI-to-ISA Bridge will then translate the request into ISA cycle to obtain the requested
data for a read transaction or complete the actual request if a write request. During this
period the original master would keep retrying the cycles while other PCI masters are also
allowed to use the bus that would normally be wasted holding the original master in wait
states. Eventually, the original master would get the latched data for read transaction, or
complete the cycle for the write transaction when the PCI-to-ISA Bridge completes the ISA
cycles.

• DMA/ISA Master Cycles
ISA devices or DMA controller embedded in the PCI-to-ISA Bridge of SiS5595 may become

ISA master and initiate cycles to access PCI bus. It is quite often that the ISA master may
request for ISA bus while there is a delayed transaction undergoing. As a result, an
arbitration rule is adopted in the PCI-to-ISA Bridge to prevent conflict on the ISA bus. In this
section, the actions of an ISA master cycle will be described first, and next outline the
arbitration rules. For convenience, the progress of a delayed transaction cycle will be divided
into three phases: DT_PH_1, DT_PH_2 and DT_PH_3.

PCI BUS

ISA BUS

T1

T2

DT_PH_1 DT_PH_2 DT_PH_3 DT_PH_1 DT_PH_2 DT_PH_3 DT_PH_1

: BUS BUSY PERIOD

T1: A new delayed transaction is accepted
T2: The delayed transaction is completed on ISA bus
T3: Original master completes the delayed transaction cycle

T3 T1

T3

T2

Figure 3.1-1 PCI ISA Delay Transaction

DT_PH_1: This is the period when there is no pending delayed transaction in progress

Preliminary V2.0 Nov. 2, 1998 10 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

DT_PH_2: This is the period when the ISA cycle corresponding to the delayed transaction is

undergoing on ISA bus.

DT_PH_3: From the end of ISA cycle up to the original PCI master successfully retries and

completes the whole delayed transaction.
Note: the delayed transaction is said to be pending during DT_PH_2 and DT_PH_3.
Traditionally, ISA (DMA) masters request ISA bus by asserting their corresponding DRQs to

DMA controller embedded in the PCI-to-ISA bridge. The PCI-to-ISA bridge will then generate
PHOLD# to system arbiter to request for PCI bus. The PHOLD# will be asserted as long as
DRQ is asserted by the ISA master. In response to PHOLD#, the system arbiter grants PCI
bus to PCI-to-ISA bridge by asserting PHLDA#. The PCI-to-ISA bridge, upon receiving
PHLDA#, will first check if ISA bus is busy or idle. If busy, it will defer the assertion of DACK#
until ISA bus returns to idle. If idle, it will assert the corresponding DACK# immediately to
inform ISA master to start. When ISA master receives DACK#, it can then start its cycles
transferring data to or from PCI (ISA) bus. When ISA master finishes its cycles, it de-asserts
DRQ and then PHOLD# will also be de-asserted immediately. The system arbiter, in
response to the desertion of PHOLD#, will immediately de-assert PHLDA#. This completes
the whole sequence of ISA master cycles.

• Delayed Transaction and ISA Master Arbitration Rule

1) When ISA master issues DREQ and there is no pending delayed transaction, this is the
normal case that no arbitration is needed and the PCI-to-ISA bridge behaves exactly as
that stated above.

2) When ISA master issues DREQ and there is currently a delayed transaction pending,
the PCI-to-ISA bridge will disregard the pending delayed transaction and immediately
generate PHOLD# to request for PCI bus.

3) When the system arbiter grants PCI bus to ISA master by asserting PHLDA#, and the
delayed transaction is in DT_PH_2, i.e., the ISA bus is busy, the PCI-to-ISA bridge
should defer the assertion of DACK# until DT_PH_3 is entered. Otherwise, ISA master
will start its cycles as soon as DACK# is asserted and may result in ISA bus conflict.

4) If PHLDA# is asserted when the pending delayed transaction is already in DT_PH_3,
i.e., the ISA bus has returned to idle, the PCI-to-ISA bridge can assert DACK#
immediately and hence ISA master may start its cycles even when the delayed
transaction is not yet completed on PCI bus.

5) During the period that ISA master is active and delayed transaction is pending in
DT_PH_3, the original PCI master that initiated the delayed transaction will temporarily
stop retrying on the PCI bus because PCI bus is now owned by ISA master.

6) After the ISA master finishes its data transfers, the original PCI master should
eventually re-gain PCI bus and retry successfully.

3.1.2 DISTRIBUTED DMA (DDMA)

Distributed DMA allows the individual DMA channels to be separated into different physical
devices on the PCI bus. In distributed DMA, the DMA Master contains the addresses that
were occupied by the traditional ISA DMA Controller (8237). This device will respond to any
system read or write to the traditional ISA DMA address locations so the software will

Preliminary V2.0 Nov. 2, 1998 11 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

continue to think it is communicating with a standard DMA controller. The SiS5595 is the
DMA Master and the protocol is as follows:

1) When the CPU Bridge attempts to read/write a legacy DMA register, a PCI I/O cycle will
be initiated on the PCI bus with a legacy DMA address. The SiS5595 will take control of
this cycle by driving DEVSEL# active, asserting PHOLD# and issuing a PCI retry to
terminate this cycle.

2) When granted the PCI bus, the SiS5595 will run up to 4 PCI I/O read/write cycles. The
specific I/O addresses for each legacy DMA address are remappable. The purpose of
these read/writes is to return/send the individual channel read/write information. DMA
Slave devices must only respond to the slave address assigned to them and not any
legacy DMA address.

3) At the end of the last read/write the SiS5595 will set an internal flag indicating the
completion and will de-assert PHOLD# and wait for the retried PCI I/O read/write from
the CPU bridge.

The PCI I/O read/write will be retried. If it was a read, the SiS5595 will return the data. If it
was a write, the SiS5595 will simply terminate the cycle. Then the SiS5595 will reset the
internal flag.

3.1.3 PC/PCI DMA

SiS5595B supports one PC/PCI PDMAREQ0#/PDMAGNT0# pairs. PCI devices plugged in
the PCI slot may initiate PC/PCI DMA transfer cycles through the PDMAREQ0#/
PDMAGNT0# pair. For DMA operation, three types of transfer cycles are supported:
Memory-to-I/O, I/O-to-Memory and Verify. SiS5595B also supports ISA master operation
through PC/PCI DMA channels, on which a PCI device may request the PCI bus through the
PDMAREQ0#/PDMAGNT0# pair. Each of the seven DMA channels can be individually
programmed to be in Legacy, DDMA or PC/PCI DMA mode. Care must be taken to ensure
only one of the three operation modes is enabled for a particular DMA channel. The legacy
8237 compatible registers will be used to control the operation of PC/PCI DMA, for software
backward compatibility.

3.1.4 SERIAL IRQ (SIRQ)

The Serial IRQ provides a mechanism for communicating IRQ status between ISA legacy
components, PCI components, and PCI system controllers. A serial interface is specified that
provides a means for transferring IRQ and/or other information from one system component
to a system host controller. A transfer, called a serial IRQ cycle, consists of three frame
types: one Start Frame, several IRQ/Data Frames, and one Stop Frame. This protocol uses
the PCI clock as its clock source and conforms to the PCI bus electrical specification.

3.1.4.1 Timing Diagrams For Serial IRQ Cycle

Preliminary V2.0 Nov. 2, 1998 12 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

oftheStopFrame.

SL

or
H

STARTFRAME

H R T S R T S R T S R T

IRQ1 FRAME

SMI#FR AME

PCICLK
SIRQ#

DriveSource

1

START

Host Contr oller None

None

SM I#

H=Hos tCon trol SL=Sl aveControl R=Recovery T=Turn-around S=Sample

1. Start Framepulsecan be 4-8 clocks wide.

Figure 3.1-2 Start Frame Timing with Source Sampled a Low Pulse on SMI#

IRQ14 FRAME IRQ15 FRAME

S R T S R T S R T

PCICLK

SIRQ#

Drive

None

H=Host Control R=Recovery T =Turn-around S=Sample I=Idle

1. Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mod e.

2. There may be none, one or more Idel states during the Stop Frame .

3. The next SerialIRQ cycle's Start Frame pulse may o r ma y not start immediatelyafter the turn-around clock

IRQ15 None Host Controller

IOCHK#FRAME

2

I

STOP FRAME

H

STO P

R T

1

NEXT CYCLE

START

3

Figure 3.1-3 Stop Frame Timing with Host using 17 SIRQ# Sampling Period

3.1.4.2 Serial IRQ Cycle Control

There are two modes of operations for the serial IRQ start frame.

1) Quiet (Active) Mode: Any device may initiate a Start Frame by driving SIRQ# low for
one clock, while SIRQ# is idle. After driving low one clock the SIRQ# must immediately
be tri-stated without any time driving high. A Start Frame may not be initiated while the
SIRQ# is Active. The SIRQ# is Idle between Stop and Start Frames. This mode of
operation allows the SIRQ# to be Idle when there are no IRQ/Data transitions which
should be most of the time.

Once a Start Frame has been initiated, the SiS5595 will take over driving the SIRQ#
low in the next clock and will continue driving the SIRQ# low for a programmable period
of three to seven clocks more. This makes a total low pulse width of four to eight clocks.
Finally, SiS5595 will drive the SIRQ# back high for one clock, then tri-state.

Any serial IRQ device which detects any transition on an SIRQ# line for which it is
responsible must initiate a Start Frame in order to update the SiS5595 unless the

Preliminary V2.0 Nov. 2, 1998 13 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

SIRQ# is already in a serial IRQ cycle and the IRQ/Data transition can be delivered in
the serial IRQ cycle.

2) Continuous (Idle) Mode: Only the SiS5595 can initiate a Start Frame to update SIRQ#
line information. All other serial IRQ agents become passive and may not initiate a Start
Frame. SIRQ# will be driven low for four to eight clocks by the SiS5595. There are two
functions in this mode. It can be used to stop or idle the SIRQ# or the SiS5595 can
operate SIRQ# in a continuous mode by initiating a Start Frame at the end of every
Stop Frame. A serial IRQ mode transition can only occur during the Stop Frame. Upon
reset, the Serial IRQ bus is defaulted to continuous mode, therefore only the SiS5595
can initiate the first Start Frame. Slave must continuously sample the Stop Frames
pulse width to determine the next serial IRQ cycle's mode.

3.1.4.3 IRQ/Data Frame

Once a Start Frame has been initiated, all serial IRQ devices must detect the rising edge of
the Start pulse and start counting IRQ/Data Frames from there. There are three clock
phases for each IRQ/Data Frame: Sample Phase, Recovery Phase, and Turn-around Phase.
During the Sample phase the serial IRQ device must drive the SIRQ# low, if and only if, its
last detected IRQ/Data value was low. If its detected IRQ/Data value is high, SIRQ# must be
left tri-stated. During the Recovery phase, a serial IRQ device will drive SIRQ# back high if it
has driven the SIRQ# low in the previous clock. During the Turn-around phase all serial IRQ
devices must be tri-stated. All serial IRQ devices will drive SIRQ# low at the appropriate
sample point regardless of which device initiated the sample activity, if its associated
IRQ/Data line is low.

The Sample phase for each IRQ/Data follows the low to high transition of the Start Frame
pulse by a number of clocks equal to the IRQ/Data Frame times three, minus one. (e.g., the
IRQ5 sample clock is the sixth IRQ/Data frame, (6x3)-1=17th clock after the rising edge of
the Start Pulse).

Table 3.1-1 IRQs Mapping in Serial IRQ Periods

SERIAL IRQ SAMPLING PERIODS

IRQ/Data Frame Signal Sampled # of clocks past Start

1 Reserved 2
2 IRQ1 5
3 SMI# 8
4 IRQ3 11
5 IRQ4 14
6 IRQ5 17
7 IRQ6 20
8 IRQ7 23

9 IRQ8# 26
10 IRQ9 29
11 IRQ10 32
12 IRQ11 35
13 IRQ12 38

Preliminary V2.0 Nov. 2, 1998 14 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

SERIAL IRQ SAMPLING PERIODS

IRQ/Data Frame Signal Sampled # of clocks past Start

14 IRQ13 41
15 IRQ14 44
16 IRQ15 47
17 IOCHCK# 50
18 INTA# 53
19 INTB# 56
20 INTC# 59
21 INTD# 62

32:22 Unassigned 95

At the end of each Sample phase, the SiS5595 will sample the state of the SIRQ# line and
replicate the status on the original IRQ/Data line at the input to the 8259s Interrupt
Controller.

3.1.4.4 Stop Cycle Control

Once all IRQ/Data frames have completed, the SiS5595 will terminate SIRQ# activity by
driving Stop cycle. Only the SiS5595 can initiate the stop frame. A Stop Frame is indicated
by the SiS5595 driving SIRQ# low for two clocks (Quiet Mode) or 3 clocks (Continuous
Mode), then back high for one clock. In the Quiet mode, any serial IRQ device may initiate a
Start frame in the third clock or more after the rising edge of the Stop frame pulse. In the
Continuous mode, only the SiS5595 may initiate a Start frame in the third clock or more after
the rising edge of the Stop frame pulse.

3.2 ACPI /LEGACY PMU

3.2.1 ADVANCED CONFIGURATION AND POWER INTERFACE (ACPI)

Advanced Configuration and Power Interface (ACPI) is PC 97/98 specification. ACPI extends
the portability for different platforms by moving the power management function into the OS.
ACPI also releases the restriction of ROM BIOS capacity on the complexity of the advanced
power management functions. The power management events of ACPI are initiated by the
assertion of System Control Interrupt (SCI). System uses SCI to send ACPI-relevant
notifications to the host OS, and then OS executes the specific service sub-routines
according to which enable bit and status bit is set.

The ACPI architecture in SiS5595 consists of the Fixed Features logic, Generic Features
logic, Legacy Features logic, and the configuration registers to ensure fluent communication
with the ACPI-compliant OS. The Fixed Features meet ACPI SPEC 1.0 requirement. The
SCI/SMI# generating logic in ACPI senses external environmental changes or requests and
interrupts, the OS to take some action. The wakeup logic will sequence the system from the
S1/S2 to G0/S0 working state. Besides, sequencing the system from S3/S5 to G0/S0 can
only be achieved through the power up events processed in the RTC/APC module.

3.2.1.1 Fixed Features

Preliminary V2.0 Nov. 2, 1998 15 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

SLP_TYPx=10

SLP_TYPx=10

C0

S2

SLP_TYPx=(001-

From ACPI specification, SiS5595 supports the four global system states (G0-G3), and the
traditional Legacy system state as shown in the Figure 3.2-1 Global System State Diagram.
The ACPI-compliant OS assumes the responsibility of sequencing the platform between
these various global states. The ACPI-compliant OS is invoked by the shareable interrupt to
which SCI is routed. The re-routability of SCI is through the programming of register 6Ah of
the PCI to ISA configuration space. Transition of Legacy to/from ACPI is through issuing
ACPI activate/deactivate command to the SMI# handler by doing I/O write command to the
SMI# Command Port (35h).

Power
Failure

Mech Off

(SCI_EN=0)

(G3)

Legacy

Boot

ACPI
Boot

(SCI_EN=1)

Legacy

SCI_EN=1

Working

SCI_EN=0

Legacy

Boot

(SCI_EN=0)

S0

(G0)

SLP_EN=1

PWRBTN_OR

and

or

Wake
Event

ACPI
Boot

(SCI_EN=1)

S4/S5

Soft-Off

(G2)

and

SLP_EN=1

and

SLP_EN=1

S1

Sleeping

(G1)

Software

Suspend to Disk

S3

Figure 3.2-1 Global System State Diagram

• Sleeping State
ACPI state machine would stay at G0 working state as the normal operating state in which

different devices are dynamically transiting between the respective power states, and
processors are dynamically transiting between their respective states (C0, C1, C2, C3). In
reality, the system G1 State consists of S1, S2, S3, and S4 State hierarchically in the sense
of sleeping states. The O.S. can initiate the sleeping state transition by programming the
SLP_TYPx field with the appropriate value and then setting the SLP_ENx bit high. Table

3.2-1 Sleeping State and Clock State summarizes the recommended arrangement of CLK;
Table 3.2-2 Sleeping State and Power State describes the recommended arrangement of
the power state for the major components at the three sleeping states. In S2 state, the CLK
to the CPU can be further stopped in SiS cored based Pentium system. However, all the
clocks in S2 State must keep running in SiS cored based Pentium II system due to the
nature of the clock scheme used. It is optional to put memory subsystem into the self-refresh

Preliminary V2.0 Nov. 2, 1998 16 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

mode while the system enters S2 State. However, it is a MUST for a system to place the
memory subsystem into self-refresh mode when it enters S3 State.

Table 3.2-1 Sleeping State and Clock State

SYSTEM

STATE

S1
S2

S3

(*1) Only 5595/32KHz is alive. Wake-up logic in SiS5595 chipset family normally relates to
RTC module.

SYSTEM

STATE

S1
S2
S3

S4/S5

The following statement details the running steps of S1, S2 and S3 State:

• S1 state

Assert STPCLK# ;
Assert STPCLK# ;
Use GPIO3 to stop CPUCLK ;
Use GPIO3 as SLP# to put Pentium II into SLEEP state
Disable all the clocks except that for the wake-up logic (*1)

Table 3.2-2 Sleeping State and Power State

Keep all the power supplied
Can turn off the power for ISA devices
Can turn off all the power except for the SDRAM and the wake-up logic
Turn off all the power except for the wake-up logic.

CLOCK STATE

POWER STATE

Entering S1 state is achieved by setting SLP_EN bit HIGH and SLP_TPY=001. All system
power is still alive in this state. A set of wake-up Events can be enabled, before entering S1,
to wake up the system back to G0 State.

• S2 state
The North Bridge in the following context may stand for SiS530 used in Pentium system or

SiS5600/SiS620 used in Pentium II system, respectively.

1) Disable PCI system Arbiter & AGP arbiter

2) Program into S2 mode with the consequence that STPCLK# is asserted.

3) North Bridge keeps processing whatever is requested until CPU generates a stop grant
(stpgnt) cycle. The North Bridge then forwards the stpgnt cycle via PCI special cycle to the
PCI bus. While intercepting the stpgnt special cycle on the PCI bus, 5595 will optionally first
mask the ISA commands (IORC#, IOWC#, MRDC#, and MWTC#), float all the ISA signals,
and then assert GPIO3 in 32 PCICLKs later. GPIO3 can be used to disable the CPUCLK in

Preliminary V2.0 Nov. 2, 1998 17 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

Pentium system. However, it is recommended that GPIO3 is connected to SLP# of Pentium
II processor to place it into very low power SLEEP STATE in which the processor maintains
its context, and PLL, and has stopped all internal clocks.

4) When the system is awaken, the WAK_STS is set, re-enable the ISA bus, unmask the ISA
commands, and finally de-assert the STPCLK# in about 4ms. A period of 4ms is reserved to
allow the CPU/PLL stabilization. A set of wake up events illustrated in Figure 3.2-2 Wake up
events in S1 / S2 are supported to wake up the system in the S2 state.

Enabling "Mask the ISA command" and "Float the ISA signals" upon waking up from S2
State can be achieved by setting bit 3 of ACPI Reg. 13h. No ISA cycles should be initiated
before RSTDRV is de-asserted. Setting bit 2 of ACPI reg. 13h can select the GPIO3 multi­function pin to function as CPU_STOP#/SLP#.

USB IRQ / SMI#

EXTSMI#

Ring Logic

DAM IRQ / SMI#

SMBus

GPIOxx

IRQ8#

PWRBT#

(bit)Source

(30)USB
(29)GP_TMR
(28)EXTSMI#
(26)Hotkey
(25)Ring
(24)DAM
(23)SMBus
(17:7,5:0)GPIO

(bit)Source

(10)RTC
(08)PWRBTN#

GPE Status
ACPI 14h

PM1 Status
ACPI 00h

PM1 Enable
ACPI 02h

GPE Enable
ACPI 18h

Wake up Event Set in S1 /S2

IRQWK_EN
ACPI 18h.31

IRQ Wakeup evet
from PMU Block

IRQWK_STS
ACPI 18h.31

Figure 3.2-2 Wake up events in S1 / S2

Note : DAM means Data Acquisition Module.

enter S2

STPCLK#

stpgnt

maskisa#
floatisa#

GPIO3

wak_sts

RSTDRV

1~2PCLKs

32PCLKs

tri-state

Figure 3.2-3 5595's Timing Diagram in S2 State

1~2PCLKs

1~2PCLKs

Wake up event

4ms

Clear by BIOS

Note : stpgnt, maskisa, floatisa, and wak_sts are internal signals.

Preliminary V2.0 Nov. 2, 1998 18 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

32~64u

enter S3

STPCLK#

stpgnt

CKE_S
(DUAL_ON#)

PS_ON#

128~160u

Power up request

Boot Process

clear APC reg 04h.7

PCIRST

CKE_N

CKE

Set 6Ch.[5:4] of Host to PCI config. space

Set 6Ch.4 of Host to PCI config. space

Figure 3.2-4 North Bridge/5595's Timing Diagram in S3 State

Note : “stpgnt” is an internal signal. CKE_N and CKE are driven by SiS North Bridge.

• S3 state (Suspend To RAM)
Disable PCI system Arbiter & AGP arbiter.

Similar to the S2 state, STPCLK# is asserted as a result of transiting the system into S3
state by writing 011(binary digit) to SLP_TYP field of register 04h in the ACPI IO space.

Having intercepted the Stop_Grant special cycle on the PCI bus, the SiS5595 will enable
and drive CKE_S low in 32us to 64 us, and then negate PS_ON# in another 128us to 160us
later.

Figure 3.2-4 North Bridge/5595's Timing Diagram in S3 State is the timing

diagram showing the sequence happening on the SiS5595 while entering/exiting S3 State.
To provide a fast wake-up latency, it is highly recommended to place the system into the

Suspend to RAM (STR) state in S3 state. Placing the system into STR is normally achieved
through keeping the system image in the main memory (not in the hard disk). Except the
memory subsystem, and the wake-up logic, the power to the rest of the M/B components is
removed. Moreover, the memory subsystem is put into the low power state. For today's
mainstream memory like EDO or SDRAM, placing it into low power state can be performed
by programming it for self-refresh mode.

Per the SDRAM specification, it is required to keep CKE low as long as it is maintained in
self-refresh mode. There are two classes of CKE signals generated in SiS chipset. One is
CKE_N from the North Bridge, and the other is CKE_S from SiS5595. For a system which
does not support Suspend to RAM (STR), CKE can be simply connected to a pull high
resistor. To support Suspend to RAM function, an external LVT 245 is employed to generate
6 CKE signal lines to support 3 DIMM configuration. Please refer to the SiS5600/
SiS620/SiS5595 design guide or the associated application circuit for more detail. The

Preliminary V2.0 Nov. 2, 1998 19 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

following details the protocol of CKE_N, and CKE_S while entering/exiting the self-refresh
mode.

When Battery is first plugged in, CKE_S is put into HI_Z State. In fact, CKE line is driven
high by external pull up resistor at this moment. Note that the pull-up resistor should be
connected to the power supplying the SDRAM. CKE_N is also put into HI-Z State upon
power up every time. Upon power up or wake-up, the BIOS should read the STR_STS bit
stored in RTC APC 06h bit 5 to determine if it needs to alter the CKE_N, and CKE_S state.

If it is, the BIOS should program the North Bridge to drive CKE_N low, put the CKE_S into
high impedance state, and then drive the CKE_N high to exit SDRAM from self-refresh
mode. If STR_STS bit is not set, leave CKE_N and CKE_S in the high impedance state, and
have the external pull-up resistor driving CKE high.

On the other hand, CKE_N and CKE_S perform in the following way while entering into S3
State.

1) The North Bridge enables CKE_N low after the completion of emptying the write buffer.

2) The SiS5595 drives CKE_S low in 32 us later after having intercepted the Stop_Grant
special cycle on the PCI bus.

3) CKE_N stops driving CKE line in 128us to 160us later as a result of the negation of
PS_ON# to turn off the power. Starting from this point, SDRAM and the wake-up logic is
powered by the AUX3V (or AUX5V), or Vdual from Power Supply '98. The CKE_S keeps the
CKE line low from this moment. CKE_S can also be connected to DUAL_ON# of the power
supply '98.

The following example to represent routine recommended for regulating the CKE_S and
CKE_N in the S3 State for SiS5595 working with SiS530 or SiS5600/SiS620.

{Power up or resuming sequence for SiS530 or SiS5600/SiS620 core based
system}

...

If (STR_STS)
/* Drive CKE_N low with the following two steps */

Set bit 4 of reg. 6Ch in the Host to PCI config. space ;
Set bit 5 of reg. 6Ch in the Host to PCI config. space ;

/* Place CKE_S into high impedance state */

Clear bit 7 of APC Reg 04h in the SiS5595;

/* Drive CKE_N high */

Clear bit 4 of reg. 6Ch in the Host to PCI configuration space ;

If (!STR_STS)
If (the system would like to support STR)
/* Drive CKE_N high */

Set bit 5 of reg. 6Ch in the Host to PCI config. Space ;

Preliminary V2.0 Nov. 2, 1998 20 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

Else Leave CKE_N, and CKE_S as they are ;

While in the G1 State, a set of Wake_Up Events can be enabled to transit the system state
back to G0. Please refer to “ RTC APC ” illustrating the supported wake up events in S3
State.

• G2---S4/S5(Suspend To Disk/Soft Off)
The G2 soft-off state is an O.S. initiated system shutdown. The State can be initiated by

programming the SLP_TYPx field with S5 value and setting the SLP_ENx bit high. Also, a
hardware event, which is driven by pressing the power button for more than four seconds
can transit the system to the G2 state while it is in the G0 state. This hardware event is
called a Power Button Over-ride, and is mainly provided to turn off a hung system in case.
Putting system in the G2 state will de-assert PS_ON# eventually from hardware point of
view.

In the G2 State, only the RTC power is alive. While in the G2 state, the SiS5595 could sense
the following seven power up events to transit the system to the Legacy system state by
asserting the PS_ON#. They are RTC Alarm On event, Power Button Up (PWRBT#) event,
Ring Up event, PME0# event, PME1# event, Hotkey Match event, and Password Match
event. Please see the APC portion of the RTC module for more details.

• Processor Power State

• STPCLK# Throttling (C0)

SiS5595 supports the four power states in the G0/S0 working state. While in the C0 state, it
provides programmable throttling function to place the processor executing at a designated
performance level relative to its maxima performance. This can be achieved by programming
the Throttling Duty Cycle Control field (ACPI: 0Ch[3:1]) with desired value, and setting
Throttling Function Enable bit (ACPI: 0Ch[4]) to HIGH.

• CPU Power State Level 1 (C1)
The C1 State is supported through the HLT instruction. For instance, the execution of a

HALT instruction will cause CPU to automatically enter the Auto HALT Power down state
where Icc of the processor will be -20% of the Icc in the Normal State. In this state, the CPU
will transit to the Normal state upon the occurrence of INTR, NMI, SMI#, RESET, or INIT.
CPU would not recognize AHOLD, BOFF#, and EADS# for cache invalidation or write-back.
That is, the system is no longer able to allow bus master snooping, or memory access. As
such, C2 low power state provides an alternative not to block bus master streaming while the
CPU is put into the low power state.

Preliminary V2.0 Nov. 2, 1998 21 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

duty cycle value

000
001

010

011

100
101
110
111

%100 performance

%12.5 performance

%25 performance

STPCLK#

%37.5 performance

%50 performance

%67.5 performance

%75 performance

%87.5 performance

Figure 3.2-5 STPCLK# Throttling & Performance

• CPU Power State Level 2(C2)
In the C2 power state, SiS5595 places the processor into the low power state by keeping

STPCLK# low as long as no interrupt requests occur. Entering C2 state is through reading
P_LVL2 register (ACPI Register 10h) as it is defined in the ACPI specification. Exiting C2 is
effective when any interrupt is asserted. Register 68h, and 69h in the PMU configuration
space defines which interrupt requests among the IRQ15-3, 1-0, and NMI are enabled to exit
C2. Beside, the PMU configuration space register 50h bit 24 should be enabled.

• CPU Power State Level 3(C3)
As a more rigid or flexible alternative to the handling of bus master in the CPU low power

state, SiS5595 supports the C3 power state by also keeping STPCLK# low, which can be
entered by reading P_LVL3 register (ACPI Register 11h). Optionally, GPIO3 used as SLP#
can be asserted to place the Pentium II processor into SLEEP State. The main difference
between C3 and C2 state is that the bus masters are prevented from writing into the memory
in the C3 state. This is, prior to entering the C3 state, done by setting the ARB_DIS bit (ACPI
Register 12h[0]) to HIGH which disables the system arbiter. Upon a bus master requesting
an access, the CPU will awaken from C3 state if the BM_RLD bit (ACPI Register 05h[1]) is
set, and re-enable bus master accesses by clearing the ARB_DIS to enable the system
arbiter. If the BM_RLD bit is not set, the C3 Power State is not exited upon bus master
requests. From hardware point of view, in the C3 state, to serve bus master requests, it is
needed to transit the CPU back to C0 state by de-asserting STPCLK# while it is not needed
for C2 state. Any interrupt will also bring the processor out of C3 power state. The BM_STS
is set whenever any bus master request (REQ#) is asserted. Figure 3.2-6 Processor Power
State Diagram illustrates the processor power state diagrams supported by SiS5595.

Preliminary V2.0 Nov. 2, 1998 22 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

INTR, NMI,

Over Heat

Thermal

STPCLK#

not Over Heat

HLT

C1

Processor

support

Figure 3.2-6 Processor Power State Diagram

• System Timer Event (IRQ0)

%100

Performance

SMI#,

RESET,

INIT

Throttling Enable =1
performance < %100

C0

Throttling Enable =0

P_LVL2

C2

Chipset

support

G0

Working

`

Interrupt

Chipset Support

Throttling

Interrupt

or

Bus Master

Request

P_LVL3

C3
Chipset
support

In Legacy mode, SiS5595 supports special IRQ0 function. When in C2 or C3, the IRQ0
(system timer) can de-assert STPCLK# (&SLP#) 125us and does not exit C2 or C3. This
function is enabled by setting ACPI Register 13h bit 0, and you should disable IRQ0 wake up
event in PMU configuration space register 68-69h. Legacy PMU handler can use 125us to
update system time or do something else. After 125us, STPCLK# is asserted again.

Preliminary V2.0 Nov. 2, 1998 23 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

STPCLK# of S1 / S2

IRQ0 125us

Enable(13h.0)

IRQ0

IRQ0 125us

Conuter

TH_EN(0Ch.4)

125us CLK

interrupt
interrupt

Bus Master

GPIO9/THRM#

GPIO9/THRM#(28h.9=1)

Thermal Throttling Enable(2Ah.6=1)

C0 Throttling

Logic

C2 Logic

C3 Logic

Thermal

Throttling

Logic

STPCLK#

Figure 3.2-7 STPCLK# Source

• Thermal STPCLK# Throttling
SiS5595 can support thermal detection by selecting GPIO9 as the THERM# pin. A 1ms de-

bouncer is used to sense the status of THERM#. When the logic of the THERM# matches
the programming active level, the STPCLK# is throttled if the Thermal Throttling Enable (bit 6
of ACPI register 2Ah) is set. The throttling will be stopped if the THERM# goes back to the
inactive state as a result of the system temperature may be cooled down. Note that it is not
necessary to set the Throttling Function Enable bit (ACPI IO 0Ch bit 4) for throttling the
STPCLK# in response to the THERM# request. If THERM# is asserted, the system will enter
the throttling mode directly (whose duty cycle is defined by ACPI I/O 2Ah, bit 4~2) or
generate an SCI/SMI# by the thermal throttling function/GPIO9 selection bit (ACPI: 28h[9]).
Please refer to Figure 3.2-8 Thermal Detection Logic.

Preliminary V2.0 Nov. 2, 1998 24 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

GPIO9/THRM#

Input Pin

Status(1Ch.9)

I/O Selection(20h.9=1)

Input Mode

Polarity

Selection(24h.9)

Output Pin Status(1Ch)

No Used

Trigger Mode Logic

(Edge/Toggle trigger)

1ms CLK PCI CLK

Enable(18h.9)

Status(14h.9)

GPIO9 Event

GPIO9/THRM#(28h.9)

Figure 3.2-8 Thermal Detection Logic

• Power Button
This button is a user interface control instead of the traditional power supplier switch. It can

be used to cycle the system between the G0 and G1 state, as one of the power
management events. Besides, the power button provides user a mechanism to force the
system to enter the G2 State (Soft-Off) when the system has hung. This is called as power
button over-ride.

Normally, the SiS5595 generates a power button event in the form of SCI, or SMI# in the G0
working state while detecting the Press-and-Release sequence on the PWRBT# pin.
However, by setting bit 4 of ACPI register 13 to 1, the power button event can be generated
simply upon that the button is pressed. Upon the instant that power button is pressed to the
instant that the power button override event is recognized, the specific routine can be
invoked, and executed (due to SMI#, or SCI) to do any housekeeping before the power is
removed.

A 1ms de-bouncer associated with the power button is used to recognize and respond to the
active low logic presented on the pin. If the PWRBT# is pressed for more than 4 seconds,
the SiS5595 will turn off the system power by de-asserting the PS_ON#.

If the PWRBT# is released within 4 seconds, only the PWRBTN_STS bit (ACPI: 00h[8]) will
be set. If the PWRBTN_EN bit (ACPI: 02h[8]) is also enabled, an SMI# or SCI will be raised.
There is a power button over-ride enable bit in ACPI Register 13h bit 5, which is enabled by
default. Although the ACPI SPEC 1.0 no longer requires the support of this power button
over-ride enable bit, SiS5595 keeps the bit in other location to allow the application software
to disable the function just in case.

• Power Management Timer
The SiS5595 supports a 24-bit power management timer, based on a 3.579545MHz clock,

which provides an accurate time value used by system software to measure and profile
system idleness (along with other tasks) while the system is in the working (G0) state. To
allow software to extend the number of bits in the timer, the power management timer

Preliminary V2.0 Nov. 2, 1998 25 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

generates an interrupt when the last bit of the timer changes (from 0 to 1 or 1 to 0). The PM
Timer can be accessed directly by the ACPI driver or software. The TMR_STS status bit is
set any time the last bit of the timer bit 23 goes from HIGH to LOW or LOW to HIGH. If the
TMR_EN bit is set, the TMR_STS being set will generate an ACPI event (SCI/SMI#). The
timer is reset when system wake-up from sleeping states (S1, S2) or hardware reset.

• Real Time Clock Alarm
It is required to extend the current RTC definition of a 24-hour alarm to a one-month-alarm in

ACPI specification. To extend the alarm bytes, SiS5595 supports both the Day of the Month
Alarm, and Month Alarm function. The Day of the Month Alarm byte, and Month Alarm byte
are located in the 7Eh, and 7Fh of the Standard Bank of the RTC CMOS RAM, respectively.
The RTC_STS bit will be set once IRQ8# is asserted from the internal RTC module. The
application software can set any specific time to generate an SCI or SMI# if the system is in
the working state, or a wake-up event if the system is in the sleeping state S1, or S2.

• SCI /SMI# Generation
When SCI_EN=1, most of the ACPI events can generate SCI; when SCI_EN=0 (Legacy

mode) they can generate SMI#. Normally, ACPI events can generate SCI or SMI# only when
the system is in the G0 working state. However, an option is reserved to generate SMI# in
response to the ACPI events while the system is in one of the sleeping states. Figure 3.2-9
SCI / SMI# Events Overview summarizes all the supported ACPI events in SiS5595 to
generate SCI/SMI#. System designer should take care that some events only generate SMI#
or wake up system. For example, Hotkey can only generate SCI/SMI#, IRQWK can only
generate wake-up events in S1 or S2 state, and SIRQ can only generate SMI#.

Preliminary V2.0 Nov. 2, 1998 26 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

(bit)Source

(15)IRQ15
(14)IRQ14
(13)IRQ13
(12)IRQ12
(11)IRQ11
(10)IRQ10
(09)IRQ9
(08)IRQ8
(07)IRQ7
(06)IRQ6
(05)IRQ5
(04)IRQ4
(03)IRQ3
(02)NMI
(01)IRQ1
(00)IRQ0

Ring Logic

BM_REQ

Write ACPI 04h.2
GBL_RLS =1

USB IRQ / SMI#

DAM IRQ / SMI#

GPCS0#
GPCS1#

INIT

ExtSMI#

PMU_SMI#

DAM SMI#

USB SMI#

SMBus SMI#

GPIOxx

EXTSMI#

Ring Logic

SMBus
GPIOxx

IRQ8#

PWRBT#

IRQWK Enable
PMU 68~69h

(bit)Wake up source

(31)Ch0 IDE D0
(30)Ch1 IDE D0
(29)Keyboard Port
(28)Serial Port 1
(27)Serial Port 2
(26)Parallel Port
(25)DMA,USB MA Req.
(24)IRQ0,1,3~15,NMI
(23)Ring
(22)10-bit I/O
(21)16-bit I/O
(20)Mem A-B Seg.
(19)Mem C0000-C7FFF
(18)VGA I/O 3B0-3DFh
(17)Linear Frame Buffer
(16)Microsoft Sound
(15)Sound Blaster Port
(14)MIDI Port
(13)Game Port
(12)GPCS0#
(11)GPCS1#
(10)INIT
(09)EXTSMI#
(08)PCI,IDE or AGP Master
(07)AGP cycle
(06)Floppy Port
(05)Ch1 IDE D1
(04)Ch1 IDE D1

(bit)SMI# Source

(7)DAM_SMI#
(6)USB_SMI#
(4)SMI# CMD
(3)SMBus SMI#
(2)Perodic SMI#
(1)Wake-up SMI#
(0)Software SMI#

(bit)SMI# Source

(17:7,5:1)GPIO SMI#

GPIO SMI# Enable
ACPI 2Ch

SIRQ SMI# Enable
ACPI 18h.27

(bit)SMI# Source

(27)Serial IRQ SMI#

(bit)Source

(8)USB
(11)GP_TMR
(0)EXTSMI#
(6)Hotkey
(1)Ring
(4)DAM
(10)SMBus
(others)GPIO

(bit)Source

(10)RTC
(08)PWRBTN#
(00)PM_TMR

Wake up 0 Enable
PMU 50~53h

Legacy Status
ACPI 30h

GPIO Status
ACPI 14h

SIRQ SMI# Status
ACPI 14h.27

GPE Status
ACPI 14h

PM1 Status
ACPI 00h

PM1 Enable
ACPI 02h

Wake up 1 Enable
PMU 54~57h

Legacy Enable
ACPI 31h

GPE Enable
ACPI 18h

PMU 79h
PMU 7Ah

PMU 7Bh

Ring Logic

GPCS0#
GPCS1#

ExtSMI#

(bit)SMI# source

(31)Standby Tmr 0
(30)Standby Tmr 1
(29)Standby Timr 2
(28)Wake up 0
(27)Wake up 1
(26)Reserved
(25)Ch0 IDE D0
(24)Ch1 IDE D0
(23)Keyboard Port
(22)Serial Port 1
(21)Serial Port 2
(20)Parallel Ports
(19)Ring
(18)10-bit I/O
(17)16-bit I/O
(16)Mem A-B Seg.
(15)Mem C0000-C7FFF
(14)VGA I/O 3B0 3DF
(13)Linear Frame Buffer
(12)Microsoft Sound
(11)Sound Blaster Port
(10)MIDI port
(09)Game Port
(08)GPCS0#
(07)GPCS1#
(06)ExtSMI#
(05)Floppy Port
(04)Ch0 IDE D1
(03)Ch1 IDE D1
(02)APM(Sofware)

*Note 1

SCI Enable
PMU 80~83h

SMI# Status
PMU 64~67h

SMI# Enable
PMU 60~63h

SMI_EN

ACPI 31h.5

SMI_STS

ACPI 30h.5

PMU Block

IRQ Wakeup event

to ACPI 14h.31

PMU_SCI

(to ACPI Block)

PMU_SMI#

ACPI Block

SMI#

SCI

GBL_EN

Write ACPI 13h.1
BIOS_RLS =1

PMU_SCI

(from PMU Block)

ACPI 02h.5

GBL_STS
ACPI 00h.5

SCI_EN

ACPI 04h.0

Figure 3.2-9 SCI / SMI# Events Overview

Note 1: The “line” means OR logic.

Preliminary V2.0 Nov. 2, 1998 27 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

3.2.1.2 Generic Features

Generic Features in SiS5595 offers a variety of additional events such as USB event,
GP_TMR event, EXT_SMI# event, Hotkey event, Ring event, Data Acquisition Module event,
and GPIO events. These events are all categorized as ACPI events. Hence, they can either
generate SCI or SMI# in the working state or serve as the wake-up events in the sleeping
state.

• Wake up IRQ (IRQ_WK) Event
IRQ_WK event is one of GPE Bank event. A status bit located in ACPI register 14h bit 31 is

set when IRQ_WK is asserted if its enable bit locating in ACPI Reg.18h bit 31 is set. Note
that IRQ_WK only generates wake-up event in S1 or S2 State. It cannot generate SCI or
SMI#. To correctly function, additional registers are to be programmed:

1) Specify IRQ Enable in PMU Configuration Space 68~69h,

2) Mask other wake-up source in PMU Configuration in PMU Configuration Space
50~53h.

Besides, the IRQ_WK (internal signal) is also used to exit CPU Power State from C2 or C3.

• General Purpose Timer (GP_TMR) Event
General-purpose timer is an 8 bits down counter. Its resolution is 1us or 1 min. General-

purpose timer can be programmed as Suspend timer or BIOS Timer (ACPI: 1Ch[7]). Loading
values into the counter values initiates the counting immediately. If there is not any reload
events (PMU Configuration Register: 40h-43h) detected during counting down period, the
timer will expire with the result of generating a power management event (SCI, SMI#, or
wake up event). Suspend timer is functionally similar to System Standby Timer. However,
expiration of Suspend Timer can assert SCI or SMI# but expiration of System Standby Timer
can only assert SMI#.

start(write 1Fh)

Select Clock(2Ah.8)

GP_TMR

Status(14h.29)

GP_TMR

Enable(18h.29)

GP_TMR Event

PMU Stop events

(in PMU space 40h)

GPIOs Stop events

(in ACPI space 2Eh)

Select suspend

timer(2Ah.7=1)

SCI_EN=0

8bit down counter

8 bits

GP_TMR[0-7](1Fh)

Figure 3.2-10 General Purpose Timer Logic

Preliminary V2.0 Nov. 2, 1998 28 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

• HotKey Event
When internal keyboard controller is enabled, the HOTKY_STS (ACPI: 14h[6]) will be set if

the"CTRL+ALT+Backspace" is recognized. Then SCI/SMI# is generated if HOTKY_EN
(ACPI: 18h[6]) is set.

• Ring Event
There are two de-bouncers associated with the RING to allow two possible modes of

activation. The default mode supports 150ms detection on the RING signal while the other
mode supports frequency between 14Hz to 70Hz, depending on the value of ACPI Register
2Ah bit 5.

For ring detection, the RI_STS bit (ACPI 14h bit 1) will be set if the ring signal is sensed
asserted. If the RI_EN bit (ACPI 18h bit 1) is also enabled, the power management event will
be generated.

Ring function can only used with internal RTC.

• GPIOx Events
SiS5595 provides eighteen pins to support general purpose I/O function. GPO6 is output

only. GPI[12:15] are input only. The rest (GPIO[5:0], GPIO[11:7], GPIO[17:16]) are bi­directional. Beside, GPIO5, GPO6 GPIO10 are in RTC power plant, so that the control
register is in RTC APC space. The input/output attribute of these pins can be programmed
through setting or resetting the corresponding bits of the GPE I/O Selection register in ACPI
20h. By default, all the GPIO pins are input. While in the input mode, the active logic level
can be programmed through GPE Polarity Selection registers in ACPI 24h. The default
active level is low. Some GPIOs have trigger mode selection, including GPIO1, GPIO11~15.
User can set rising/falling edge trigger by GPE Control in ACPI space 24h and 2Ah. Please
refer Figure 3.2-11 GPIO Logic.

GPIOx Pin

Input Pin

Status(1Ch)

I/O

Selection(20h)

(Output Enable)

Polarity

Selection(24h)

Output Pin Status(1Ch)

Edge/Toggle

trigger logic

Trigger Mode selection(2Ah)

Status(14h)

Enable(18h)

GPIO Wake-up
Event

Figure 3.2-11 GPIO Logic

Preliminary V2.0 Nov. 2, 1998 29 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

When the corresponding enable and status bits are set, SCI or SMI# or Wake-up event will
be generated. Writing a 1 to the status bit can clear the bit. In addition, the input level of each
GPIO pins can be directly read back by reading the corresponding bit in the GPIO Pin Status
register (in ACPI 1Ch). While in the output mode, the logic of each GPIO pin can be
controlled by writing the desired value to the corresponding bit in the GPIO Pin Status
registers to control the peripheral device power, for instance.

• GPIOx Logic
The SiS5595 supports a variety of General-Purpose Input/ Output pins that are also MUXed

with other signals as they are shown below with a couple of properties (Table 3.2-3):

Preliminary V2.0 Nov. 2, 1998 30 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

Table 3.2-3 GPIOx Relational Data Table

PIN

NMAE

GPIO0 PAR PAR follow PCI VDD Level
GPIO1 PMCLK GPIO1 IN KBVDD Toggle/Edge

GPIO2 KBCLK GPIO2 IN KBVDD Level

GPIO3 CPU_STP#/

MUX

FUNCTION

DEFAULT

FUNCTIO

DEFAULT

I/O

POWER

PLANE

MODE(*1)

N

GPIO3 IN VDD Level

GPI

FUNC

SELECT

REG.

ACPI 28.1 ACPI 20.0 ACPI 24.0 ACPI 1C.0
SIO CFG

60.3
SIO CFG

60.3
ACPI 28.3 ACPI 20.3 ACPI 24.3 ACPI 1C.3

IO

SELECT

GPI MODE

SELECT

GPO

LEVEL

REG.

ACPI 20.1 ACPI

24.1,2A.1

ACPI 20.2 ACPI 24.2 ACPI 1C.2

ACPI 1C.1

SLP#

GPIO4 FAN1 GPIO4 IN VDD Level

GPIO5 PME0#/

GPIO5 IN RTCVDD Level

DUAL_ON#

GPO6 CKE_S/

CKE_S OUTPUT RTCVDD Level

ACPILED

GPIO7 OC0#/PPS GPIO7 IN VDD Level

GPIO8 OC1# GPIO8 IN VDD Level
GPIO9 THERM#/

GPIO9 IN VDD Level

None ACPI 20.4

ACPI 28.4
APC 03.3
APC 04.5
APC 04.2
APC 07.6
ACPI

28.6~7
ACPI 28.8 ACPI 20.8 ACPI 24.8 ACPI 1C.8
ACPI 28.9 ACPI 20.9 ACPI 24.9 ACPI 1C.9

APC 04.4 ACPI 24.5 ACPI 1C.5

None ACPI 24.6 ACPI 1C.6

ACPI 20.7 ACPI 24.7(*2) ACPI 1C.7

ACPI 24.4 ACPI 1C.4

/SMBALERT#/
BTI

GPIO10 ACPILED/

PME1#

GPIO11 FAN2 GPIO11 IN VDD Toggle/Edge

GPI12 VIN0 GPI12 IN VDD Toggle/Edge

GPI13 VIN1 GPI13 IN VDD Toggle/Edge

GPI14 VIN2 GPI14 IN VDD Toggle/Edge

GPI15 VIN3 GPI15 IN VDD Toggle/Edge

GPIO16 IOCHK# GPIO16 IN VDD Level

GPIO17 SIRQ GPIO17 IN VDD Level

GPIO10 IN RTCVDD Level

APC 04.1
APC 07.7
None ACPI 20.11 ACPI 24.11,

None None ACPI

None None ACPI

None None ACPI

None None ACPI

ACPI 28.12
ACPI 28.13
ACPI 28.5 ACPI 20.17 ACPI 24.17 ACPI 1C.17

APC 04.3 ACPI 24.10 ACPI 1C.10

ACPI 1C.11

2A.11

ACPI 1C.12

24.12,2A.12
ACPI 1C.13

24.13,2A.13
ACPI 1C.14

24.14,2A.14
ACPI 1C.15

24.15,2A.15

ACPI 20.16 ACPI 24.16 ACPI 1C.16

*1 : When GPIO is configured as the INPUT "Toggle" mode, the "Polarity (GPI Mode)" bit in ACPI Reg. 24[1&:0] is ignored.
*2: GPIO7’s Polarity, while configured in output mode, can be defined by programming ACPI Reg24[7]. This function is special in USB Application.
*3: The details can be referred in ACPI & APC SPEC of 5595.

Preliminary V2.0 Nov. 2, 1998 31 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

Since these signals are multiplexed with other signals, the BIOS need to program the
associated bit to select the usage first. Then, the input/output modes for these pins are
further determined if they are selected as GPIO function. While the GPIOx pins are inputs for
the SiS5595, GPI [15:12], GPIO11, and GPIO1 can be set as either edge (falling or rising)
triggered or toggle mode by programming bit [15:11,1] of register 2Ah respectively. The
rising or falling edge depends on the programming of bit [15:11,1] of reg. 24h respectively.
Except these pins, the rest of the GPIO pins are sensitive to level trigger only. The high or
low sensitive mode depends on the programming of bit [17:0] of register 24h respectively.
The default active level is low. While in the input mode, the input level of each GPIO pin can
be directly read back by reading the corresponding bit in the GPIO Pin Status Register
Located in ACPI Register 1Ch. Besides, while in the output mode, the logic of each GPIO pin
can be controlled by writing the desired value to the corresponding bit in the GPIO Pin Status
registers. When configured in the input mode, activation of any of the GPIO[17:7,5:0] pin can
set the corresponding status bit in GPE_STS reg. with a consequence of generating a Power
Management Event (SCI, SMI#, or wake-up event) if the corresponding enable bit of
GPE_EN reg. is set.

For GPIO5, GPO6, and GPIO10, the following rules are supposed to be followed specifically:

1) If GPIO5 and GPIO10 are not adopted, the two pins can not be left open. One external
pull-up or pull-down resistor is required. While GPO6 is not adopted, this pin can be left
open.

2) The three pins are put in high impedance state upon the battery is plugged. The logic is
retained unless it is programmed to serve as other functions. If they are designed as
GPIO function, they can be controllable by appropriate programming, while power is on.
While the system power is down and these pins are programmed to be output mode,
they are rendered to output low state. As a summary of these GPIO pins working at the
GPIO mode, we have to:

− Select them working in GPIO function.

− Select them functioning in the input/output mode.

− Drive output high/or low depending on application.

Note that the bits control the functionality of these multifunction pins, and their input/output
mode are stored in the APC registers. Their logic values are retained as long as the RTC
power exists. For instance, if DUAL_ON#/GPIO5/PME0# is selected to function as GPIO
with input mode, GPIO5 logic will be controlled by setting bit5 of Register 24h in the ACPI I/O
space while the system power is on. While the system power is down, GPIO5 is enforced
high no mater what value has been programmed before. Later when the system power is on
again, GPIO5 stays at output mode with logic controlled by bit 5 of ACPI Register 24h, which
by default is high. For more detail information, please refer to S3 State Related Signals in the
RTC module.

• GPIOx Stop and Reload Timers Events
GPIO[17:16, 11:7, 5:1], GPI[15:12] events also can be used to reload PMU standby timer

and stop General Purpose Timer in ACPI. Application software can specify which GPIO
events are able to reload or stop timers (PMU and ACPI) in ACPI registers 2E~2Fh. For
reloading PMU standby timers, bit 3 of 40h, 44h, 48h registers should enable for each timer
in PMU block.

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SiS5595 PCI System I/O Chipset

3.2.1.3 Legacy Features

• Legacy SMI# Events
Legacy SMI# include DAM SMI#, USB SMI#, Periodic SMI#, Wake up SMI# from S1 /S2,

Software SMI#, Serial IRQ SMI#, and GPIOx SMI#. All information are presented in Figure

3.2-9 SCI / SMI# Events Overview

• SMI# Command
ACPI register 35h is a SMI# command port. A SMI# will be generated if the APCI register

31h, bit 4 (SMICMD_EN) is enabled and an I/O write to SMI command port is detected. The
SMI# handeler can check the SMI command port to determine which action should be taken.

• Periodic SMI# Event
Periodic SMI# can generate SMI# every 16 sec if the PERSMI_EN (ACPI 31h bit 2) is set.

This allows the SMI# handler to periodically give warning to the user for delivering the low
battery message, for instance.

3.2.2 POWER MANAGEMENT UNIT

Basically, the legacy PMU provides three main functions as follows:

3.2.2.1 System Activity Monitoring

The system activity monitor watches, within a specified monitoring period, at the system
events to decide when and to which green state the system will transit into. SiS5595
provides three independent system activity monitors to fulfill the requirement of flexible, and
wide range of today's Green PC application.

Basically, the system activity monitor consists of a system standby timer specifying the
"Monitor -Period", and an Event Recognizer to detect the enabled "Reload Events". Counting
down the timer until expiration mechanizes the "Monitor Period". However, the timer is
reloaded with its initial count, and re-counted down once any of the enabled Reloaded
Events is detected. If the specified Monitor Period is elapsed (certainly without any reload
event detected), the timer is expired with the result of generating SMI# to invoke the SMI#
routine to do any preferred action, such as turning off the screen, transiting the system into
throttling state or sleeping state by throttling the STPCLK# or keeping the STPCLK#
asserted, respectively.

Each Standby Timer is 8-bit wide with 14.318MHz as the Clock source, and provides 4 levels
of granularity, namely 17.8us, 4.58ms, 1.17us, and 5min. Register 79h, 7Ah, and 7Bh of the
PMU configuration space defines the initial count for the system standby timer 0, 1, and 2,
respectively. Bit[7:6], Bit[5:4], and Bit[3:2] of the PMU register 7Ch defines the granularity for
the system standby timer 0, 1, and 2, respectively. Table 3.2-4 Reload Events for Each
Timer summarizes the Reload Events that the Event Recognizers in SiS5595 can support.
There are three independent Event Recognizers provided, and their Reload Events can be
defined by programming PMU Register 40h-43h, 44h-47h, and 48h-4Bh, respectively.

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SiS5595 PCI System I/O Chipset

Table 3.2-4 Reload Events for Each Timer

TIMER RELOAD EVENT

System Standby
Timer 0 (PMU)

System Standby
Timer 1 (PMU)
System Standby
Timer 2 (PMU)

Defined on PMU Configuration Register 40h~43h
Hard Disk Primary Channel Drive 0/1: 1F0h~1F7h, 3F6h, Bus

master IDE port,
Hard Disk Secondary Channel Drive 0/1 : 170h~177h, 376h, Bus

Master IDE port,
Keyboard Port : 60h, 64h
Serial Port 1 : 3E8h~3Efh, 3F8h~3FFh
Serial Port 2 : 2E8h~2Efh, 2F8h~2FFh
Parallel Port :278h~27Fh, 378h~37Fh, 3BCh~3BEh
IRQ[15:3,1:0], NMI (Please refer to Register 68h~69h, 6Ah~6Bh,

6Ch~6Dh)
RING IN
Master request from USB, ISA Master or DMA cycle
Programmable 10 bit I/O Port (Please refer to Register5Ch~5Dh)
Programmable 16 bit I/O Port (Please refer to Register5Eh~5Fh)
Memory Address A0000h~BFFFFh
Memory Address C0000h~C7FFFh
VGA I/O Port 3B0h~3DFh
Linear Frame Buffer Memory Address (Please refer to Register

4Eh~4Fh)
Microsoft Sound System Port, one of the 530h~537h, 604h~60Bh,

E80h~E87h, F40h~F47h (Please refer to Register 4Ch~4Dh)
Sound Blaster Port, one of the (220h~22Fh, 230h~233h),

(240h~24Fh, 250h~253h), (260h~26Fh, 270h~273h), (280h~28Fh,
290h~293h)

MIDI Port, one of the 300h~333h, 310h~313h, 320h~323h,
330h~333h

Game Port 200h~207h, 388h~38Bh
GPCS0# (Please refer to Register 70h~73h)
GPCS1# (Please refer to Register 74h~77h, 78h)
INIT
EXTSMI#
Master request from 530 or 5600/620 (BM_REQ#)
AGP cycle from 530 or 5600/620 (BM_REQ#)
GPI[17, 15:7, 5:1]
Defined on PMU Configuration Register 44h~47h
The reload event is same as System Standby Timer 0
Defined on PMU Configuration register 48h~4Bh
The reload event is same as System Standby Timer 0

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SiS5595 PCI System I/O Chipset

Upon power up, the three standby timers are frozen which means they keep reloading the
initial count from their associated system timer register (default 00h). Setting "System
Standby Timer X SMI# Enable (bit 31, 30, and 29 of PMU Register 60h-63h) will de-freeze
the system standby timer 0, 1, and 2, respectively. Upon expiration, the corresponding
System Standby Timer X SMI# Request Status Bit is set, and the SMI# is generated. Note
that the standby timer stays at "reloading" status upon expiration.

The SMI# Request Status allows the SMI# routine to identify which SMI# source is coming.
Bit31, 30, and 29 of Register PMU 64h-67h correspond to the SMI# Request Status Bit for
the system standby timer 0, 1, and 2, respectively. Writing a logic 1 to the SMI# Request Bit
clears the status bit, and enables the standby timer count down again if its corresponding
SMI# Enable bit is not cleared. It is recommended to disable the SMI# Enable bit before
programming the initial count to make a clean start, meaning that the standby timer really
counts down starting from the initial count. Before the timer is expired, it can be reloaded if
any of the enabled reload events is identified, and then counts down again.

3.2.2.2 Wake Up Event Recognizers

Two independent Wake Up Event Recognizers are provided to allow the system designers to
flexibly meet the Green PC application. The main mission of the WUER (Wake Up Event
Recognizers) is to generate SMI# upon detecting the wake up events, if the corresponding
SMI# Enable bit is set.

Table 3.2-5 Wakeup Event from PMU

TIMER RELOAD EVENT

WAKEUP 0
(PMU)

WAKEUP 1
(PMU)

To summarize the supported Wake UP Event Set, namely WakeUp0, and WakeUp1 which
can be defined by programming the wake up event control registers locating on 50h-53h and
54h-57h of PMU configuration space, respectively. Bit 28, and 27 of the SMI# Enable
Register enables/disables the generation of SMI# while wake up event is recognized. The
WUER is designed to be quite independent on the system state (Sleep, or Throttling state).
The wake up event can be recognized, and thus SMI# be generated as long as its
corresponding enable bit in the wake event control register is set.

3.2.2.3 SMI# Generation Logic

SiS5595 PMU allows a versatile event that could give rise to the generation of SMI#. Two
sets of registers, namely SMI# Enable Registers, and SMI# Status Register relate to the
SMI# generating logic. The SMI# Enable register locating on Register 60h to 63h enables
the generation of SMI# upon that any of the enabled events is recognized. SMI# Request
Status register, locating on Register 64h to 67h reflects the event(s) producing the SMI#.

Defined on PMU Configuration Register 50h~53h
The wakeup event is same as System Standby Timer 0 except GPI

[17, 15:7, 5:1].
Defined on PMU Configuration Register 54h~57h
The wakeup event is same as System Standby Timer 0 except GPI

[17, 15:7, 5:1].

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SiS5595 PCI System I/O Chipset

3.3 SMBUS FUNCTIONAL DESCRIPTIONS

The System Management Bus (SMBus) is a subset of the Phillips I2C protocol. It is a two­wire interface for system to obtain chips' information, to indicate device model or part
number, and so on. It also can be applied to control devices such as system
suspend/wakeup, return device status or extend I/O for control purposes.

The SMBus host controller contains a Host Master and a Host Slave. The slave address may
contain an alias address. The host master and slave are fully independent, which conveys
that the host master can communicate with the host slave via the SMBUS protocol.
SiS5595B also supports SMBALERT# signal for slave devices to assert request. The
SMBALERT# pin is multiplexed with GPIO9 and BTI.

Access the SMBus register can be achieved by issuing an I/O write to ACPI offset 38H with
an INDEX, then followed by a I/O read or write to APCI offset 39h with Data.

The SMBus Interrupt Request can be routed to any IRQ or SMI#/SCI.

Table 3.3-1 SMBus Interrupt Table

INTERRUPT TYPE ASSOCIATED REGISTER

IRQ SIO.7E.7 : Data Acquisition Module and SMBus IRQ Mapping First

Enable
SIO.7E.5 : SMBus IRQ Mapping Second Enable
SIO.7E.3~0 : IRQ Routing table

SCI/SMI# APCI.14.23 : SMB_STS

APCI.18.23 : SMB_EN

SMI# APCI.30.3 : SMBSMI_STS

APCI.31.3 : SMBSMI_EN

3.3.1 SMBUS HOST MASTER INTERFACE

SiS5595B SMBus Host Master supports full SMBus protocol, including Quick command,
Send/Receive Byte, Read/Write Byte/Word, Read/Write Block, and Process Call. The
SiS5595B supports Read/Write Block command by an 8-byte buffer instead of 32-byte. For
block transfer size larger than 8 bytes, software manipulation is required. Once the eight
bytes block data have been transferred, the Sub-Block Request Status is employed to tell
service routine some data not processed yet. For the maximun of 32 bytes block data
transfer, four SMBus Interrupts will be raised by 5595 to complete the transfer.

When a Host transfer is initiated, the HOST_BUSY status bit will be set. The software is not
allowed to start a new command protocol till the HOST_BUSY reset to 0. The currently
HOST Master transfer cycle can be stopped by writting a ‘1’ to SMB_Kill bit. When a ‘1’ is
written to SMB_Kill bit, all status bit for host master and host slave will be reset. After
HOST_BUSY status bit becomes zero, the software is allowed to initiate a new transfer.

3.3.2 SMBUS HOST SLAVE INTERFACE

The Host has a Reserved Address in 0001000xb (x is R/W bit for command protocol) and an
Alias Address defined in SMB_Alias (SMBus Reg.13h). An idividual enable and status bit is
implemented for both address decoder. If a modified Write Word has been received by Host

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SiS5595 PCI System I/O Chipset

Slave with the Slave Address hit the Reserved Address or Alias Address, a SMBus Interrupt
will be raised. The device address, high data byte and low data byte are stored in SMBus
register 10h ~ 12h. Once the status bit HIT_HAA or HIT_HRA is set to ‘1’, the Host Slave is
unable to receive other modified Write Command until this status bit is reset.

3.4 USB INTERFACE

The SiS USB Host Controller is developed to support the USB bus as the Host Controller
with built-in Root Hub and 2 USB ports. The SiS USB Host Controller is implemented based
on the OpenHCI, the Open Host Controller Interface Specification for USB Release 1.0.

To support the applications and drivers under non-USB aware environments (such as DOS
environment), the SiS USB Host Controller implemented hardware to support the emulation
of a PS/2 keyboard and mouse by their USB equivalents (to the USB keyboard and USB
mouse). This emulation support is done by a set of registers that are controlled by code
running in SMM. The hardware implementation is based on OpenHCI Legacy Support
Interface Specification Release Version 1.01.

The SiS USB Host Controller provides the following major features:

− Provides USB Host Controller function to meet the Universal Serial Bus Specification
version 1.0, with full compatibility to the Open Host Controller Interface Specification for
USB Release 1.0

− Provides Legacy Support function based on OpenHCI Legacy Support Interface
Specification Release Version 1.01.

− Built-in Root Hub, with two USB Ports integrated.

− Implement circuit and control for Overcurrent Protection on the USB ports.

The following figure illustrates the USB System Block Diagram.

Preliminary V2.0 Nov. 2, 1998 37 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

USB System Block Diagram

(10-16-95)

CPU

Host Bus

Chipset

Chip set Core

PCI Bus

USB Host
Controller

Bridge/Transceiver

USB Device USB Hub1

USB Root Hub

USB

USB Host Controller

Figure 3.4-1 USB System Block Diagram

Memory

3.5 DATA ACQUISITION MODULE (DAM)

3.5.1 GENERAL DESCRIPTION

The Data Acquisition Module provides PC system hardware environment monitoring
including power supply voltages and cooling fan rotational speed. In addition, up to eight
external temperature sensors (such as LM75 device) can be deployed on the motherboard
with their outputs connected together through the BTI line into the SiS5595 to optionally
generate SMI# or IRQ. The most typical application will be putting one temperature sensor
chip or one thermistor under the CPU to monitor the ambient temperature of CPU.

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SiS5595 PCI System I/O Chipset

The Data Acquisition Module internally contains an Analog-to-Digital Converter (ADC) to
continuously transform analog signals from power supply voltages or temperature sensor
into 8-bit digital binary numbers. The rotational speed of fans can be calculated by counting
the cycle time of digital pulses from tachometer output based on an internally generated

22.5KHz clock. For every input sources to be monitored, the actual readings which have
been calculated or transformed will be compared with those upper and lower limits as
programmed in their associated registers. Upon a limit being exceeded, a SMI# or IRQ can
be optionally generated to inform the operating software to take proper steps to protect the
system from critical failure.

AD BUS

FAN1
FAN2

VIN0
VIN1
VIN2
VIN3

Index Address Reg.

Data Register

Fan Speed

Counter

8-Bit

Analog

To

Digital

Converter

(ADC)

DXP/VIN4

Temperature

Sensor

Limit

Registers

and

Comparators

BTI#

Interrupt

and
SMI#
Mask

Registers

SMI#

IRQ

Figure 3.5-1 Data Acquisition Module Block Diagram

3.5.2 POWER SUPPLY VOLTAGE MONITORING

The SiS5595 Data Acquisition Module supports up to five positive voltage inputs monitoring.
Analog inputs from power supply voltages, in term, will be converted into 8-bit unsigned
binary numbers by the internal Analog-to-Digital Converter (ADC) with a resolution of 16mV.
The resulting measurable voltage range is therefore from 0V to 4.096V. For voltages higher
than 4.096V, an external voltage attenuator circuit consisting of two properly selected
resistors can be used to scale down the voltage into the measurable range. Typically, the
four voltages to be monitored in a PC system are +12V, +5V, +3.3V and +2.5V respectively.
The +12V and +5V require external attenuators. The SiS5595 application notes contain the
recommended values of the resistors for the attenuators.

3.5.3 FAN SPEED MONITORING

The fan inputs are from fans equipped with tachometer pin, which carries continuous digital
pulses, indicating its current rotational speed. The longer the pulse’s cycle time, the slower
the fan rotates. The tachometer output requires a pull-up resistor connected to +5V. The
SiS5595 Data Acquisition Module supports two fan inputs monitoring. The typical application
will be connecting one to CPU fan and the other one to the case fan.

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SiS5595 PCI System I/O Chipset

The cycle time of the pulses from the tachometer output is measured by a counter counting
up at 22.5KHz clock. The reading of counter can be derived from the following formula. At
the nominal speed, a reading of 153 is expected.

Count = 22500 * 60 / RPM * Divisor

Where:
RPM is the fan’s nominal rotations per minute
Divisor is the normalized factor programmed in the fan divisor register in order to get a

reading of 153 at nominal speed for every RPM. It should be:

8800RPM : 1
4400RPM : 2
2200RPM : 4
1100RPM : 8

If the speed of fan decreases, the reading should go up until the maximum reading of 255 is
reached. This may indicate that the fan speed is very slow or has already stopped. There is
no upper limit for the fan speed; only lower limit can be programmed. Once the lower limit is
exceeded, a SMI# or IRQ can be generated to inform the operating software to take proper
steps such as throttling CPU activities by asserting the STPCLK#.

3.5.4 THE ROUND-ROBIN SAMPLING CYCLE

Once the monitoring process is started by setting a 1 to the Start bit at Configuration register,
the Data Acquisition Module will start sampling the inputs from each sources in a round-robin
manner according to the following order:

(1) Reserved (2) VIN0 (3) VIN1 (4) VIN2 (5) VIN3 (6) DXP/VIN4 (7) FAN1 (8) FAN2
A complete round-robin cycle will be completed with the rate of approximately 8/7second,

and the switch time for the eight input sources is evenly distributed within one cycle, i.e., 1/7
second. This gives the ADC enough time to provide a stable value before switching to the
next input. The readings for each input sources will be updated approximately once every
8/7 second and can be read from these offset registers.

OFFSET REGISTERS DESCRIPTION

20h/60h VIN0 reading
21h/61h VIN1 reading
22h/62h VIN2 reading
23h/63h VIN3 reading
24h/64h DXP/VIN4 reading
27h/67h Reserved
28h/68h Fan1 reading
29h/69h Fan2 reading

The Analog-to-Digital Converter can be calibrated through PCI-ISA configuration Registers
7Ch~7Dh. Users are advised NOT to program these calibration registers.

Preliminary V2.0 Nov. 2, 1998 40 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

3.5.5 INTERFACE REGISTER BLOCK

The Data Acquisition Module internal registers can be accessed through Interface Register
Block located in I/O address space, with its base address relocatable anywhere within the
low 64K I/O space by programming PCI-ISA configuration Register 68h~69h and must be 8­byte aligned. The Interface Register Block consists of two registers—Index Address Pointer
register and Data register located at base address +05h and base address +06h
respectively.

BASE ADDRESS REGISTER

+05h Index Address Pointer
+06h Data

All accesses to the Data Acquisition Module internal registers must be through the two
registers. First the Index Address Pointer should be written with the offset address of the
internal register, then the actual data read or write transaction can be carried out by reading
or writing to Data register.

3.5.6 INTERNAL REGISTERS

Limit registers set the lower and higher limits for voltages, temperature and fan speed. Note
that there is only lower limit for fan speed. A lower limit is considered to be exceeded if the
reading is less than lower limit, while a higher limit is considered to be exceeded if the
reading is greater than or equal to the higher limit. When the round-robin monitoring process
updates a reading which has exceeded a limit, an IRQ or SMI# can be generated, if the
corresponding Mask bit in NMI Mask register or SMI# Mask register is not disabled. At the
same time, the corresponding interrupt status bit at the Interrupt Status register will be set.
Reading the Interrupt Status register will reset all bits as well as clear outstanding interrupts.

3.6 INTEGRATED REAL TIME CLOCK (RTC)

3.6.1 REAL TIME CLOCK MODULE

The Real Time Clock module in the SiS5595 contains the industrial standard Real Time
Clock, which is compatible to MC146818, and the Automatic Power Control (APC) circuitry
mainly to support the ACPI power control functions. The Real Time Clock part provides a
time-of-day clock with alarm and one hundred year calendar, a programmable periodic
interrupt generator, 112 Bytes of standard CMOS SRAM, and 128 Byes of extended CMOS
SRAM. The Automatic Power Control part provides the software/hardware power up/down
functions. Figure 3.6-1 shows the block diagram of the RTC module.

Preliminary V2.0 Nov. 2, 1998 41 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

GPIO5O

PWRGD

PWRBTN#

Password

Hot_Key

OSC32KHI

AD[7:0]

PSRSTB#

PWRGD

AS
RD

WR
EXTEND_EN
APCREG_EN

RING
PME1#
PME0#

SPWROFF

S3OFF

RTC_ALARM

RTCOSC
APC.R7[7:0]
APC.R5[7:0]
APC.R4[7:0]
APC.R3[7:0]
APC.R2[7:0]

RTCDAY[2:0]

S5OFF

GPO6O

GPIO10O

OSC32KHO
APC.R6[5:0]
RTCDO[7:0]

RTC

Figure 3.6-1 RTC Module Block Diagram

APC

GPIO5O_EN

GPO6O_EN

GPIO10O_EN

GPIO5

GPO6

GPIO10

PS_ON#

3.6.1.1 RTC Registers & RAM

Three separate RTC registers & RAMs are provided in the SiS5595. One is called the
Standard Bank, another is the Extended Bank, and the other is the APC registers. All of
these registers are referenced through the same address and data port, i.e. Port 70h and
71h, respectively. The access control with which the three portions of registers can be
appropriately addressed are stored in PCI-ISA: 45h[3] (EXTEND_EN bit) and PCI-ISA:
45h[1] (APCREG_EN bit). Figure 3.6-2 shows the address map of the Standard Bank. In the
Standard Bank, the lower 10 bytes contain the time, calendar and alarm data. The registers
0Ah, 0Bh, 0Ch, and 0Dh contain the RTC control and status bytes. The last two bytes (7Eh,
7Fh) are the Day of the Month Alarm byte and the Month Alarm byte which are the extended
alarm features requested by the ACPI. The Day of the Month Alarm selects the day within
the month to generate a RTC alarm while the Month Alarm selects the month within the year
to generate a RTC alarm. The remaining 112 bytes in the Standard Bank are the general­purpose RAM bytes. In the Extended Bank, another 128 bytes are also provided for the
general-purpose usage.

Table 3.6-1 The Access of Standard/Extend Bank and APC Registers

STANDARD BANK EXTEND BANK APC

REGISTERS

EXTEND_EN 0 1 0

APCREG_EN 0 0 1

Preliminary V2.0 Nov. 2, 1998 42 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

00
0D
0E

7D
7E

7F

14 Bytes

112 Bytes

User SRAM

Day of the Month Alarm

Month Alarm

00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D

Seconds

Seconds Alarm

Minutes

Minutes Alarm

Hours

Hours Alarm

Day of the Week

Day of the Month

Month

Year
Register A
Register B
Register C
Register D

Figure 3.6-2 Address Map of the Standard Bank

3.6.1.2 RTC Update Cycle and RTC Alarm Event

The primary function of the update cycle is to increase the Seconds byte, update the other
time bytes, and compare each alarm byte with the corresponding time byte. When the alarm
time is written in the Month Alarm, Day of the Month Alarm, Hours Alarm, Minutes Alarm and
Seconds Alarm, a RTC Alarm Event will be activated at the time specified in those alarm
registers. A “don’t care” code can be set in one or more of the five alarm bytes by writing the
two most significant bits to 1 (11XX XXXX). For example, if the “don’t care” code is set in the
Month Alarm, the RTC Alarm Event will be generated at the time specified in the other four
alarm registers in every month. Similarly, the RTC Alarm Event will be generated at the time
specified in Hours Alarm, Minutes Alarm and Seconds Alarm every day if the Month Alarm
and the Day of the Month Alarm are both set to “don’t care” code. Note that the Day of the
Month Alarm and Month Alarm are “don’t care” by default. Figure 3.6-3 shows the block
diagram of the RTC.

Preliminary V2.0 Nov. 2, 1998 43 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

1Hz

OSC32KHI *1/32

Periodic Interrupt Selection (1 of 13 Selector)Divider Control

DV[2:0] RS[3:0]

*1/32*1/32

WR

RD

AD[7:0]

PWRGD

PSRSTB#

Register A, B, C, D

(4 Bytes)

Clock Alarm Calendar

AS

Clock Calendar Update

Bus Interface

BCD/Binary Increment

RTC Time Comparator

Register (12 Bytes)

User SRAM

(112 Bytes)

Extended SRAM

(128 Bytes)

APC Register

(6 Bytes)

INTIRQ8

RTCDAY[2:0]

EXTEND_EN

RTC_ALARM
APCREG_EN

APC.R2 ~

APC.R7

Figure 3.6-3 Block Diagram of RTC

3.6.1.3 RTC External Connection Requirement

The RTC is powered by RTCVDD and RTCVSS. In reality, not only the internal circuitry of
the RTC, but also the pins associated with the RTC module are also powered by this specific
power planes. They are PS_ON#, PWRGD, PSRSTB#, PWRBT#, RING, OSC32KHI,
OSC32KHO, GPIO5/PME0#/DUAL_ON#, GPO6/CKE_S/ACPILED and GPIO10/PME1#/
ACPILED. RING is an input pin by default, which should be pulled low while not used.

3.7 AUTOMATIC POWER CONTROL MODULE

APC module is only functional while internal RTC is used. If an external RTC is used, all
Automatic Power Control functions will be disabled automatically. ATX power supply has a
control signal PS_ON# and two set of VDD named VDD5V and AUX5V. The AUX5V will
output +5V as long as the AC power is applied to the ATX power supply, while the VDD5V
will only be activated when the PS_ON# signal is output low. APC controls the signal
PS_ON# to turn on or turn off VDD5V of ATX power supply. SiS5595 also supports PC’98
power supply, which will be discussed in “APC Functions” section.

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SiS5595 PCI System I/O Chipset

3.7.1 APC REGISTERS

The APC registers are provided to support the Auto Power Control Function. The register
02h defines the “Day of the Week Power Up” setting byte. The 03h, 04h, 05h, 06h, 07h, and
08h registers contain the control information for the Automatic Power Control functions.
Table 3.7-1 Address Map of the APC Control Registers shows the address map of the APC
registers.

Table 3.7-1 Address Map of the APC Control Registers

ADDRESS REGISGER NAME

00h Reserved
01h Reserved
02h APC Register 02h
03h APC Register 03h
04h APC Register 04h
05h APC Register 05h
06h APC Register 06h
07h APC Register 07h
08h APC Register 08h

3.7.2 APC FUNCTIONS

Let us take the following power up/down sequence as an example to illustrate the APC
functions. Figure 3.7-1 Typical Timing Sequence on the Power Control Related Signals
shows the typical timing sequence of the power control related signals.

RTCVDD

PSRSTB#

PS_ON#

AUX5V
VDD5V

PWRGD

Figure 3.7-1 Typical Timing Sequence on the Power Control Related Signals

3.7.2.1 APC Power Source Connection Requirement

The PSRSTB# is traditionally used to convey the battery life status to the RTC module. In
SiS core based system, the signal is also used to determine if the internal RTC is to be used.
A logic high on PSRSTB# inform SiS5595 that the internal RTC is selected.

Since the RTC must continue to count the time when the system power is removed, a
conversion from the system power to an alternate power supply, usually a battery, must be

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SiS5595 PCI System I/O Chipset

made. In a system equipped with the ATX power supply, it is recommended to design the
power conversion circuitry powered by both the AUX5V and battery. In practical application,
the PSRSTB# is low only when both the battery and the AUX5V is low. That is, PSRSTB# is
low whenever the battery happens to be exhausted and the power supply is not plugged yet.
Most of the cases in the application, the PSRSTB# is first restored to high by battery. As long
as the PSRSTB# is high and the system is in power down state (PWRGD is low), the power
up events can be recognized and results in the assertion of the PS_ON# to have the ATX
power supply provide VDD5V for the system. It is now obvious why the conversion circuitry
should use the AUX5V or battery for the power source. This ensures that the APC circuit
block can keep working while VDD5V is removed, and can sense the “Power Up Request
Events” to wake up the system by activating PS_ON#. In a word, RTC and APC controller
must be powered by AUX5V/battery through RTCVDD, and PSRSTB# signal must be high,
so that Power Up Request Events can wake up system power.

3.7.2.2 Power Up Request Events

During the power down period, the following events can power up the PC main board by the
assertion of PS_ON#. They are Power Button On event (via PWRBT#), Hot Key Match event
(via Keyboard Controller), Password Match event (via Keyboard Controller), RTC Alarm On
event (via RTC Alarm), Ring Up event (via RING), Power Management Event 1 (via PME1#),
Power Management Event 0 (via PME0#). Each power up function has its enable/disable bit
specified in APC Registers. Except Power Button On event, all the rest power up events are
enabled when APC_EN is set. APC module also provides five status bits to record the power
up request events, they are MNUP_STS, ALMUP_STS, RNUP_STS, PME1_STS, and
PME0_STS.

Note that PME0# and PME1# are low active logic and must be pulled high by external
resistors. If they are pulled high by AUX5V and the system AC power source is suddenly off
(that is, VDD5V and AUX5V are both disappeared), APC may recognize this as a power on
event and will activate PS_ON#. If the AC power source is recovered within 4 seconds, the
ATX power supply will be activated by this event. If PS_ON# is asserted due to an AC power
source suddenly off event and the AC power source is not recovered within 4 seconds, APC
will dessert PS_ON# automatically. In other words, APC will sample PWRGD while PS_ON#
is asserted. If PS_ON# is asserted and PWRGD is not asserted within 4 seconds, APC will
recognize this as a power failure event and will de-assert PS_ON# automatically. APC
module provides a PSON_RSM bit (APC 07h[5]) to disable this power failure detecting
function. While programming a 1 to this bit, PS_ON# can only be de-asserted by all power
down events (Power Button Override, Software Power Off, S3 Power Off, and S5 Power
Off). If RING is set to active low mode and the System Powered-up by Ring function is
enabled, it will show the same characters, too.

The following is the detail description of these power-up events:

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SiS5595 PCI System I/O Chipset

BTNUP Event

BTNUP_EN

Hot_Key Match Event

Password Match Event

RTC Alarm Event

RNUP Event

PME1

PME0

APC_EN

APC03h[6]

APC03h[7]

HKUP_EN

APC05h[5]

PSUP_EN

APC05h[6]

ALMUP_EN

APC03h[2]

DWAUP_EN

APC03h[7]

RNUP_EN

APC03h[5]

PME1_EN

APC07h[7]

PME0_EN

APC03h[3]

MNUP_STS

APC06h[0]

ALMUP_STS

APC06h[1]

RNUP_STS

APC06h[2]

PME1_STS

APC06h[3]

PME0_STS

APC06h[4]

PS_ON#

Figure 3.7-2 Power Up Request Events

• Power Button On Event :
SiS5595 provides a power button control pin, PWRBT#, to power up the system. While

PWRGD is low, a high to low transition with the active low logic lasting for more than 30ms
indicates the Power On Request Event which eventually activates the PS_ON#. While
PWRGD is high, the assertion of PWRBT# less than 4 seconds results in an SCI/SMI event,
and the assertion of PWRBT# more than 4 seconds will turn off the system. Power Button
On function is enabled by default and can be disabled by writing a 0 to BTNUP_EN. If the
AC power of the system is suddenly off (that is, VDD5V and AUX5V are both disappeared),
the function will be enabled automatically to ensure that the user can power up the system
by power button. Note that when PWRGD is low, Power Button on Event is controlled by
APC. After PWRGD going high, this event will be recognized and responded by ACPI.

BTNUP EventPWRBT# 30ms Debounce

Figure 3.7-3 Power Button On Event

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SiS5595 PCI System I/O Chipset

• Hot Key Match Event and Password Match Event :
SiS5595 build-in Keyboard Controller can generate two special events to power up the

system. They are Hot Key Match Event and Password Match Event. These two functions will
be disabled automatically while internal keyboard controller’s power is suddenly off. Please
refer to Keyboard Controller for more detail.

• RTC Alarm On Event :
When the time value of RTC matches the corresponding alarm bytes, the RTC would send

an “RTC Alarm Event” to the APC module. RTC alarm event can be created form once per
second to once per year. Beside the standard RTC Alarm power up function, SiS5595 also
provides an additional power up function called the “Day of the Week Alarm Power Up”.
Following are the detail description of these two alarm power-up functions:

• RTC Alarm Power Up Function :
If APC_EN and ALMUP_EN are enabled and the system is in power down state, an RTC

Alarm Event will power up the system.

• Day of the Week Alarm Power Up Function:
The Day of the Week Alarm Power Up Function can be enabled to power up the system on

selected days within a week. With this additional feature, SiS5595 allows the user to power
up the system, say, at 08:00 on each working day, and to stay at power off state on
weekend. The Day of the Week Alarm Power Up byte is located in APC register 02h. Note
that this feature is enabled when APC_EN and DWAUP_EN bits are both enabled, and
ALMUP_EN is disabled.

• Ring Up Event :
While PWRGD is low, the detection of an active RING pulse lasting for more than 4ms would

activate the PS_ON#. Note that the active high/low logic of the RING can be defined through
programming RN_POL. While PWRGD is high, the detection of RING pulse would generate
an SCI/SMI# event, which will be recognized and responded by ACPI. Please refer to ACPI
section for more details.

RING

4ms Debounce RNUP Event

RN_POL

APC03h[4]

Figure 3.7-4 Ring Up Event

• Power Manage Event 1 :
When the power is removed, a high to low transition on PME1# indicates a power

management event which will activate PS_ON#. When this function is used, APC 04h[3]
must be set to 1 to configure this pin in input mode. This power up function can be used to
accept PCI or AGP power management event (PME#) when system is in power down state.

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SiS5595 PCI System I/O Chipset

APC04h[3]

GPIO10/PME1#/ACPILED GPI10/PME1#

0
1

APC04h[3]

MUX

APC04h[1]

Low Pulse Over 30 us

Detection

GPO10

ACPILED

PME1

Figure 3.7-5 Power Manage Event 1

• Power Manage Event 0 :
When power is removed, a high to low transition on PME0# also indicates a power

management event which will activate PS_ON#. When this function is used, APC 04h[4]
must be set to 1 to configure this pin in input mode. This power up function can also be used
to accept PCI or AGP power management event PME# when system is in power down state.

APC04h[4]

GPIO5/PME0#/DUAL_ON# GPI5/PME0#

0
1

APC04h[4]

MUX

APC04h[5]

H to L Edge

Detection

DUAL_ON#

GPO5

PME0

Figure 3.7-6 Power Manage Event 0

3.7.2.3 Power Down Request Events

While in the power up state, the following events can power down the PC main board by the
de-assertion of PS_ON#. They are Power-Button-Over-Ride Event (via PWRBT#), S3 Power
Off Event, S5 Power Off Event and Software Power Off Event (via PCI-ISA: 63h[2]).
Following is the detailed description of these events:

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SiS5595 PCI System I/O Chipset

Power Button

Override Event

Soft Off Event

PS_ON#

S5 Off Event

S3 Off Event

APC_EN

APC03h[6]

Figure 3.7-7 Power Down Request Eve

• Power-Button-Over-Ride Event :
Power-Button-Over-Ride event is generated when the Power Button has been pushed for

more than 4 seconds. The SiS5595 will de-assert the PS_ON# if Power-Button-Over-Ride
event occurs. Please note that this is purely done by hardware. No special support from
BIOS is required.

• Software Power Off Event :
When APC_EN is enabled and the system is in power up state, writing a 1 to Power Off

System Control bit (PCI-ISA: 63h[2]) can de-assert PS_ON#.

STR_STS
APC06h[5]

• S5 Power Off Event :
SiS5595 also provides another alternative to de-assert PS_ON# signal. When system is in

power up state and APC_EN is enabled, programming a ‘1’ to SLP_EN bit (ACPI 04h[13])
and ‘101’ (S5 state) to SLP_TYP bits (ACPI 04h[12:10]) can sequence the system into S5
state with the consequence that PS_ON# is negated eventually.

• S3 Off Event :
When system is in power up state and APC_EN is enabled, programming a 1 to SLP_EN

(ACPI 04h[13]) and ‘011’ (S3 state) to SLP_TYP bits (ACPI 04h[12:10]) can force the system
enter S3 state with the consequence that PS_ON# is negated eventually. This will be
discussed in next section and ACPI section.

3.7.3 S3 (STR) FUNCTION RELATED SIGNALS

SiS5595 supports the ACPI S3 state or equivalently the ‘Suspend to RAM (STR)’ state which
essentially turns off the system power except the power for the memory subsystem (mainly
SDRAM). During the S3 State, the SDRAM memory subsystem should be put into self­refresh mode. The following illustrates the three multi-function pins, namely GPIO5, GPO6,
and GPIO10 that are mainly used to support the S3 state.

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SiS5595 PCI System I/O Chipset

3.7.3.1 GPIO5/PME0#/DUAL_ON# :

APC 04h[5] APC 03h[3] Function Select

1 0 GPIO5
1 1 PME0#

0 X DUAL_ON#
*APC 04h[4] : I/O Mode selection bit (0:output mode)
*APC 05h[7] : DUAL_ON# active level (1:active low)

• DUAL_ON# :
While operating in this mode, the pin can be connected to the DUAL_ON# signal of the

PC’98 power supply. APC 05h[7] determines the logic of this pin running in this mode. Note
that: in addition to configure this pin as the DUAL_ON# function, and CKE_S can also be
done as it will explain later. Following shows the output level of DUAL_ON# while
programming APC 05h[7] to 0 or 1.

APC 05h[7] = 0 APC 05h[7] = 1

Normal State 1 0

Suspend State 1 0

Soft Off State 0 1

3.7.3.2 GPO6/CKE_S/ACPILED :

APC 04h[2] APC 07h[6] Function Select

1 X GPO6

0 0 CKE_S

0 1 ACPILED
*APC 04h[0] : ACPILED supports 1 Hz blinking (0:disable)

• CKE_S :
While entering S3 State, the SiS core based system can keep the SDRAM in the self-refresh

mode by driving CKE_S low. Please refer to ACPI for more detail on the CKE_S function.
Besides, when supporting PC’98 power supply, the CKE_S signal can be connected to the
DUAL_ON# of power supply, too. The following summarizes the power supply subsystem
operating states supported by the power supply ’98.

PS_ON# DUAL_ON# CKE_S SYSTEM

STATE

STANDBY
OUTPUTS

DUAL

OUTPUTS

MAIN

OUTPUTS

1 1 Z Soft Off ON OFF OFF

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SiS5595 PCI System I/O Chipset

1 0 0 Suspend

(S3)

0 X Z Normal ON ON ON

1.When system wakes up from S3 state, APC 04h[7] must be programmed to 1 to reset
CKE_S output level.

* CKE_S must be pulled high by an external resistor.

3.7.3.3 GPIO10/PME1#/ACPILED :

APC 04h[1] APC 07h[7] Function Select

0 0 GPIO10
0 1 PME1#

1 X ACPILED
*APC 04h[3] : Pin I/O Mode selection bit (0:output mode)
*APC 04h[0] : ACPILED support 1 Hz blinking (0:disable)

• ACPILED :
It is up to the application to configure either GPO6 or GPIO10 as the ACPILED signal.

ACPILED is driven low to turn on the LED while the system is in the S0, S1, or S2 states. It
is floated in all other system states. Optionally, the LED can be put in the blinking state by
setting APC 04h[0] while in the S0, S1, or S2 states.

3.8 INTEGRATED KEYBOARD CONTROLLER

ON ON OFF

The built-in KBC (Keyboard Controller) module uses hardwired methodology instead of
software implementation as the traditional 8042 keyboard BIOS commands. In this way, the
built-in KBC can have instant response to all the commands. It also has Fast Gate-20 and
Fast Reset Features. Besides, the built-in KBC supports the industrial standard PS/2 mouse
optionally. Moreover, the password security and the hot-key <CTRL+ALT+ Backspace>
power up functions are implemented.

3.8.1 STATUS REGISTER

The status register is an 8-bit read-only register located at address hex 64 of the I/O space
and can be read at any time. It provides the state information of the built-in KBC and the
interface. The definitions of each bit are described in the following:

BIT ACCESS DESCRIPTION

7 RO

6 RO

Preliminary V2.0 Nov. 2, 1998 52 Silicon Integrated Systems Corporation

Parity Error

0: The last byte received from the keyboard had Odd Parity

(No parity error).

1: The last byte received from the keyboard had Even Parity

(Parity error).

Time-out error

0: No Transmission Time-out Error is occurred.
1: Transmission Time-out Error is occurred.

SiS5595 PCI System I/O Chipset

5 RO

4 RO

3 RO

2 RO

1 RO

0 RO

Auxiliary Output Buffer Full

0: The Output Buffer’s data is from the Keyboard.
1: The Output Buffer’s data is from the Mouse.

Inhibit Switch

0: The Keyboard is Inhibited.
1: The Keyboard is not Inhibited.

Command/Data

0: The data is written to the I/O 60h, it is interpreted as a ‘data

byte’.

1: The data is written to the I/O 64h, it is interpreted as a

‘command byte’.

System Flag

This bit may be set to 0 or 1 by writing the system flag bit in the
command byte. After a power on reset, it is cleared to 0.

Input Buffer Full

0: The Input Buffer is Empty.
1: The Input Buffer is Full. Data has been written into the input

buffer but the controller has not read the data.

Output Buffer Full

0: The Output Buffer is Empty.
1: The Output Buffer is Full. The controller has placed data into

the output buffer but the system has not yet read data.

3.8.2 INPUT/OUTPUT BUFFER

3.8.2.1 Input Buffer

The input buffer is an 8-bit write-only register located at address hex 60 or 64 of the I/O
space. Writing to address hex 60 would set the bit 3 of status register to ‘0’, which indicates
a ‘data byte’; writing to address hex 64 would set the bit 3 of status register to ‘1’, which
indicates a ‘command byte’. Data written to I/O address hex 60 is sent to the keyboard,
unless the keyboard controller is expecting a ‘data byte’ following a controller’s BIOS
command. Data should be written to the input buffer only if the input buffer’s full bit in the
status register equals to ‘0’.

3.8.2.2 Output Buffer

The output buffer is an 8-bit read-only register only located at address hex 60 of the I/O
space. The keyboard controller would place the codes received from the keyboard or the
return values of the KBC BIOS commands into the output buffer. The output buffer should be
read only when output buffer’s full bit in the status register equals to ‘1’.

3.8.3 INTERNAL OUTPUT PORT DEFINITIONS

The Internal Output Port includes two signals, P20 and P21, which are defined as following:

NAME DEFINITIONS

P20

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RC – Keyboard Hardware Reset Control Signal

SiS5595 PCI System I/O Chipset

1 : Inactive ( default )
0 : Active

P21

3.8.4 KEYBOARD INTERNAL BIOS COMMANDS ( I/O PORT 64H )

Command Keyboard Mode Keyboard PS/2 Mode

GA20 – Gate 20 Control Signal

1 : Inactive ( default )
0 : Active

01 – 1F

20 (00)

21 – 3F
41 – 5F

60 (40)

61 – 7F

Read Internal RAM – The controller sends value of RAM to output buffer.
Read Keyboard Controller’s Command byte – The controller sends the

current Command Byte to its output buffer.
Read Internal RAM – The controller sends value of RAM to output buffer.
Write Internal RAM – The next byte of data written to I/O 60h is placed into

Internal RAM.
Write Keyboard Controller’s Command Byte – The next byte of data written

to I/O 60h is placed in the controller’s command byte.

BIT BIT DEFINITIONS

0

1 – Enable Keyboard Output-Buffer-Full Interrupt

The KBC would generate an interrupt when it places keyboard
data into its output buffer.

1 – Enable Mouse-Buffer-Full Interrupt

1

The KBC would generate an interrupt when it places mouse data
into its output buffer.

1 – The controller generates a System Flag.

2

The value written to this bit is placed in the system flag bit of the
controller’s status register.

1– Disable Keyboard lock Switch “KLOCK#” (Even when the

3

KLOCK# enable bit equals 1).

4

1 – Disable Keyboard.

Disable the Keyboard interface by driving the ‘keyboard clock’ line
low. Data won’t be sent or received.

5

1 – Disable Mouse.

Disable the Mouse interface by driving the ‘mouse clock’ line low.
Data won’t be sent or received.

6

1 – IBM Personal Computer Compatibility Mode.

Convert the scan codes received from keyboard to IBM PC. This
includes converting a two-byte sequence to the one-bye IBM
Personal Computer format.

0 – Reserved.

7

Write Internal RAM – The next byte of data written to I/O 60h is placed into
Internal RAM.

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SiS5595 PCI System I/O Chipset

A0

A1

A4

A5

A6

A7

A8

A9

AA

Read Internal ROM – The controller would convert the scan codes ‘E0h’ and
‘FFh’ into Kscan codes, and place the result in the output buffer.

Read Keyboard Controller’s Version – The version code (48h) will be placed
to the output buffer.

Reset Internal Register B to 00h. Test Password Installed – The

controller would send test result to its
output buffer.

FAh – The Password has been
installed.

F1h – The Password is not installed.

Reset Internal Register B to 01h. Load Password – The next byte of

data written to I/O 60h is placed into
password stream (Max 15 bytes) that
ends with “00h”. The password is
stored in scan code format.

Read Internal Register B – The
controller sends value to the output
buffer.

Set Internal Register C to 00h. Disable Mouse Device – The mouse

Set Internal Register C to 01h. Enable Mouse Device – The mouse

Read Internal Register C – The
controller sends value to the output
buffer.

Self-Test – This command would result in the internal reset and test of KBC.
If the test is successful, the value 55h will be placed in the output buffer.

Enable Password Security – The
keyboard data won’t be sent to output
buffer until the input character string
matches the pre-loaded password.

interface is disabled by driving the
mouse clock line low.

interface is enabled by driving the
mouse clock line floating.

( Not Implemented in 5595)
Reference: Mouse Device Interface

Test – This command tests the
controller’s mouse clock and data
line, and place the result to output
buffer as follows :

00 – No error detected.
01 – The ‘Mouse Clock” line is stuck

low.
02 – The ‘Mouse Clock’ line is stuck

high.
03 – The ‘Mouse data’ line is stuck

low.
04 – The ‘Mouse data’ line is stuck

high.

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SiS5595 PCI System I/O Chipset

AB

AD

AE

CA

CB

D0

D1

D2

D3

D4

D6

D7

( Not Implemented in 5595)
Reference: Keyboard Interface Test – This command tests the keyboard

clock and data line, and the test result is placed in the output buffer as
follows :

00 – No Error detected.
01 – The ‘Keyboard Clock’ line is stuck low.
02 – The ‘Keyboard Clock’ line is stuck high.
03 – The ‘Keyboard Data’ line is stuck low.
04 – The ‘Keyboard Data’ line is stuck high.
Disable Keyboard Interface – This command would set the bit 4 of the

controller’s command byte, and disable the keyboard interface by driving the
clock line low. Data will not be sent or received.

Enable Keyboard Interface – This command would clear the bit 4 of
command byte and release the keyboard interface.

Read Internal Register D – The Internal Register will be placed into its
output buffer.

Write Internal Register D – The next byte of data written to I/O 60h is placed
in the controller’s Register D.

Read Internal Output Port – The value of P20 and P21 would be placed in
the bit 0 and bit 1 of the output buffer respectively. This command should be
issued only if the output buffer is empty.

Write Internal Output Port – The bit 0 and bit 1 of the next byte written to I/O
60h would be placed in the P20 and P21 respectively. The other bits are
reserved and should be written to ‘1’.

Write Keyboard Output Buffer – The next byte of data written to I/O port 60h
is placed in output buffer as it received from keyboard.

Not Valid Write Mouse Output Buffer – The next

byte of data written to I/O port 60h is
placed in output buffer as it received
from mouse.

Not Valid Write Mouse Device – The next byte

written to I/O 60h is transmitted to
mouse device.

Enable Keyboard Lock < KLOCK#> Switch (Default: Enable) – The KLOCK#
function will work if the KLOCK# function enable bit is enabled.

Disable Keyboard Lock Switch < KLOCK# > – The KLOCK# function won’t
work even when the KLOCK# function enable bit is enabled.

3.8.5 PASSWORD SECURITY AND KEYBOARD POWER UP FUNCTIONS

Traditional password security function in the KBC has provided the ability of protecting your
PC from being invaded. SiS5595/KBC supports the function with registers to store the
password character string, and a pattern recognition circuitry to identify if an input character
string matches the pre-loaded password.

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SiS5595 PCI System I/O Chipset

Writing A4h to I/O port 64h directs the SiS5595/KBC to store the successive data written
through I/O port 60h into the password string register until character 00h is input. ‘00h’ is
regarded as the end code of the password. Enabling the password security is done by
programming I/O port 64h with data A6h. Once being initiated in this mode, the KBC won’t
issue IRQ1 to invoke the KB interrupt service routine until the input string matches the
password. Thus, the system can be protected from invading to some degree.

Moreover, a more user friendly interface or higher security service has led to the request of
the password security power up function. A specific power pin, called KBVDD is allocated for
the whole KBC circuitry in the SiS5595 to support the function. A power conversion circuit is
required to forward power to the SiS5595’s KBC, and the keyboard. During the powered­down state of the power rails (including 3.3V, ±5V, ±12V), AUX5V supplies power to the
KBC, and the keyboard. Upon the moment that VDD is gone away, the pattern recognition
circuitry inside KBC is automatically configured to process the input keyboard string. Once
the input string matches the pre-loaded password, the PS_ON# is asserted to turn on the
ATX power supply if the password security power up function is enabled.

The following illustrates a procedure to regulate the password security and hot-key power up
functions in application. It is highly recommended that the BIOS programmers could follow
the sequence in the procedure. For the simplicity and readability, the events that the power
up function is altered in the sequence are not included in our procedure. For example, the
system was powered up by pressing password and the user want to power up the system by
hot-key next time. However, such events are practicable.

3.8.5.1 Procedure Regulating the Password Security and Hot-key Power up Functions

If (!CMOS_Valid) /* Initialize all CMOS setting */

Initialize( );

else { if PSUP_SET /* User has enabled KB password security

Password_Check( ); power up function */

else if HKUP_SET /* User has enabled KB hot-key power up
else /* PSUP_SET and HK_SET are software

}
Continue BIOS Posting;

Initialize( )
{Clear PSUP_SET;
Clear HKUP_SET;
Password_or_Hotkey_Setting( );
}

Password_Check( )
{If KBP_LST /* Keyboard power had ever lost */
{Clear KPR_LST; /* Enter second level security protection */

Request the user to enter the password string [*1] and identify it;
Reload password string into KBC;
Enable PSUP_EN ;

Disable BTNUP_EN; [*2]
}
else Reload password string into KBC ; /* Keyboard power is not lost and the
system is powered up by KBC */
}

Hotkey_Check( ); function */
Password_or_Hotkey_Setting( ); variable used to regulate the functions */

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SiS5595 PCI System I/O Chipset

Hotkey_Check ( )
{If KPR_LST

{Clear KPR_LST;

Enable HKUP_EN;

Disable BTNUP_EN;

}
}

Password_or_Hotkey_Setting( )
{Clear KPR_LST;
If (password security power up function is selected [*3])

{Set and load KB password into KBC;

Enable PSUP_EN;

Enable PSUP_SET;

Disable BTNUP_EN;
if ( hot-key power up function is selected [*3] )

}

[*1] Typically, the password string is stored in the RTC CMOS RAM.

}

{Enable HKUP_EN;

Enable HKUP_SET;

Disable BTNUP_SET;

}

[*2] It is apparent that BTNUP_EN should be disabled if password security or hot-key power
up function is enabled. Otherwise, the system can be powered up simply by pressing the
Power-Button for over 30ms. However, BTNUP_EN will be automatically enabled to allow
manually power up the system if the KBC power has ever lost. The KBP_LST locating in the
RTC APC register file is designed to reflect the KBC power status. When KBC power has
ever lost, KBP_LST is set with the result that BTNUP_EN is set, and that KBC is held in
“CLEAR” state when keyboard power is restored later. Both PSUP_EN and HKUP_EN are
cleared also. Ending the KBC clear state can be done by writing logic 0 to KPR_LST.

[*3] User can select the password security or hot-key power up function normally through
setting the corresponding option in the BIOS setup menu. As a result, PSUP_SET or
HKUP_SET is set. If the user wants to change the enabled power up function in the
sequence, this setting menu can do it also.

The following bits are used to support the password security or hot-key power up function.
They are placed in the RTC module, and thus are retained as long as RTC power is there.

KBP_LST : APC 07h[0]

BTNUP_EN : APC 03h[7]

PSUP_EN : APC 05h[6]

HKUP_EN : APC 05h[5]

3.8.6 RELATED PCI TO ISA BRIDGE CONFIGURATION REGISTERS

R64h bit 0: Enable Keyboard Hardware Reset

R6Dh bit 1: Keyboard Hot-key Status

Preliminary V2.0 Nov. 2, 1998 58 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

R6Dh bit 0: Keyboard Hot-key Control

R70h bit 4: Enable KLOCK# Function

R70h bit3: Enable Built-in Keyboard Controller

R70h bit2: Enable PS/2 Mouse Mode

3.9 ISA BUS INTERFACE

3.9.1 ISA BUS CONTROLLER

The SiS5595’s ISA Bus Interface accepts those cycles from PCI bus interface and then
translates them onto the ISA bus. It also requests the PCI master bridge to generate PCI
cycle on behalf of DMA or ISA master devices. The ISA bus interface thus contains a
standard ISA Bus Controller (IBC) and Data Buffering logic. IBC provides all the ISA control,
such as ISA command generation, I/O recovery control, wait-state insertion, and data buffer
steering. The PCI to/from ISA address and data bus buffering are also integrated in SiS5595.
The SiS5595 can directly support 4 ISA slots without external data or address buffering.

Standard ISA bus refresh is requested by Counter 1, and then performed via the IBC. IBC
generates the pertinent command and refresh address to the ISA bus. Since the ISA refresh
is transparent to the PCI bus and the DMA cycle, an arbiter is employed to resolve the
possible conflicts among PCI cycles, refresh cycles, and DMA cycles.

3.9.2 DMA CONTROLLER

The SiS5595 contains a seven-channel DMA controller. Channels 0 to 3 are for 8-bit DMA
devices while channels 5 to 7 are for 16-bit devices. The channels can also be programmed
for any of the four transfer modes, which include single, demand, block, and cascade.
Except in cascade mode, each of the three active transfer modes can perform three different
types of transfers, which include read, write, and verify. The address generation circuitry in
SiS5595 can support 32-bit address for DMA devices.

3.9.3 INTERRUPT CONTROLLER

The SiS5595 provides an ISA compatible interrupt controller that incorporates the
functionality of two 8259 interrupt controllers. The two controllers are cascaded so that 14
external and two internal interrupts are supported. The master interrupt controller provides
IRQ<7:0> and the slave provides IRQ<15:8>. The two internal interrupts are used for internal
functions only and are not available externally. IRQ2 is used to cascade the two controllers
together and IRQ0 is used as a system timer interrupt and is tied to interval Counter 0. The
remaining 14 interrupt lines are available for external system interrupts.

Table 3.9-1 8259 IRQs Mapping

PRIORITY LABEL CONTROLLER TYPICAL INTERRUPT SOURCE

1 IRQ0 1 Timer/Counter 0 Out
2 IRQ1 1 Keyboard

3-10 IRQ2 1 Interrupt from Controller 2

3 IRQ8# 2 Real Time Clock
4 IRQ9 2 Expansion bus pin B04

Preliminary V2.0 Nov. 2, 1998 59 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

5 IRQ10 2 Expansion bus pin D03
6 IRQ11 2 Expansion bus pin D04
7 IRQ12 2 Expansion bus pin D05
8 IRQ13 2 Coprocessor Error FERR#
9 IRQ14 2 Fixed Disk Drive Controller Expansion bus

pin D07
10 IRQ15 2 Expansion bus pin D06
11 IRQ3 1 Serial port 2, Expansion Bus B25
12 IRQ4 1 Serial port 1, Expansion Bus B24
13 IRQ5 1 Parallel Port 2, Expansion Bus B23
14 IRQ6 1 Diskette Controller, Expansion Bus B22
15 IRQ7 1 Parallel Port1, Expansion Bus B21

In addition to the ISA features, the ability to do interrupt sharing is included. Two registers
located at 4D0h and 4D1h are defined to allow edge or level sense selection to be made on
an individual channel by channel basis instead of on a complete bank of channels. Note that
the default of IRQ0, IRQ1, IRQ2, IRQ8 and IRQ13 is edge sensitive, and can not be
programmed. Also, each PCI Interrupt (INTx#) can be programmed independently to route to
one of the eleven ISA compatible interrupts (IRQ<7:3>, IRQ<15:14>, and IRQ<12:9>)
through PCI to ISA bridge configuration registers 41h to 44h.

3.9.4 INTERRUPT STEERING

For each interrupt channel, an interrupt router is associated, serving as an interface between
bunches of the interrupt request lines and the 8259 interrupt controller as shown in figures
below. These routers can be classified into two categories, one for the IRQ [7:3], IRQ [12:9],
and IRQ [15:14], and one for the IRQ0, IRQ1, IRQ8, and IRQ13. The following interrupt
request lines can be routed to the IRQx of the first category.

Illustrates the structure of the Interrupt Router.

1) PCI Interrupt INT [A:D]#, and SIRQ [A:D]# through programming PCI to ISA register 41­44h,

2) IDE Interrupt request line through programming PCI to ISA register 61h,

3) USB Interrupt request line through programming register PCI to ISA 62h,

4) ACPI/SCI interrupt request line through programming register PCI to ISA 6Ah,

5) Data Acquisition and SMBus Interrupt request line via programming register PCI to ISA
7Eh,

6) SIRQx interrupt request line via programming PCI to ISA registers 89h, 8Ah, where x
can be [7:3], [12:9], and [15:14].

Except the SIRQx, the rest of the interrupt requests are regarded to be sharable. That is,
more than one line of interrupt request can be routed to the same IRQx. While supporting the
shared interrupts, the associated IRQ channel must be set in the level sensitive mode.
Enabling any of the routing registers will automatically mask the ISA Interrupt request to the
corresponding IRQ. SIRQ [A:D]# are regarded to work in the level sensitive mode, while
SIRQx in the level or edge sensitive mode. While configuring the SIRQ [A:D]# to any of the

Preliminary V2.0 Nov. 2, 1998 60 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

IRQx, in addition to the enabling of PCI to ISA Register 41h to 44h, the BIOS should also set
bit 3 to bit 6 of PCI to ISA Register 8Ch for each SIRQ, respectively.

SIRQ1 can be routed to IRQ1 while bit 0 of PCI to ISA register 89h is set.
SIRQ8 can be routed to IRQ8 while bit 7 of PCI to ISA register 89h is set.
SIRQ13 can be routed to IRQ13 if bit 4 of PCI to ISA register 8Ah is set.
ACPI/SCI can also be routed to IRQ13 via programming PCI to ISA register 6Ah.

To support some super I/O devices that don’t keep their SIRQ1 (or 12) active until the INTR
to the CPU is driven active, SIRQ1 (or SIRQ12) will be internally latched on its rising edge if
bit 7 (or bit 6) of register 64h is set, respectively. Reading port 60h clears the latch.
Optionally, setting the SIRQ bit of IRQ1 (or IRQ12) can clear the latch if bit 7 of Register 67h
is set.

ELCR/4D0H

7
6
5
4
3
2
1
0

7
6
5
4
3
2
1
0

ELCR/4D1H

Interrupt

Controller

Interrupt

Controller

1

2

INTR

IRQ(7:3,12:9,15:14)

SIRQ(7:3,12:9,15:14)

SIRQ[A:D]#

ACPI/SCIIRQ13

INT[A:D]#

USBIRQ

ACPI/SCI

DAMIRQ

IRQ1

SIRQ1

OUT0

IRQ13

SIRQ13

IRQ8

SIRQ8

IR7
IR6
IR5
IR4
IR3
IR1

IR15
IR14
IR13
IR12
IR11
IR10

IR9
IR8

IRL7
IRL6
IRL5

IRL4

IRL3

IRL1

IRL15

IRL14

IRL13

IRL12

IRL11

IRL10

IRL9

IRL8

Figure 3.9-1 Interrupt Router IRx

Note: ELCR-Edge/Level-triggered Control Register

3.9.5 TIMER/COUNTER

The SiS5595 contains 3 counter/timers that are equivalent to those found in the 8254
programmable interval timer. The counters use a division of 14.318MHz OSC input as the
clock source. The outputs of the timers are directed to key system functions. Counter 0 is
connected to the interrupt controller IRQ0 and provides a system timer interrupt for a time-of­day, diskette time-out, or the other system timing function. Counter 1 generates a refresh­request signal and Counter 2 generates the tone for the speaker.

3.10 SYSTEM RESET

Power-on Reset

When the system is initially powered, the power supply must wait until all voltages are stable
for at least one millisecond, and then assert PWRGD signal. While PWRGD is deasserted,
chipset must hold its PCI bus in reset. While power-on reset is asserted, chipset will reset
and initialize their internal registers. Chipset must also initialize their PCI busses by asserting
PCIRST# for a minimum of one millisecond. For Pentiumn II processor in power-on

Preliminary V2.0 Nov. 2, 1998 61 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

configuration, the core logic must assert BREQ0# before the clock in which CPURST# is
deasserted. BREQ0# must be deasserted by core logic in the clock after CPURST# is
sampled deasserted. CPU agent 0 must delay BREQ0# assertion for a minimum of three
clocks after the clock in which CPURST# is deasserted to guarantee wire-or glitch free
operation. This sequence of events is shown following.

CPUCLK

PWRGD

CPURST#

INIT#

PCIRST#

BREQ0#

min. 10 clk

about 1ms

about 1ms

Figure 3.10-1 Timing Sequence for Power-on Process

Soft Reset (INIT)

The SiS5595 can be programmed to deliver a soft reset to processors through the Reset
control register. A soft reset asserts the INIT signal for 2us. The INIT signal resets all
processors without effecting their internal caches or bus state machines. After soft reset, the
processors begin to execute from address 00_FFFF_FFF0h. SiS5595 devices are not
effected by the INIT signal. SiS5595 also can be programmed to deliver a CPU reset to
processors through the Reset control register. The timing is the same as INIT.

CPUCLK
ADS#

PCICLK
FRAME#
AD[31:0]

FRSTTRG

INIT# / CPURST#

64h

6us or 2us about 2us
depend on reset latency control bit

Figure 3.10-2 Timing for Generating INIT#/CPURST#

Preliminary V2.0 Nov. 2, 1998 62 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

4 PIN DESCRIPTIONS

4.1 PCI/ISA BUS INTERFACE
SiS5595

PIN NO.

142, 137,
139, 134,
135, 140,
131, 133,
196, 197,
200, 202,
203, 206,
207, 208

179, 178,
177, 175,
170, 171,
167, 166,
165, 164,
163, 161,
160, 156,
155, 153,
147

190, 189,
187, 186,
185, 184,
183

181 SBHE# I/O

149 IORC# I/O

148 IOWC# I/O

193 MRDC# I/O

NAME TYPE

ATTR

SD[15:0] I/O

SA[16:0] I/O

LA[23:17] I/O

DESCRIPTION

ISA Data bus:

SD[7:0] is the lower byte of ISA data bus.
SD[15:8] is the upper byte of ISA data bus.

ISA Address bus:

External SA[19:17] with SA[16:0] allow memory
space addressing up to 1 Mbytes.

SA[15:0] allow IO space addressing up to 64Kbyte.

ISA LA[23:17] address bus:

LA[23:17] allow memory space addressing up to 16
Mbytes.

System Byte High Enable:

When asserted, it indicates the upper byte of the
ISA data bus, i.e. SD[15:8], contains valid data.

ISA bus I/O Read Command:

IORC# is asserted to indicate the addressed IO
device should drive its data onto the ISA data bus.
This pin is input during ISA master cycles and
output otherwise.

ISA bus I/O Write Command:

IOWC# is asserted to strobe data into the
addressed IO device. This pin is input during ISA
master cycles and output otherwise.

ISA bus Memory Read Command:

MRDC# is asserted to indicate the addressed
memory device should drive its data onto the ISA
data bus. This pin is input during ISA master cycles
and output otherwise.

Preliminary V2.0 Nov. 2, 1998 63 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

195 MWTC# I/O

145 SMRDC# O

144 SMWTC# O

176 BALE O

180 IO16# I

182 M16# I/O

159 RFH# I/O

136 ZWS# I

141 IOCHRDY I/O

138 AEN O

ISA bus Memory Write Command:

MWTC# is asserted to strobe data into the
addressed memory device. This pin is input during
ISA master cycles and output otherwise.

ISA bus Memory Read Command—address
below 1Mbyte:

For memory addresses within 000000h-0FFFFFh, it
is asserted to indicate the addressed memory
device should drive its data onto the ISA data bus.

ISA bus Memory Write Command—address
below 1 Mbytes:

For memory addresses within 000000h-0FFFFFh, it
is asserted to strobe data into the addressed
memory device.

Bus Address Latch Enable:

BALE indicates ISA address bus, LA[23:17],
SA[16:0] and SBHE#, contain valid ISA address.

16-bit I/O Chip Select:

IO16# is asserted by the addressed IO device to
indicate that it is capable of doing 16-bit data
transfers.

16-bit Memory Chip Select:

M16# is asserted by the addressed memory device
to indicate that it is capable of doing 16-bit data
transfers.

Refresh:

RFH# is asserted during ISA refresh cycles. This pin
is input during ISA master cycles and output
otherwise.

Zero Wait State:

ZWS# is asserted by the addressed device to
indicate that the current ISA cycle can be terminated
without any additional wait-states.

I/O Channel Ready:

IOCHRDY is de-asserted by the addressed slave
device to indicate more wait-states are required to
complete the current ISA transaction. This pin is
output during ISA master and DMA cycles and input
otherwise.

Address Enable:

Address Enable is driven high during DMA and
refresh cycles.

Preliminary V2.0 Nov. 2, 1998 64 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

162 BCLK O

173 TC O

191, 158,
132, 152,
199, 201,
204

192, 157,
169, 154,
194, 198,
205

143, 146, 8,
9, 2, 3, 4, 5,
7, 6

4.2 PCI BUS + CPU INTERFACE

SiS5595
PIN NO.

102, 91, 82,76C/BE[3:0]# I/O

87 FRAME# I/O
112, 111,

110, 108,
107, 106,
105, 103,
101, 100,
98, 97, 96,
95, 94, 93,
80, 79, 78,
77, 75, 74,
72, 71, 70,
69, 68, 67,
66, 65, 63,
61

92 IRDY# I/O
86 TRDY# I/O
58 PCLK I
83 SERR# I

DRQ[3:0]
DRQ[7:5]

DACK[3:0]#
DACK[7:5]#

IRQ[15:14],
IRQ[11:9],
IRQ[7:3]

NAME TYPE

AD[31:0] I/O

O

ATTR

I

I

ISA Bus Clock:

The ISA bus clock can be optionally derived from
PCI clock or the CLK14M input.

Terminal Count of DMA:

A high pulse on TC during DMA cycles indicates
one of the DMA channels has completed its
transfers.

DMA Request:

They will be asserted by external ISA devices to
request for DMA service or become ISA masters.

DMA Acknowledge:

When one of them is asserted, it indicates the
corresponding DMA request has been granted.

Interrupt Request:

These are interrupt requests input to the internal
8259-compatible Interrupt Controller.

DESCRIPTION

PCI Bus Command and Byte Enables:

Comply with PCI specification 2.1

PCI FRAME#: Comply with PCI specification 2.1
PCI Address/Data Bus:

Comply with PCI specification 2.1

PCI IRDY#: Comply with PCI specification 2.1
PCI TRDY#: Comply with PCI specification 2.1
PCI Clock: Comply with PCI specification 2.1
System Error:

When sampled active low, a non-maskable interrupt
(NMI) can be generated to CPU if enabled.

Preliminary V2.0 Nov. 2, 1998 65 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

-

-

89 DEVSEL# I/O

84 STOP# I/O
113 PHOLD# O

125 PHLDA# I

56, 57, 59,60INT[A:D]# I

126 PCIRST# OD

151

130

PDMAREQ0#

PDMAGNT0#

I

O

47 NMI OD

Device Select:

SiS5595 will do positive decoding with medium
timing to:

- SiS5595 PCI configuration registers access

- Built-in legacy ISA bus embedded controller
registers access

- BIOS ROM memory access

- Interrupt acknowledge cycle
In addition, SiS5595 will do subtractive decoding to:

I/O address range 00000000h-0000FFFFh.(Low

64 Kbytes)

Memory address range 00000000h-00FFFFFFh

(Low 16 Mbytes).

PCI STOP#: Comply with PCI specification 2.1
PCI Bus Hold Request:

PHOLD# is asserted to inform the PCI system arbiter
located at north-bridge chipset that SiS5595 is
intending to become PCI bus master. SiS5595
asserts PHOLD# on behalf of three local devices
including ISA/DMA master, Distributed DMA master
and USB master.

PCI Bus Hold Acknowledge:

The PCI system arbiter responds to the assertion of
PHOLD# by driving PHLDA# low, indicating SiS5595
can start its PCI master cycles.

PCI interrupt A,B,C,D:

The PCI interrupts will be connected to the inputs of
the internal Interrupt controller through the rerouting
logic associated with each PCI interrupt.

PCI Bus Reset:

PCIRST# will be asserted during the period when
PWRGD is low, and will be kept on asserting until
about 1 ms after PWRGD goes high.

PC/PCI DMA Request 0: This signal is used by PCI
agent to request DMA services.

PC/PCI DMA Grant 0: This signal is used by 5595 to
indicate which DMA channel is granted.

Non-Maskable Interrupt:

A rising edge on NMI will trigger a non-maskable
interrupt to CPU. This signal requires an external
pull-up resistor tied to 3.3V.

Preliminary V2.0 Nov. 2, 1998 66 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

48 INTR OD

46 IGNE# OD

43 FERR# I

44 STPCLK# OD

49 SMI# OD

50 CPURST OD

45 INIT OD

51 A20M# OD

Interrupt Request:

At high-level voltage on this signal indicates to the
CPU that there is outstanding interrupt(s) need to be
serviced. This signal requires an external pull-up
resistor tied to 3.3V.

Ignore Error:

IGNE# is asserted to inform CPU to ignore a numeric
error. This signal requires an external pull-up resistor
tied to 3.3V.

Floating Point Error:

CPU will assert this signal upon a floating point error
occurs.

Stop Clock:

STPCLK# will be asserted to inhibit or throttle CPU
activities upon a pre-defined power management
event occurs. It requires an external pull-up resistor
tied to 3.3V.

System Management Interrupt:

SMI# will be asserted upon a pre-defined power
management event occurs. It requires an external
pull-up resistor tied to 3.3V.

CPU Reset:

Active high signal to reset CPU. It requires an
external pull-up resistor tied to 3.3V.

Initialization:

INIT is used to re-start the CPU without flushing its
internal caches and registers. In Pentium platform it
is active low, while in Pentium II platform it is active
high. This signal requires an external pull-up resistor
tied to 3.3V.

Address 20 Mask:

When A20M# is asserted, the CPU A20 signal will be
forced to ‘0’. It requires an external pull-up resistor
tied to 3.3V.

Note: “OD” means open drain signal.

4.3 KBC + MISC.

SiS5595
PIN NO.

Preliminary V2.0 Nov. 2, 1998 67 Silicon Integrated Systems Corporation

NAME TYPE

ATTR

DESCRIPTION

SiS5595 PCI System I/O Chipset

31 GPIO2/

KBCLK

33 KBDAT/

IRQ1

32 GPIO1/

PMCLK

34 PMDAT/

IRQ12

General Purpose Input/ Output 2:

I/O

When the internal keyboard controller is disabled,
this pin is used as GPIO2. As input, it can be
configured to generate a SMI#/SCI event, a Wakeup
event or a Standby Timer reload event to the ACPI­compatible power management unit. As output, its
output logic state can be controlled via a register bit.

Keyboard Clock:

When the internal keyboard controller is enabled,
this pin is used as the keyboard clock signal.

Keyboard Dada:

I/O

When the internal keyboard controller is enabled,
this pin is used as the keyboard data signal.

IRQ1:

When the internal keyboard controller is disabled,
this pin is used as the IRQ1 signal.

General Purpose Input/ Output 1:

I/O

When the internal PS2 mouse controller is disabled,
this pin is used as GPIO1. As input, it can be
configured to generate a SMI#/SCI event, a Wakeup
event or a Standby Timer reload event to the ACPI­compatible power management unit. As output, its
output logic state can be controlled via a register bit.

PS2 Mouse Clock:

When the internal keyboard and PS2 mouse
controllers are enabled, this pin is used as the PS2
mouse clock signal.

PS2 Mouse Data:

I/O

When the internal keyboard and PS2 mouse
controllers are enabled, this pin is used as PS2
mouse data signal.

Interrupt Request 12:

When the internal PS2 mouse controller is disabled,
this pin is used as the IRQ12 signal.

Preliminary V2.0 Nov. 2, 1998 68 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

128 GPIO3/

CPU_STOP#
/ SLP#

53 GPIO0/PAR I/O

40 GPIO9/

THERM#/
BTI/

SMBALERT#

I/O

I/O

General Purpose Input/ Output 3:

As input, GPIO3 can be configured to generate a
SMI#/SCI event, a Wakeup event or a Standby
Timer reload event to the ACPI-compatible power
management unit. As output, its output logic state
can be controlled via a register bit.

CPU_STOP#: (For Pentium platform)

It is asserted to inform the system Clock Generator
chip to stop the CPU and SDRAM clock outputs as
well as to disconnect ISA bus from power supply, as
defined in the power management S2 state.

SLP#: (For Pentium-II platform)

It is asserted to put the Pentium II processor into
SLEEP state.

General Purpose Input/ Output 0:

As input, GPIO0 can be configured to generate a
SMI#/SCI event, a Wakeup event or a Standby
Timer reload event to the ACPI-compatible power
management unit. As output, its output logic state
can be controlled via a register bit.

PCI Parity:

SiS5595 always generates even-parity on PAR and
ignores the parity driven by other PCI agents.

General Purpose Input/ Output 9:

As input, GPIO9 can be configured to generate a
SMI#/SCI event, a Wakeup event or a Standby
Timer reload event to the ACPI-compatible power
management unit. As output, its output logic state
can be controlled via a register bit.

Thermal Detect:

THERM# is connected to the internal ACPI­compatible power management unit as an indication
of outstanding thermal event. In response, the
STPCLK# signal will be asserted to throttle CPU
activities.

Board Temperature Interrupt:

BTI is connected to the internal Data Acquisition
Module for interrupt or SMI# generation. It is driven
by temperature monitoring chips located on the
motherboard.

SMBUS Alert Interrupt:

The SMBALERT# is an interrupt signal for SMBUS
device to notify the host it wants to talk.

Preliminary V2.0 Nov. 2, 1998 69 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

127 BM_REQ# I

55 GPCS0# I/O

52 GPCS1#/

KLOCK#

54 GPIO17/

SIRQ

I/O

I/O

Bus Mater Request:

This is a serial link from SiS North Bridge chipset
carrying the current AGP and PCI bus master
information to SiS5595 for power management
purpose. Two types of events are defined and can
be enabled as a wakeup or reload event to the
power management unit:

Event 1: AGP activity
Event 2: AGP/PCI/IDE master requesting for PCI bus
Event 1 can be sampled by SiS55595 at the

1,3,5…Nth PCI clock after FRAME# asserted. Event
2 can be sampled at the 2,4,6…Nth PCI clock after
FRAME# asserted.

General Programmable Chip Select 0:

This pin can be programmed through Reg_73h/PMU
as one of the GPI, GPO, GPCS# or GPCSW#
functions:

1) GPI: can be used to generate a reload, wakeup or
SMI event

2) GPO: its output logic state can be controlled via a
register bit.

3) GPCS#: active-low output can be used as a chip
select signal.

4) GPCSW#: similar to GPCS#, the GPCS with Write
function further qualifies the IOWC# signal so that it
can be used to control an external 8-bit latch
connected to SD[7:0], thereby expanding the number
of general purpose outputs up to 8.

General Programmable Chip Select 1:

Refer to GPCS0#.

Keyboard Lock:

When KLOCK# is tied low, the internal keyboard
controller will not respond to any key-strikes.

General Purpose Input/ Output 17:

As input, GPIO17 can be configured to generate a
SMI#/SCI event, a Wakeup event or a Standby
Timer reload event to the ACPI-compatible power
management unit. As output, its output logic state
can be controlled via a register bit.

Serial IRQ:

This signal is used as the Serial IRQ line signal.

Preliminary V2.0 Nov. 2, 1998 70 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

129 EXTSMI# I

35 CLK14M I

36 ROMKBCS# O

37 SPKR O

41 DDCDAT OD

42 DDCCLK OD

122 GPIO7/

OC0#/
PPS

124 GPIO8/

OC1#

I/O

I/O

External SMI#:

EXTSMI# can be configured to generate a SMI#/SCI
event, a Wakeup event or a Standby Timer reload
event to the ACPI-compatible power management
unit.

14.318 MHz clock input:

This signal provides the fundamental clock for the
8254-compatible timer, PMU System Standby Timer,
ACPI Timer and BCLK.

Keyboard or System ROM Chip Select:

ROMKBCS# will be asserted during external
keyboard controller or ROM access cycles.

Speaker output:

The SPKR is connected to the system speaker.

SMBus/I2C Bus Data:

An external pull-up resister tied to 3.3V is required.

SMBus/I2C Bus Clock:

An external pull-up resister tied to 3.3V is required.

General Purpose Input/Output 7:

As input, GPIO7 can be configured to generate a
SMI#/SCI event, a Wakeup event or a Standby
Timer reload event to the ACPI-compatible power
management unit. As output, its output logic state
can be controlled via a register bit.

USB Over Current Detection:

OC0# is used to detect the over current condition.

USB Power Switch:

PPS function is used to control the external Power­Distribution Switches logic to power off the USB
power supply lines.

General Purpose Input/Output 8:

As input, GPIO8 can be configured to generate a
SMI#/SCI event, a Wakeup event or a Standby
Timer reload event to the ACPI-compatible power
management unit. As output, its output logic state
can be controlled via a register bit.

USB Over Current Detection:

OC1# is used to detect the over current condition.

Preliminary V2.0 Nov. 2, 1998 71 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

38 GPIO4/

FAN1

39 GPIO11/

FAN2

1 GPIO16/

IOCHK#

General Purpose Input/Output 4:

I/O

As input, GPIO4 can be configured to generate a
SMI#/SCI event, a Wakeup event or a Standby
Timer reload event to the ACPI-compatible power
management unit. As output, its output logic state
can be controlled via a register bit.

Fan Tachometer Input 1:

It is driven from the fan’s tachometer output and is
connected to the internal Data Acquisition Module for
fan speed monitoring.

General Purpose Input/Output 11:

I/O

As input, GPIO11 can be configured to generate a
SMI#/SCI event, a Wakeup event or a Standby
Timer reload event to the ACPI-compatible power
management unit. As output, its output logic state
can be controlled via a register bit.

Fan Tachometer Input 2:

It is driven from the fan’s tachometer output and is
connected to the internal Data Acquisition Module for
fan speed monitoring.

General Purpose Input/Output 16:

I/O

As input, GPIO16 can be configured to generate a
SMI#/SCI event, a Wakeup event or a Standby
Timer reload event to the ACPI-compatible power
management unit. As output, its output logic state
can be controlled via a register bit.

I/O Channel Check:

IOCHK# can be issued by ISA devices to indicate an
error event. In response, SiS5595 will assert the NMI
if enabled.

Note: “OD” means open drain signal.

4.4 USB CONTROLLER

SiS5595
PIN NO.

115
116
117
118
120 UCLK48M I

Preliminary V2.0 Nov. 2, 1998 72 Silicon Integrated Systems Corporation

NAME TYPE

UV0+,
UV0­UV1+,
UV1-

ATTR

I/O

I/O

DESCRIPTION

USB Data port 0:

Used as the differential USB data bus pair of port 0.

USB Data port 1:

Used as the differential USB data bus pair of port 1.

48 MHz USB Clock Input .

SiS5595 PCI System I/O Chipset

4.5 RTC

SiS5595
PIN NO.

21 OSC32KHI/

20 OSC32KH

18 PWRGD I

23 PSRSTB# I

25 PS_ON#/

NAME TYPE

ATTR

IRQ8#

O/RTCCS#

OD

RTCALE

32.768 KHz Input:

I

When internal RTC is enabled, this pin provides the

32.768 KHz clock signal from external crystal or
oscillator.

Interrupt Request 8:

When external RTC is enabled, this pin is used as
IRQ8#.

32.768 KHz Output:

O

When internal RTC is enabled, this pin should be
connected the other end of the 32.768 KHz crystal or
left unconnected if an oscillator is used.

RTC Chip Select:

When external RTC is enabled, this pin is used as
the chip select signal for the external RTC.

Power Good:

A high-level input to this signal indicates the power
being supplied to the system is in stable operating
state. During the period of PWRGD being low,
CPURST and PCIRST# will all be asserted until after
PWRGD goes to high for 1~2 ms.

RTC Power Strobe:

When the internal RTC is enabled, this signal is used
as the power strobe signal to initialize RTC internal
registers when power is first applied to the system. If
the internal RTC is disabled, this signal should be
tied low.

ATX Power ON/OFF control:

PS_ON# is internally powered by RTCVDD and is
used to control the on/off state of the ATX power
supply. When the ATX power supply is in the OFF
state, several power management events can be
defined to generate a low output on this signal and
hence switch the power supply to ON state. These
events are PWRBT #, RING, PME0 #, PME1 #, RTC
alarm, keyboard password matched and hotkey
being pressed.

RTC Address Latch Enabled:

When external RTC is used, this signal can be used
to latch the address of RTC internal register being
accessed on the ISA SD [7:0] data bus.

DESCRIPTION

Preliminary V2.0 Nov. 2, 1998 73 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

29 GPIO5/

PME0#/
DUAL_ON#

28 GPO6/

CKE_S/
ACPILED

27 GPIO10/

PME1#/
ACPILED

General Purpose Input/Output 5:

I/O

When the system is in power-on mode, this pin is
GPIO5. As input, GPIO5 can be configured to
generate a SMI#/SCI event, a Wakeup event or a
Standby Timer reload event to the ACPI-compatible
power management unit. As output, its output logic
state can be controlled via a register bit.

PME0#:

When the system is in power-down mode, a high-to­low transition on PME0# will cause the PS_ON# to
go low and hence turn on the power supply.

Dual Power On/Off Control:

When the system is in suspend mode, the
DUAL_ON# signal can be used to control PC98­compatible power supply.

General Purpose Output 6:

O

The logic state of GPO6 can be controlled via a
register bit located at the internal Automatic Power
Control (APC) unit.

SDRAM Clock Enable:

When the system is in suspending mode (suspend to
DRAM), the CKE_S is driven low to enable the self­refresh mode of SDRAM.

ACPILED:

ACPILED can be used to control the blinking of an
LED at the frequency of 1 Hz to indicate the system
is at power saving mode.

General Purpose Input/Output 10:

I/O

When the system is in power-on mode, this pin is
GPIO10. As input, GPIO10 can be configured to
generate a SMI#/SCI event, a Wakeup event or a
Standby Timer reload event to the ACPI-compatible
power management unit. As output, its output logic
state can be controlled via a register bit.

PME1#:

When the system is in power-down mode, a low
pulse over 30 us on PME1# will cause the PS_ON#
to go low and hence turn on the power supply.

ACPI LED:

Refer to Pin 28.

Preliminary V2.0 Nov. 2, 1998 74 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

24 RING I

26 PWRBT# I

4.6 DATA ACQUISITION INTERFACE

SiS5595
PIN NO.

13,14,15,16 GPI[15:12]/

10 DXP/VIN4 A

11 DXN A

NAME TYPE

ATTR

VIN[3:0]

Ring In:

RING is connected to the internal Automatic Power
Control (APC) unit and the ACPI-compatible power
management unit (PMU). For the APC part, a 4ms
active pulse detected on RING will cause the
PS_ON# signal to go low and hence turn on the
power supply. For the PMU part, it can be configured
to generate a SMI#/SCI event, a wake up event or a
system standby timer reload event.

Power Button:

This signal is from the power button switch and will
be monitored by the ACPI-compatible power
management unit to switch the system between
working and sleeping states.

General Purpose Input [15:12]:

I

GPI [15:12] each can be configured to generate a
SMI#/SCI event, a Wakeup event or a Standby
Timer reload event to the ACPI-compatible power
management unit.

VIN [3:0]:

VIN [3:0] are connected to the Data Acquisition
Module for system supplied voltages monitoring.
They also can be served as temperture detection by
connecting to one external thermister.

DXP:

When the transistor 2N3904 is employed as
temperature sensor, this pin should be connected to
the base and collector of 2N3904.

When thermister sensor is used, this pin should be
connected to the one end of the thermister. The
other end of the thermister should be connected to
AGND (pin 17).

VIN4:

VIN4 are connected to the Data Acquisition Module
for system supplied voltages monitoring.

DXN:

For 2N3904 sensor, this pin should be tied to emitter
of the transistor.

For thermister sensor, this pin should be connected
to VSS.

DESCRIPTION

Preliminary V2.0 Nov. 2, 1998 75 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

Note: “A” means Analog signal.

4.7 POWER PINS

SiS5595
PIN NO.

119 USBVDD PWR
114 USBVSS PWR
22 RTCVDD PWR
19 RTCVSS PWR
12 AVDD PWR
17 DVSS PWR
30 KBVDD PWR

62, 81, 104,
168

64, 73, 85,
99,109,150,
188

88,121, 174 DVDD PWR
90,123, 172 DVSS PWR

NAME TYPE

ATTR

OVDD PWR

OVSS PWR

DESCRIPTION

+3.3V DC Power for USB circuit.
Ground pin for USB circuit
Power pin for internal RTC and APC.
Ground pin for internal RTC and APC
5V DC power for the Data Acquisition circuitry.
Ground pin for the Data Acquisition circuitry.
Keyboard Controller Power Input.

If keyboard password security or hot key power-up
function is enabled, the KBVDD should be connected
to AUX-5V of the ATX power supply. The system
designers are advised to ensure the power supply in
use will provide enough current on the AUX-5V line
to the keyboard in order for these functions to work
successfully. Typically, a keyboard will consume up
to 200~300mA of current and the actual values may
be varied for different keyboard manufacturers.

+5V DC I/O PAD power.

Ground pin for I/O DC PAD power.

+5V DC main power supply.
Ground pin for main voltage supply.

Preliminary V2.0 Nov. 2, 1998 76 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

5 HARDWARE TRAP

The ROMKBCS#, PSRSTB# and PHLDA# pins can be used to configure SiS5595 during
system boot-up. The SiS5595's operating mode will be determined by the voltage-level being
applied to these pins when the PWRGD signal is going from low to high, known as Hardware
Trap. A logic “1” will be recognized and trapped into internal control circuitry if an external
pull-up resistor is connected to the trap pin, while a logic “0” will be trapped if a pull-down
resistor is connected. The PHLDA# is driven high by North Bridge when North Bridge is 530
during the rising edge of PWRGD, but a low is driven by 5600/620 (North Bridge) instead.
The PHLDA# is also used as a selection for Pentiumn II processor core frequency
configuration during the falling edge of CPURST.

SiS5595
PIN NO.

36 ROMKBCS#

23 PSRSTB#

125 PHLDA#

For Pentium-II platform, there are four output pins of SiS5595--A20M#, INTR, IGNE# and
NMI, are used to provide core operating frequency information to the CPU when CPURST is
going from high to low. To achive this, the other four pins BM_REQ#, GPCS0#, PHOLD#
and PHLDA# are used for A20M#, INTR, IGNE# and NMI trapping control. The trapping
circuit is active when CPURST is high and till 7 PCI clocks later after CPURST goes from
high-to-low. The PHOLD# and GPCS0# pins will be forced to input mode during this period,
while BM_REQ# and PHLDA# are input only.

SYMBOL

DESCRIPTION

Enable/Disable Internal PCI Clock DLL Circuitry to
Improve Timing

Pull-up: Disable
Pull-down: Enable

Enable/Disable the Built-in RTC

Pull-up: Use Internal RTC.
Pull-down: Use External RTC

CPURST and INIT active level selection

Driven-high: Both are high level active, for Pentiumn

processor
Driven-low: Both are low level active, for Pentiumn II
processor

The 5595B also provides another method to control A20M#, INTR, IGNE# and NMI. It
employed the APC register 08h, bit 7~4 to control these four pins. The APC register 08h, bit
3 is utilized to determine which method is applied. The APC Reg. 08h will be cleared to
default value if the BIOS is unable to set the PMU Reg. 4Ch, bit 0 to ‘1’ in 4.68 seconds after
CPURST deassertion.

Preliminary V2.0 Nov. 2, 1998 77 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

Method I: APC Reg. 08h, bit 3 is set to 0

SiS5595
PIN NO.

127 BM_REQ#

55 GPCS0#
113 PHOLD#
125 PHLDA#

Method II: APC Reg. 08h, bit 3 is set to 1

PIN NAME DESCRIPTION

Routed to A20M# for Pentium-II Core Frequency Selection
Routed to INTR for Pentium-II Core Frequency Selection
Routed to IGNE# for Pentium-II Core Frequency Selection
Routed to NMI for Pentium-II Core Frequency Selection

Bit# of APC

Reg. 08h

5
6
4
7

BM_REO#

PHOLD#
PHLDA#

GPCS0#

A20M#

IGNE#

NMI

INTR

APC

REG08.

7~4

DESCRIPTION

Routed to A20M# for Pentium-II Core Frequency Selection
Routed to INTR for Pentium-II Core Frequency Selection
Routed to IGNE# for Pentium-II Core Frequency Selection
Routed to NMI for Pentium-II Core Frequency Selection

vcc

R

R

MUX

Pentium II Processor

GND

CPURST

APC REG08.3

Figure 5-1 Block Diagram for Generating Core Frequency

Preliminary V2.0 Nov. 2, 1998 78 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

6 REGISTER SUMMARY

6.1 PCI TO ISA BRIDGE CONFIGURATION REGISTERS
ADDRESS ACCESS REGISTER NAME

00-01h RO Vendor ID
02-03h RO Device ID
04-05h R/W Command Register
06-07h R/W Status register

08h RO Revision ID

09-0Bh RO Class Code

0Ch RO Cache Line Size
0Dh R/W Master Latency Timer
0Eh RO Header Type
0Fh RO Built-in Self Test

10-3Ch RO - Reserved

40h R/W BIOS Control Register

41-44h R/W PCI INTA#/B#/C#/D# Remapping Register

45h-46h R/W ISA Bus Control Register I, II

47h R/W DMA Clock and Wait State Control Register
48h R/W ISA to PCI Top of Memory Region Register

49h R/W ISA to PCI Memory Region Enable Register
4Ah R/W ISA to PCI Memory Hole Bottom Address Register
4Bh R/W ISA to PCI Memory Hole Top Address Register

4C-4Fh RO Shadow Register of ICW1 to ICW4 of the INT1

50-53h RO Shadow Register of ICW1 to ICW4 of the INT2
54-55h RO Shadow Register of OCW 2&3 of INT1
56-57h RO Shadow Register of OCW 2&3 of the INT2

58h-5Fh RO CTC Shadow Registers 1 to 8

60h RO Shadow Register for ISA Port 70

61h R/W IDEIRQ Remapping Register

62h R/W USBIRQ Remapping Register

63h R/W PCI Output Buffer Current Strength Register

64h R/W INIT Enable Register

65h R/W PHOLD# Timer

66h R/W Priority Timer

67h R/W Respond to C/D Segment

68-69h R/W Data Acquisition Module Base Address Register

6Ah R/W ACPI/SCI IRQ Remapping Register

6B-6Ch R/W Test Mode Register I, II

Preliminary V2.0 Nov. 2, 1998 79 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

6Dh R/W I2C Bus Control Register

6E-6Fh R/W Software-Controlled Interrupt Requests

70h R/W Misc. Control Register

71h R/W - Reserved

72h R/W Individual PC/PCI DMA Channel Enable Register

74-79h R/W - Reserved

7Ah R/W Data Acquisition Module Function Selection Register
7Bh R/W Data Acquisition Module Control Register

7C-7Dh R/W Data Acquisition Module ADC Calibration Register

7Eh R/W Data Acquisition Module IRQ Remapping Register
7Fh RO - Reserved

80-81h R/W Distributed DMA Master Configuration Register
82-83h RO - Reserved

84h R/W Individual Distributed DMA Channel Enable Register

85-87h RO - Reserved

88h R/W Serial Interrupt Control Register

89-8Ah R/W Serial Interrupt Request Enable Register 1,2

8Bh RO - Reserved
8Ch R/W Serial Interrupt Request Enable Register 3

8D-8Fh RO - Reserved

90-91h R/W ACPI Base Address Register

6.2 LEGACY ISA REGISTERS

6.2.1 DMA REGISTERS

(These registers can be accessed from PCI bus and ISA bus)

ADDRESS ACCESS REGISTER NAME

0000h R/W DMA1 CH0 Base and Current Address Register
0001h R/W DMA1 CH0 Base and Current Count Register
0002h R/W DMA1 CH1 Base and Current Address Register
0003h R/W DMA1 CH1 Base and Current Count Register
0004h R/W DMA1 CH2 Base and Current Address Register
0005h R/W DMA1 CH2 Base and Current Count Register
0006h R/W DMA1 CH3 Base and Current Address Register
0007h R/W DMA1 CH3 Base and Current Count Register
0008h R/W DMA1 Status(r) Command(w) Register

0009h R/W DMA1 Request Register
000Ah R/W DMA1 Command(r) Write Single Mask Bit (w) Register
000Bh R/W DMA1 Mode DMA Register
000Ch WO DMA1 Clear Byte Pointer

Preliminary V2.0 Nov. 2, 1998 80 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

000Dh WO DMA1 Master Clear
000Eh WO DMA1 Clear Mask Register
000Fh R/W DMA1 Write All Mask Bits(w) Mask Status(r) Register
00C0h R/W DMA2 CH0 Base and Current Address Register
00C2h R/W DMA2 CH0 Base and Current Count Register
00C4h R/W DMA2 CH1 Base and Current Address Register
00C6h R/W DMA2 CH1 Base and Current Count Register
00C8h R/W DMA2 CH2 Base and Current Address Register

00CAh R/W DMA2 CH2 Base and Current Count Register
00CCh R/W DMA2 CH3 Base and Current Address Register
00CEh R/W DMA2 CH3 Base and Current Count Register

00D0h R/W DMA2 Status(r) Command(w) Register
00D2h R/W DMA2 Request Register
00D4h R/W DMA2 Command(r) Write Single Mask Bit(w) Register
00D6h R/W DMA2 Mode Register
00D8h WO DMA2 Clear Byte Pointer

00DAh WO DMA2 Master Clear
00DCh WO DMA2 Clear Mask Register
00DEh R/W DMA2 Write All Mask Bits(w) Mask Status Register(r)

(These registers can be accessed from PCI bus or ISA bus)

ADDRESS ACCESS REGISTER NAME

0080h R/W Reserved

0081h R/W DMA Channel 2 Low Page Register

0082h R/W DMA Channel 3 Low Page Register

0083h R/W DMA Channel 1 Low Page Register

0084h R/W Reserved

0085h R/W Reserved

0086h R/W Reserved

0087h R/W DMA Channel 0 Low Page Register

0088h R/W Reserved

0089h R/W DMA Channel 6 Low Page Register
008Ah R/W DMA Channel 7 Low Page Register
008Bh R/W DMA Channel 5 Low Page Register
008Ch R/W Reserved
008Dh R/W Reserved
008Eh R/W Reserved
008Fh R/W Refresh Low Page Register

Preliminary V2.0 Nov. 2, 1998 81 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

(These registers can be accessed from PCI bus or ISA bus)

ADDRESS ACCESS REGISTER NAME

00480h R/W Reserved
00481h R/W DMA Channel 2 High Page Register
00482h R/W DMA Channel 3 High Page Register
00483h R/W DMA Channel 1 High Page Register
00484h R/W Reserved
00485h R/W Reserved
00486h R/W Reserved
00487h R/W DMA Channel 0 High Page Register
00488h R/W Reserved

00489h R/W DMA Channel 6 High Page Register
0048Ah R/W DMA Channel 7 High Page Register
0048Bh R/W DMA Channel 5 High Page Register
0048Ch R/W Reserved
0048Dh R/W Reserved
0048Eh R/W Reserved
0048Fh R/W Reserved

6.2.2 INTERRUPT CONTROLLER REGISTERS

(These registers can be accessed from PCI bus or ISA bus.)

ADDRESS ACCESS REGISTER NAME

0020h R/W INT 1 Base Address Register

0021h R/W INT 1 Mask Register
00A0h R/W INT 2 Base Address Register
00A1h R/W INT 2 Mask Register

6.2.3 TIMER REGISTERS

(These registers can be accessed from PCI bus or ISA bus.)

ADDRESS ACCESS REGISTER NAME

0040h R/W Interval Timer 1 - Counter 0

0041h R/W Interval Timer 1 - Counter 1

0042h R/W Interval Timer 1 - Counter 2

0043h WO Interval Timer 1 - Control Word Register

6.2.4 OTHER REGISTERS
(These registers can be accessed from PCI bus or ISA bus.)

ADDRESS ACCESS REGISTER NAME

0061h R/W NMI Status Register

0070h WO CMOS RAM Address and NMI Mask Register

Preliminary V2.0 Nov. 2, 1998 82 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

00F0h WO Coprocessor Error Register
04D0h R/W IRQ Edge/Level Control Register 1
04D1h R/W IRQ Edge/Level Control Register 2

6.3 PMU CONFIGURATION REGISTERS
ADDRESS ACCESS REGISTER NAME

40h ~ 43h R/W System Standby Timer 0 Reload Event
44h ~ 47h R/W System Standby Timer 1 Reload Event
48h ~ 4Bh R/W System Standby Timer 2 Reload Event

4Ch ~ 4Dh R/W Sound Port Trap and Address Mask for

Programmable 16-bit I/O
4Eh ~ 4Fh R/W Linear Frame Buffer Trap
50h ~ 53h R/W Wake-up 0
54h ~ 57h R/W Wake-up 1
58h ~ 5Bh R/W Reserved

5Ch ~ 5Dh R/W Programmable 10-bit I/O

5Eh ~ 5Fh R/W Programmable 16-bit I/O
60h ~ 63h R/W SMI# Enable
64h ~ 67h R/W SMI#/SCI Request Status
68h ~ 69h R/W IRQ and NMI Enable for Wake-up0 and System

Standby Timer 0

6Ah ~ 6Bh R/W IRQ and NMI Enable for Wake-up1 and System

Standby Timer 1

6Ch ~ 6Dh R/W IRQ and NMI Enable for System Standby Timer 2

6Eh ~ 6Fh R/W Reserved

70h ~ 71h R/W GPCS0# Base Address

72h R/W GPCS0# Address Mask
73h R/W GPCS0# Control

74h ~ 75h R/W GPCS1# Base Address

76h R/W GPCS1# Address Mask
77h R/W GPCS1# Control
78h R/W GPCS0# and GPCS1# De-bounce Counter and

GPCS0# Address A[11:8] Mask

79h R/W System Standby Timer 0
7Ah R/W System Standby Timer 1
7Bh R/W System Standby Timer 2
7Ch R/W System Standby Timer Granularity
7Dh R/W Auto Power Off Timer and PMU Test Mode

7Eh ~ 7Fh R/W IDE Bus Master Port Trap

80h ~ 83h R/W SCI Enable

Preliminary V2.0 Nov. 2, 1998 83 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

6.4 ACPI CONFIGURATION REGISTERS
OFFSET BYTE

LENGTH

00 2 R/W PM1 Status PM1_STS Fixed Features
02 2 R/W PM1 Enable PM1_EN Fixed Features
04 2 R/W PM1 Control PM1_CTL Fixed Features
06 2 R/W Reserved Fixed Features
08 4 R/W PM Timer PM_TMR Fixed Features
0C 4 R/W CPU Control P_CTL Fixed Features
10 1 RO CPU Power State

11 1 RO CPU Power State

12 1 R/W PM2 Control PM2_CTL Fixed Features
13 1 R/W Fixed Features

14 4 R/W GPE Status GPE_STS Generic Features
18 4 R/W GPE Enable GPE_EN Generic Features
1C 3 R/W GPE Pin Status GPE_Pin Generic Features
1F 1 R/W GP Timer GP_TMR Generic Features
20 4 R/W GPE I/O Selection GPE_IO Generic Features
24 4 R/W GPE Polarity

28 2 R/W GPE Multi-definition

2A 2 R/W GPE Control GPE_CTL Generic Features
2C 2 R/W GPIO Events SMI#

2E 2 R/W GPIO Events Stop

30 1 R/W Legacy Status LEG_STS Legacy
31 1 R/W Legacy Enable LEG_EN Legacy
32 1 R/O Reserved
33 1 R/W Test Control TST_CTL Legacy
34 1 R/W Reserved
35 1 R/W SMI# Command

36 1 R/W Free Read/Write

37 1 R/O Reserved

ACCESS NAME ABBREVIATE CLASS

P_LVL2 Fixed Features

Level 2

P_LVL3 Fixed Features

Level 3

FIX_CTL Fixed Features

Control

GPE_Pol Generic Features

Selection

GPE_Mul Generic Features

Pins Selection

GPE_SMI Generic Features

Enable

GPE_RL Generic Features
GPTMR and Reload
PMU Timers Enable

SMI_CMD Legacy
Port

Free_Byte Legacy
Byte

Preliminary V2.0 Nov. 2, 1998 84 Silicon Integrated Systems Corporation

SiS5595 PCI System I/O Chipset

38 1 R/W SMBus IO Index SMB_INDEX SMBus
39 1 R/W SMBus IO Data SMB_DAT SMBus

Note: ALL ACPI registers can be accessed by byte, word, or D-word in length.

6.5 SMBUS IO REGISTERS
OFFSET BYTE

LENGTH

00~01 2 R/W SMBus Host Status SMB_STS
02~03 2 R/W SMBus Host Control SMB_CTL

04 1 R/W SMBus Address

05 1 R/W SMBus Command

06 1 RO SMBus Data

07 1 R/W SMBus Data Byte

08 1 R/W SMBus Data Byte 0 SMB_BYTE0
09 1 R/W SMBus Data Byte 1 SMB_BYTE1
0A 1 R/W SMBus Data Byte 2 SMB_BYTE2
0B 1 R/W SMBus Data Byte 3 SMB_BYTE3
0C 1 R/W SMBus Data Byte 4 SMB_BYTE4
0D 1 R/W SMBus Data Byte 5 SMB_BYTE5
0E 1 R/W SMBus Data Byte 6 SMB_BYTE6
0F 1 R/W SMBus Data Byte 7 SMB_BYTE7
10 1 R/W SMBus Device

11 1 R/W SMBus Device

12 1 R/W SMBus Device

13 1 R/W SMBus Host Alias

ACCESS NAME ABBREVIATE COMMENT

SMB_ADS

Field

SMB_CMD

Field

SMB_PCNT

Processed Count

SMB_CNT

Count

SMB_DEV Device Master

Address

SMB_DB0 Low Byte

Byte0

SMB_DB1 High Byte

Byte1

SMB_HAA Another Host

Address

Address

Address

6.6 USB OPENHCI HOST CONTROLLER CONFIGURATION SPACE

6.6.1 USB CONFIGURATION SPACE (FUNCTION 2)

CONFIGURATION.

OFFSET

00-01h RO VID Vendor ID
02-03h RO DID Device ID

Preliminary V2.0 Nov. 2, 1998 85 Silicon Integrated Systems Corporation

ACCESS MNEMONIC REGISTER

SiS5595 PCI System I/O Chipset

04-05h R/W CMD Command Register
06-07h R/W STS Status register

08h RO RID Revision ID

09-0Bh RO CD Class Code

0Ch RO CL Cache Line Size
0Dh R/W MLT Master Latency Timer
0Eh RO HT Header Type

0Fh RO BIST Built-in Self Test
10-13h R/W Base address
13-3Bh RO - Reserved

3Ch R/W INTL Interrupt line

3Dh RO INTP Interrupt pin

3Eh RO MINGNT Min Gnt

3Fh RO MAXLAT Max Latency

6.6.2 HOST CONTROLLER OPERATIONAL REGISTERS
OFFSET 3100

0 HcRevision
4 HcControl
8 HcCommandStatus

C HcInterruptStatus
10 HcInterruptEnable
14 HcInterruptDisable
18 HcHCCA

1C HcPeriodCurrentED

20 HcControlHeadED
24 HcControlCurrentED
28 HcBulkHeadED

2C HcBulkCurrentED

30 HcDoneHead
34 HcFmInterval
38 HcFmRemaining

3C HcFmNumber

40 HcPeriodicStart
44 HcLSThreshold
48 HcRhDescriptorA

4C HcRhDescriptorB

50 HcRhStatus
54 HcRhPortStatus[1]

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SiS5595 PCI System I/O Chipset

58 HcRhPortStatus[2]

100 HceControl
104 HceInput
108 HceOutput

10C HceStatus

6.7 AUTOMATIC POWER CONTROL (APC) REGISTERS

(The following register can be accessed when PCI to ISA Register 45, bit 1 is set to 1.)

ADDRESS ACCESS REGISTER NAME

00h RO Reserved
01h RO Reserved
02h R/W APC Register 02h
03h R/W APC Register 03h
04h R/W APC Register 04h
05h R/W APC Register 05h
06h RO APC Register 06h
07h R/W APC Register 07h
08h R/W APC Register 08h

6.7.1 RTC REGISTERS
ADDRESS ACCESS REGISTER NAME

00h R/W Seconds
01h R/W Seconds Alarm
02h R/W Minutes
03h R/W Minutes Alarm
04h R/W Hours
05h R/W Hours Alarm
06h R/W Day of the Week
07h R/W Day of the Month
08h R/W Month

09h R/W Year
0Ah R/W Register A
0Bh R/W Register B ( bit 3 must be set to 0)
0Ch R/W Register C
0Dh R/W Register D
7Eh R/W Day of the Month Alarm

7Fh R/W Month Alarm

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SiS5595 PCI System I/O Chipset

6.8 DATA ACQUISITION MODULE (DAM) INTERNAL REGISTERS
OFFSET REGISTER ACCESS

40h Configuration R/W
41h Interrupt Status I RO
42h Interrupt Status II RO
43h SMI# Mask I R/W
44h SMI# Mask II RO
45h NMI Mask I RO
46h NMI Mask II RO
47h Fan Divisor R/W

48h - Reserved RO
20h/60h VIN0 Reading RO
21h/61h VIN1 Reading RO
22h/62h VIN2 Reading RO
23h/63h VIN3 Reading RO
24h/64h DXP/VIN4 Reading RO

25h~27h/65~67h - Reserved RO

28h/68h Fan 1 Reading RO
29h/69h Fan 2 Reading RO

2Ah/6Ah - Reserved RO
2Bh/6Bh VIN0 High Limit R/W
2Ch/6Ch VIN0 Low Limit R/W
2Dh/6Dh VIN1 High Limit R/W
2Eh/6Eh VIN1 Low Limit R/W
2Fh/6Fh VIN2 High Limit R/W

30h/70h VIN2 Low Limit R/W
31h/71h VIN3 High Limit R/W
32h/72h VIN3 Low Limit R/W
33h/73h DXP/VIN4 High Limit R/W
34h/74h DXP/VIN4 Low Limit R/W

35h~3Ah/75h~7Ah - Reserved R/W

3Bh/7Bh FAN1 fan count limit R/W
3Ch/7Ch FAN2 fan count limit R/W
3Dh/7Dh - Reserved RO

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SiS5595 PCI System I/O Chipset

7 REGISTER DESCRIPTION

7.1 PCI TO ISA BRIDGE CONFIGURATION REGISTERS
DEVICE IDSEL FUNCTION NUMBER

PCI to ISA bridge AD12 0000b

Registers 00h~01hVendor ID

Default Value: 1039h
Access:Read Only

BIT ACCESS DESCRIPTION

15:0 RO

Registers 02h~03hDevice ID

Default Value: 0008h
Access:Read Only

BIT ACCESS DESCRIPTION

15:0 RO

Vendor Identification Number

Default value is 1039h

Device Identification Number

Default value is 0008h

Registers 04h~ 05h Command Register

Default Value: 000Ch
Access:Read/Write, Read Only

BIT ACCESS DESCRIPTION

15:4 RO

3 RO

2 RO

1 R/W

0 R/W

Registers 06h~07hStatus

Default Value: 0200h
Access:Read/Write, Read Only

Preliminary V2.0 Nov. 2, 1998 89 Silicon Integrated Systems Corporation

Reserved.

Read as 0

Read as 1 to indicate the device is allowed to monitor special
cycles.

Read as 1 to indicate the device is able to become PCI bus
master.

Response to Memory Space Accesses (default=0)

This bit should be written to 1 after reset.

Response to I/O Space Accesses (default =0)

This bit should be written to 1 after reset.

SiS5595 PCI System I/O Chipset

BIT ACCESS DESCRIPTION

15:14 RO

13 RO

12 RO

11 RO

10:9 R/W

8:0 RO

Register 08h Revision ID

Default Value: B0h

Reserved.

Read as 0.

Received Master-Abort

This bit will be set to 1 when the current transaction is terminated
with master-abort. This bit can be cleared to 0 by writing a 1.

Received Target-Abort

This bit will be set to 1 when the current transaction is terminated
with target-abort. This bit can be cleared to 0 by writing a 1.

Reserved.

Read as 0.

DEVSEL# Timing

The two bits are hardwired to 01 to indicate positive decode with
medium timing.

Reserved.

Read as 0.

Access:Read Only

BIT ACCESS DESCRIPTION

7:0 RO

Register 09h~0Bh Class Code

Default Value: 060100h
Access:Read Only

BIT ACCESS DESCRIPTION

23:0 RO

Register 0Ch Cache Line Size

Default Value: 00h
Access:Read Only

BIT ACCESS DESCRIPTION

7:0 RO

Register 0Dh Master Latency Timer

Default Value: 00h
Access:Read/Write

Revision Identification Number

Class Code

Default value is 060100h

Cache Line Size

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SiS5595 PCI System I/O Chipset

BIT ACCESS DESCRIPTION

7:0 RO

Register 0Eh Header Type

Default Value: 80h
Access:Read Only

BIT ACCESS DESCRIPTION

7:0 RO

Register 0Fh BIST

Default Value: 00h
Access:Read Only

BIT ACCESS DESCRIPTION

7:0 RO

Master Latency Timer.

Header Type

Default value is 80h

BIST

Default value is 00h

Register 10h~3Ch Reserved. Read as 0.
Register 40h BIOS Control Register

Default Value: 08h
Access:Read/Write

BIT ACCESS DESCRIPTION

7 R/W

6 R/W

5 R/W

4 R/W

ACPI Enable

0 : Disable (default)
1 : Enable

When enabled, ACPI registers located at IO space address as
defined in ACPI Base registers (Reg. 90h~91h) can be
accessed.

PC/PCI DMA ISA Master Retry Mode Selection

When this bit is programmed to 0, the PC/PCI DMA controller will
not release the PCI bus as the PC/PCI DMA ISA Master cycle is
retried. Inversely, the PC/PCI DMA controller will release the PCI
bus.

PCI Delayed Transaction Enable

0 : Disable (default)
1 : Enable

PCI Posted Write Buffer Enable

0 : Disable (default)
1 : Enable

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SiS5595 PCI System I/O Chipset

3 R/W
2 R/W
1 R/W

0 R/W

BITS [3:2] F

SEGMENTESEGMENT

+ - + ­00
10

Others

Note *: Enabled if bit 1 is set.

Register 41h/42h/43h/44h PCI INTA#/B#/C#/D# Remapping Register

Default Value: 80/80/80/80h
Access: Read/Write

BIT ACCESS DESCRIPTION

7 R/W

6:4 RO

3:0 R/W

v

Positive Decode of Upper 64K BYTE BIOS Enable.
BIOS Subtractive Decode Enable.
Lower BIOS Enable.

BIT[3:2] will only be effective when this bit is enabled.

Extended BIOS Enable. (FFF80000~FFFDFFFF)

When enabled, the device will positively respond to PCI cycles
toward the Extended segment.

COMMENT

v*
v*

v

Remapping Enable

0 : Enable
1 : Disable (default)

When enabled, PCI INTA#/B#/C#/D# will be remapped to the
IRQ channel specified below.

Reserved.

Read as 0

IRQx Remapping Table

Bits
0000
0001
0010
0011
0100
0101

IRQx#
Reserved
Reserved
Reserved
IRQ3
IRQ4
IRQ5

Chip positively responds to E segment access.
Chip positively responds to E and F segment

access.
Chip subtractively responds to F segment

access.

Bits
0110
0111
1000
1001
1010
1011

IRQx#
IRQ6
IRQ7
reserved
IRQ9
IRQ10
IRQ11

Bits
1100
1101
1110
1111

IRQx#
IRQ12
reserved
IRQ14
IRQ15

Note: More than one of INT[A:D]# can be remapped to the same IRQ line, but that IRQ line
should be programmed to level-triggered mode in Register 4D0h/4D1h.

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SiS5595 PCI System I/O Chipset

Register 45h ISA Bus Control Register I

Default Value: 00h
Access:Read/Write

BIT ACCESS DESCRIPTION

7:6 R/W

5 R/W

4 R/W

3 R/W

2 R/W

1 R/W

0 R/W

ISA Bus Clock Selection

00: 7.159MHz
01: PCICLK/4
10: PCICLK/3
11:Reserved

Flash EPROM Control bit 0

Refer to bit 2 of this register.

Test bit for internal use only

0 : Normal mode
1 : Test mode

RTC Extended Bank Enable (EXTEND_EN)

0 : Disable
1 : Enable

When this bit is enabled, the upper 128 bytes of RTC SRAM can
be accessed.

Flash EPROM Control Bit 1

If bit 5 or 2 is not set to '1' after CPURST de-asserted, EPROM
can be flashed. Once bit 5 or bit 2 is set to 1, EPROM can only
be flashed when bit 5, 2 = 01

Automatic Power Control Registers (APCREG_EN) Enable

0 : Disable
1 : Enable

When this bit is enable, APC registers can be accessed.

Reserved. This bit must be programmed to 0

Register 46h ISA Bus Control Register II

Default Value: 00h
Access:Read/Write

BIT ACCESS DESCRIPTION

7:6 R/W

Preliminary V2.0 Nov. 2, 1998 93 Silicon Integrated Systems Corporation

16-Bit I/O Cycle Command Recovery Time

00: 5 BUSCLK (default)
01: 4 BUSCLK
10: 3 BUSCLK
11: 2 BUSCLK

SiS5595 PCI System I/O Chipset

5:4 R/W

3 R/W

2:0 R/W

Register 47h DMA Clock and Wait State Control Register

Default Value: 00h
Access:Read/Write

BIT ACCESS DESCRIPTION

7 R/W

6 R/W

5:4 R/W

3:2 R/W

1 R/W
0 R/W

8-Bit I/O Cycle Command Recovery Time

00: 8 BUSCLK (default)
01: 5 BUSCLK
10: 4 BUSCLK
11: 3 BUSCLK

ROM Cycle Wait State Selection

0 : 4 wait states (default)
1 : 1 wait state

Test bit for internal use only

0 : Normal Mode (default)
1 : Test Mode

PC/PCI DMA Function Enable
0 : Disable

1 : Enable

EXTEND DACK# Enable

0 : Disable
1 : Enable (recommended)

When enabled, the assertion time of DACK# will be extended by
1/2 BCLK.

16-Bit DMA Cycle Wait State

00 : 1 DMACLK (default)
01 : 2 DMACLK
10 : 3 DMACLK
11 : 4 DMACLK

8-Bit DMA Cycle Wait State

00 : 1 DMACLK (default)
01 : 2 DMACLK
10 : 3 DMACLK
11 : 4 DMACLK

Reserved.
DMA Clock Selection

0: ISA Bus clock divided by 2 (recommended)
1 : Same as ISA Bus clock

Preliminary V2.0 Nov. 2, 1998 94 Silicon Integrated Systems Corporation