Datasheet SIS402DN Datasheet (Vishay) [ru]

N-Channel 30-V (D-S) MOSFET

SiS402DN

Vishay Siliconix

PRODUCT SUMMARY

VDS (V) R

30

0.006 at V

0.008 at V

(Ω)I

DS(on)

= 10 V 35

GS

= 4.5 V 35

GS

D

(A)

a, g

Qg (Typ.)

12 nC

FEATURES

• Halogen-free According to IEC 61249-2-21
Definition

• TrenchFET

• 100 % R

®

Power MOSFET

Tested

g

• 100 % UIS Tested

PowerPAK® 1212-8

• Compliant to RoHS Directive 2002/95/EC

APPLICATIONS

3.30 mm

D

8

D

7

6

Ordering Information:

S

1

D

D

5

Bottom View

SiS402DN-T1-GE3 (Lead (Pb)-free and Halogen-free)

3.30 mm

S

2

S

3

G

4

• DC/DC Converter

- Notebook

- POL

D

G

S

N-Channel MOSFET

ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted

Parameter Symbol Limit Unit

Drain-Source Voltage V
Gate-Source Voltage V

= 25 °C

T

C

= 70 °C

T

Continuous Drain Current (T

= 150 °C)

J

C

TA = 25 °C

TA = 70 °C
Pulsed Drain Current I
Avalanche Current
Avalanche Energy E

Continuous Source-Drain Diode Current

Maximum Power Dissipation

L = 0.1 mH

T

= 25 °C

C

T

= 25 °C

A

= 25 °C

T

C

T

= 70 °C

C

= 25 °C

T

A

TA = 70 °C
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)

d, e

260

T

DS

GS

I

D

DM

I

AS

AS

I

S

P

D

, T

J

stg

30

± 20

a, g

35

g

35

b, c

19

b, c

15

70
35
61
43

b, c

3.2
52
33

b, c

3.8

b, c

2

- 55 to 150

V

A

mJ

A

W

°C

THERMAL RESISTANCE RATINGS

Parameter Symbol Typical Maximum Unit

Maximum Junction-to-Ambient
Maximum Junction-to-Case (Drain)

Notes:
a. Based on T
b. Surface Mounted on 1" x 1" FR4 board.

= 25 °C.

C

c. t = 10 s.
d. See Solder Profile (www.vishay.com/ppg?73257

copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed

and is not required to ensure adequate bottom side solder interconnection.
e. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.
f. Maximum under Steady State conditions is 81 °C/W.
g. Package limited.

Document Number: 68684
S09-1086-Rev. C, 15-Jun-09

b, f

t ≤ 10 s

Steady State

R

thJA

R

thJC

24 33

1.9 2.4

). The PowerPAK 1212 is a leadless package. The end of the lead terminal is exposed

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°C/W

1

SiS402DN

Vishay Siliconix

SPECIFICATIONS TJ = 25 °C, unless otherwise noted

Parameter Symbol Test Conditions Min. Typ. Max. Unit

Static

V

Drain-Source Breakdown Voltage

V

Temperature Coefficient

DS

V

Temperature Coefficient

GS(th)

Gate-Source Threshold Voltage

Gate-Source Leakage

Zero Gate Voltage Drain Current

On-State Drain Current

a

Drain-Source On-State Resistance

Forward Transconductance

Dynamic

b

a

Input Capacitance

Reverse Transfer Capacitance

Total Gate Charge

Gate-Source Charge

Gate-Drain Charge

Gate Resistance

Tur n -O n De l a y T i m e

Rise Time

Turn-Off Delay Time

Fall Time

Tur n -O n De l a y T i m e

Rise Time

Turn-Off Delay Time

Fall Time

a

V

DS

ΔV

DS/TJ

ΔV

GS(th)/TJ

V

GS(th)

I

GSS

I

DSS

I

V

D(on)

R

DS(on)

g

fs

C

iss

C

oss

C

rss

Q

g

Q

gs

Q

gd

R

g

t

d(on)

t

r

t

d(off)

t

f

t

d(on)

t

r

t

d(off)

t

f

Drain-Source Body Diode Characteristics

Continuous Source-Drain Diode Current

Pulse Diode Forward Current

Body Diode Voltage

Body Diode Reverse Recovery Time

Body Diode Reverse Recovery Charge

Reverse Recovery Fall Time

Reverse Recovery Rise Time

I

S

I

SM

V

SD

t

rr

Q

rr

t

a

t

b

Notes:
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.

V

DS

V

V

DS

V

DS

I

D

I

D

IF = 10 A, dI/dt = 100 A/µs, TJ = 25 °C

= 0 V, ID = 250 µA

GS

VDS = V

V

= 0 V, V

DS

V

= 30 V, V

DS

= 30 V, V

≥ 5 V, V

DS

V

= 10 V, ID = 19 A

GS

V

= 4.5 V, ID = 16.6 A

GS

V

= 15 V, ID = 19 A

DS

= 15 V, V

DS

= 15 V, V

= 15 V, V

V

= 15 V, RL = 1.5 Ω

DD

≅ 10 A, V

V

= 15 V, RL = 1.5 Ω

DD

≅ 10 A, V

TC = 25 °C

IS = 10 A, V

30 V

ID = 250 µA

, ID = 250 µA

GS

= ± 20 V

GS

GS

= 0 V, TJ = 55 °C

GS

= 10 V

GS

1.15 2.2 V

= 0 V

50 A

- 6

24

mV/°C

± 100 nA

1

5

µA

0.0048 0.006

0.0064 0.008

82 S

1700

= 0 V, f = 1 MHz

GS

350

140

= 10 V, ID = 19 A

GS

= 4.5 V, ID = 19 A

GS

28 42

12 21

5.4

nC

4.6

f = 1 MHz 1.2 2.4 Ω

25 40

20 30

= 4.5 V, Rg = 1 Ω

GEN

25 40

15 25

12 20

10 15

= 10 V, Rg = 1 Ω

GEN

25 40

10 15

30

70

GS

= 0 V

0.8 1.2 V

25 50 ns

17 35 nC

13

12

Ω

pFOutput Capacitance

ns

A

ns

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

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Document Number: 68684

S09-1086-Rev. C, 15-Jun-09

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

SiS402DN

Vishay Siliconix

70

60

50

40

30

- Drain Current (A)I

D

20

10

0

0.0 0.5 1.0 1.5 2.0 2.5 3.0

VGS=10V thru 4 V

- Drain-to-Source Voltage (V)

V

DS

Output Characteristics

0.010

0.008

VGS=4.5V

0.006

- On-Resistance (Ω)R

DS(on)

0.004

0.002
0 10203040506070

VGS=10V

VGS=3V

VGS=2V

10

TC= - 55 °C

8

6

4

- Drain Current (A)I

D

2

0

0.0 0.5 1.0 1.5 2.0 2.5 3.0

TC= 125 °C

- Gate-to-Source Voltage (V)

V

GS

TC= 25 °C

Transfer Characteristics

2100

1800

1500

1200

900

C - Capacitance (pF)

600

300

C

0

0 5 10 15 20 25 30

C

iss

C

oss

rss

On-Resistance vs. Drain Current and Gate Voltage

10

ID= 19 A

8

6

4

- Gate-to-Source Voltage (V)

GS

2

V

0

061218 24 30

Document Number: 68684
S09-1086-Rev. C, 15-Jun-09

ID- Drain Current (A)

VDS=15V

VDS=24V

Qg- Total Gate Charge (nC)

Gate Charge

VDS- Drain-to-Source Voltage (V)

Capacitance

1.8

ID=19 A

1.6

1.4
VGS=10V,4.5V

1.2

- On-Resistance
(Normalized)

1.0

DS(on)

R

0.8

0.6

- 50 - 25 0 25 50 75 100 125 150

-Junction Temperature (°C)

T

J

On-Resistance vs. Junction Temperature

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SiS402DN

Vishay Siliconix

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

- On-Resistance (Ω)R

DS(on)

0.015

ID=19 A

0.012

0.009

0.006

0.003

0.000

02468 10

VGS- Gate-to-Source Voltage (V)

TJ= 125 °C

TJ= 25 °C

On-Resistance vs. Gate-to-Source Voltage

50

40

30

100

10

- Source Current (A)I

S

1

0.0 0.2 0.4 0.6 0.8 1.0 1.2

TJ= 150 °C

V

-Source-to-Drain Voltage (V)

SD

TJ= 25 °C

Source-Drain Diode Forward Voltage

2.4

2.2

2.0

(V)V

1.8

ID= 250 µA

GS(th)

1.6

1.4

1.2

1.0

- 50 - 25 0 25 50 75 100 125 150

TJ- Temperature (°C)

Threshold Voltage

100

Limited byR

10

- Drain Current (A)I

D

0.1

0.01

Power (W)

20

10

0

0.01

0.1 10 100

Single Pulse Power (Junction-to-Ambient)

IDMLimited

*

DS(on)

I

D(on)

Limited

1

TA= 25 °C

Single Pulse

0.1 1 10 100

VDS- Drain-to-Source Voltage (V)

> minimum VGSat which R

* V

GS

BVDSS
Limited

DS(on)

100 µs

1ms

10 ms

100 ms

1s
10 s

DC

is specified

Safe Operating Area, Junction-to-Ambient

1

Time (s)

600

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Document Number: 68684

S09-1086-Rev. C, 15-Jun-09

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

SiS402DN

Vishay Siliconix

80

60

- Drain Current (A)
I

40

D

20

Package Limited

0

0 255075100125150

TC- Case Temperature (°C)

Current Derating*

* The power dissipation PD is based on T
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package

= 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper

J(max)

60

50

40

30

Power (W)

20

10

0

25 50 75 100 125 150

- Case Temperature (°C)

T

C

Power Derating

limit.

Document Number: 68684
S09-1086-Rev. C, 15-Jun-09

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SiS402DN

Vishay Siliconix

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

2

1

Duty Cycle = 0.5

0.1

Thermal Impedance

Normalized Effective Transient

0.01

0.1

Thermal Impedance

Normalized Effective Transient

0.2

0.1

0.05

0.02

-4

10

2

1

Duty Cycle = 0.5

0.2

0.1

Single Pulse

0.05

0.02

-3

10

Single Pulse

Notes:

P

DM

1. Duty Cycle, D =

2. Per Unit Base = R

3. T

JM

4. Surface Mounted

-2

10

-1

1 10 60010

Square Wave Pulse Duration (s)

Normalized Thermal Transient Impedance, Junction-to-Ambient

t

1

t

2

- TA = PDMZ

thJA

thJA

100

t

1

t

2

= 65 °C/W

(t)

0.01

-4

10

-3

10

-2

10

-1

110

Square Wave Pulse Duration (s)

Normalized Thermal Transient Impedance, Junction-to-Case

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?68684

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.

Document Number: 68684

S09-1086-Rev. C, 15-Jun-09

PowerPAK® 1212-8, (SINGLE/DUAL)

W

M

1

45

θ

c

2

E1

E

Notes:

1.

Inch will govern

2

Dimensions exclusive of mold gate burrs

3.

Dimensions exclusive of mold flash and cutting burrs

8

e

L1

θ

A

Package Information

Vishay Siliconix

H

θ

Z

2

D

D1

θ

A1

Detail Z

D4

D2

Backside View of Single Pad

HK

H

D4

D3(2x)

D2

Backside View of Dual Pad

E2

E4

E3

E2

E4

D1

D2

E3

L

K

1

2

D5

3

4

b

L

1

2

D5

3

K1

4

b

MILLIMETERS INCHES

DIM. MIN. NOM. MAX. MIN. NOM. MAX.

A 0.97 1.04 1.12 0.038 0.041 0.044

A1 0.00 - 0.05 0.000 - 0.002

b 0.23 0.30 0.41 0.009 0.012 0.016

c 0.23 0.28 0.33 0.009 0.011 0.013

D 3.20 3.30 3.40 0.126 0.130 0.134

D1 2.95 3.05 3.15 0.116 0.120 0.124

D2 1.98 2.11 2.24 0.078 0.083 0.088

D3 0.48 - 0.89 0.019 - 0.035

D4

D5

0.47 TYP. 0.0185 TYP.

2.3 TYP. 0.090 TYP.

E 3.20 3.30 3.40 0.126 0.130 0.134

E1 2.95 3.05 3.15 0.116 0.120 0.124

E2 1.47 1.60 1.73 0.058 0.063 0.068

E3 1.75 1.85 1.98 0.069 0.073 0.078

E4

0.34 TYP. 0.013 TYP.

e 0.65 BSC 0.026 BSC

K

0.86 TYP. 0.034 TYP.

K1 0.35 - - 0.014 - -

H 0.30 0.41 0.51 0.012 0.016 0.020

L 0.30 0.43 0.56 0.012 0.017 0.022

L1 0.06 0.13 0.20 0.002 0.005 0.008

θ 0° - 12° 0° - 12°

W 0.15 0.25 0.36 0.006 0.010 0.014

M

0.125 TYP. 0.005 TYP.

ECN: S10-0951-Rev. J, 03-May-10
DWG: 5882

Document Number: 71656 www.vishay.com
Revison: 03-May-10 1

PowerPAK® 1212 Mounting and Thermal Considerations

Johnson Zhao

AN822

Vishay Siliconix

MOSFETs for switching applications are now available
with die on resistances around 1 mΩ and with the
capability to handle 85 A. While these die capabilities
represent a major advance over what was available
just a few years ago, it is important for power MOSFET
packaging technology to keep pace. It should be obvi­ous that degradation of a high performance die by the
package is undesirable.
technology that addresses these issues. The PowerPAK
1212-8 provides ultra-low thermal impedance in a
small package that is ideal for space-constrained
applications. In this application note, the PowerPAK
1212-8’s construction is described. Following this,
mounting information is presented. Finally, thermal
and electrical performance is discussed.

THE PowerPAK PACKAGE

The PowerPAK 1212-8 package (Figure 1) is a deriva­tive of PowerPAK SO-8. It utilizes the same packaging
technology, maximizing the die area. The bottom of the
die attach pad is exposed to provide a direct, low resis­tance thermal path to the substrate the device is
mounted on. The PowerPAK 1212-8 thus translates
the benefits of the PowerPAK SO-8 into a smaller
package, with the same level of thermal performance.

(Please refer to application note “PowerPAK SO-8
Mounting and Thermal Considerations.”)

PowerPAK is a new package

The PowerPAK 1212-8 has a footprint area compara­ble to TSOP-6. It is over 40 % smaller than standard
TSSOP-8. Its die capacity is more than twice the size
of the standard TSOP-6’s. It has thermal performance
an order of magnitude better than the SO-8, and 20
times better than TSSOP-8. Its thermal performance is
better than all current SMT packages in the market. It
will take the advantage of any PC board heat sink
capability. Bringing the junction temperature down also

increases the die efficiency by around 20 % compared
with TSSOP-8. For applications where bigger pack­ages are typically required solely for thermal consider­ation, the PowerPAK 1212-8 is a good option.

Both the single and dual PowerPAK 1212-8 utilize the
same pin-outs as the single and dual PowerPAK SO-8.
The low 1.05 mm PowerPAK height profile makes both
versions an excellent choice for applications with
space constraints.

PowerPAK 1212 SINGLE MOUNTING

To take the advantage of the single PowerPAK 1212-8’s
thermal performance see Application Note 826,

Recommended Minimum Pad Patterns With Outline
Drawing Access for Vishay Siliconix MOSFETs. Click

on the PowerPAK 1212-8 single in the index of this
document.

In this figure, the drain land pattern is given to make full
contact to the drain pad on the PowerPAK package.

Figure 1. PowerPAK 1212 Devices

Document Number 71681
03-Mar-06

This land pattern can be extended to the left, right, and
top of the drawn pattern. This extension will serve to
increase the heat dissipation by decreasing the ther­mal resistance from the foot of the PowerPAK to the
PC board and therefore to the ambient. Note that
increasing the drain land area beyond a certain point
will yield little decrease in foot-to-board and foot-to­ambient thermal resistance. Under specific conditions
of board configuration, copper weight, and layer stack,
experiments have found that adding copper beyond an
area of about 0.3 to 0.5 in
ment in thermal performance.

2

of will yield little improve-

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1

AN822

Vishay Siliconix

PowerPAK 1212 DUAL

To take the advantage of the dual PowerPAK 1212-8’s
thermal performance, the minimum recommended
land pattern can be found in Application Note 826,

Recommended Minimum Pad Patterns With Outline
Drawing Access for Vishay Siliconix MOSFETs. Click

on the PowerPAK 1212-8 dual in the index of this doc­ument.

The gap between the two drain pads is 10 mils. This
matches the spacing of the two drain pads on the Pow­erPAK 1212-8 dual package.

This land pattern can be extended to the left, right, and
top of the drawn pattern. This extension will serve to
increase the heat dissipation by decreasing the ther­mal resistance from the foot of the PowerPAK to the
PC board and therefore to the ambient. Note that
increasing the drain land area beyond a certain point
will yield little decrease in foot-to-board and foot-to­ambient thermal resistance. Under specific conditions

of board configuration, copper weight, and layer stack,
experiments have found that adding copper beyond an

area of about 0.3 to 0.5 in
ment in thermal performance.

REFLOW SOLDERING

Vishay Siliconix surface-mount packages meet solder
reflow reliability requirements. Devices are subjected
to solder reflow as a preconditioning test and are then
reliability-tested using temperature cycle, bias humid­ity, HAST, or pressure pot. The solder reflow tempera-

2

of will yield little improve-

ture profile used, and the temperatures and time
duration, are shown in Figures 2 and 3. For the lead
(Pb)-free solder profile, see http://www.vishay.com/
doc?73257.

Ramp-Up Rate + 6 °C /Second Maximum

Temperature at 155 ± 15 °C 120 Seconds Maximum

Temperature Above 180 °C 70 - 180 Seconds

Maximum Temperature

Time at Maximum Temperature

Ramp-Down Rate

Figure 2. Solder Reflow Temperature Profile

240 + 5/- 0 °C

20 - 40 Seconds

+ 6 °C/Second Maximum

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2

140 - 170 °C

3° C/s (max)

10 s (max)

210 - 220 °C

3 °C/s (max) 4 °C/s (max)

183 °C

50 s (max)

60 s (min)

Pre-Heating Zone

Maximum peak temperature at 240 °C is allowed.

Figure 3. Solder Reflow Temperatures and Time Durations

Reflow Zone

Document Number 71681

03-Mar-06

TABLE 1: EQIVALENT STEADY STATE PERFORMANCE

Package SO-8 TSSOP-8 TSOP-8 PPAK 1212 PPAK SO-8

Configuration Single Dual Single Dual Single Dual Single Dual Single Dual

Thermal Resiatance R

thJC

(C/W)

20 40 52 83 40 90 2.4 5.5 1.8 5.5

AN822

Vishay Siliconix

PowerPAK 1212

49.8 °C

2.4 °C/W

PC Board at 45 °C

Standard SO-8

85 °C

20 °C/W

Figure 4. Temperature of Devices on a PC Board

THERMAL PERFORMANCE

Introduction

A basic measure of a device’s thermal performance is
the junction-to-case thermal resistance, Rθjc, or the
junction to- foot thermal resistance, Rθjf. This parameter
is measured for the device mounted to an infinite heat
sink and is therefore a characterization of the device
only, in other words, independent of the properties of the
object to which the device is mounted. Table 1 shows a
comparison of the PowerPAK 1212-8, PowerPAK SO-8,
standard TSSOP-8 and SO-8 equivalent steady state
performance.

By minimizing the junction-to-foot thermal resistance, the
MOSFET die temperature is very close to the tempera­ture of the PC board. Consider four devices mounted on
a PC board with a board temperature of 45 °C (Figure 4)

Suppose each device is dissipating 2 W. Using the junc­tion-to-foot thermal resistance characteristics of the
PowerPAK 1212-8 and the other SMT packages, die
temperatures are determined to be 49.8 °C for the Pow­erPAK 1212-8, 85 °C for the standard SO-8, 149 °C for
standard TSSOP-8, and 125 °C for TSOP-6. This is a

4.8 °C rise above the board temperature for the Power­PAK 1212-8, and over 40 °C for other SMT packages. A

4.8 °C rise has minimal effect on r
of over 40 °C will cause an increase in r

whereas a rise

DS(ON)

DS(ON)

as high

as 20 %.

Standard TSSOP-8

149 °C

52 °C/W

TSOP-6

40 °C/W

Spreading Copper

Designers add additional copper, spreading copper, to
the drain pad to aid in conducting heat from a device. It
is helpful to have some information about the thermal
performance for a given area of spreading copper.

Figure 5 and Figure 6 show the thermal resistance of a
PowerPAK 1212-8 single and dual devices mounted on
a 2-in. x 2-in., four-layer FR-4 PC boards. The two inter­nal layers and the backside layer are solid copper. The
internal layers were chosen as solid copper to model the
large power and ground planes common in many appli­cations. The top layer was cut back to a smaller area and
at each step junction-to-ambient thermal resistance
measurements were taken. The results indicate that an
area above 0.2 to 0.3 square inches of spreading copper

.

gives no additional thermal performance improvement.
A subsequent experiment was run where the copper on
the back-side was reduced, first to 50 % in stripes to
mimic circuit traces, and then totally removed. No signif­icant effect was observed.

125 °C

Document Number 71681
03-Mar-06

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3

AN822

Vishay Siliconix

105

95

85

75

(°C/W)

AJht

R

65

55

45

Spreading Copper (sq. in.)

100 %

50 %

0 %

0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00

Figure 5. Spreading Copper - Si7401DN

CONCLUSIONS

As a derivative of the PowerPAK SO-8, the PowerPAK
1212-8 uses the same packaging technology and has
been shown to have the same level of thermal perfor­mance while having a footprint that is more than 40 %
smaller than the standard TSSOP-8.

Recommended PowerPAK 1212-8 land patterns are
provided to aid in PC board layout for designs using this
new package.

130

120

110

100

(°C/W)

AJ
ht

R

Figure 6. Spreading Copper - Junction-to-Ambient Performance

Spreading Copper (sq. in.)

90

80

70

60

50

0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00

50 %

100 %

0 %

The PowerPAK 1212-8 combines small size with attrac­tive thermal characteristics. By minimizing the thermal
rise above the board temperature, PowerPAK simplifies
thermal design considerations, allows the device to run
cooler, keeps r

low, and permits the device to

DS(ON)

handle more current than a same- or larger-size MOS­FET die in the standard TSSOP-8 or SO-8 packages.

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Document Number 71681

03-Mar-06

RECOMMENDED MINIMUM PADS FOR PowerPAK® 1212-8 Single

0.152

(3.860)

Application Note 826

Vishay Siliconix

0.016

(0.405)

0.026

(0.660)

Return to Index

0.039

(0.990)

0.068

(1.725)

0.088
(2.235)

0.025

(0.635)

Recommended Minimum Pads

Dimensions in Inches/(mm)

0.030

(0.760)

0.010

(0.255)

0.094
(2.390)

Return to Index

Document Number: 72597 www.vishay.com
Revision: 21-Jan-08 7

APPLICATION NOTE

Legal Disclaimer Notice

www.vishay.com

Vishay

Disclaimer

ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.

Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
disclosure relating to any product.

Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all
liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,
consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular
purpose, non-infringement and merchantability.

Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical
requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements
about the suitability of products for a particular application. It is the customer’s responsibility to validate that a particular
product with the properties described in the product specification is suitable for use in a particular application. Parameters
provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All
operating parameters, including typical parameters, must be validated for each customer application by the customer’s
technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase,
including but not limited to the warranty expressed therein.

Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
applications or for any other application in which the failure of the Vishay product could result in personal injury or death.
Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk. Please
contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by
any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.

Material Category Policy

Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the
definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment
(EEE) - recast, unless otherwise specified as non-compliant.

Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.

Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free
requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21
conform to JEDEC JS709A standards.

Revision: 02-Oct-12

1

Document Number: 91000