Datasheet SiRA10bdp Datasheet (Mosfet)

www.vishay.com

PowerPAK® SO-8 Single

Top View

1

6.15 mm

5.15 mm

Bottom View

4

G

3

S

2

S

1

S

D

8
D
6

D

7
D
5

N-Channel MOSFET

G

D

S

N-Channel 30 V (D-S) MOSFET

FEATURES

• TrenchFET® Gen IV power MOSFET

• 100 % Rg and UIS tested

• Material categorization:
for definitions of compliance please see

www.vishay.com/doc?99912

APPLICATIONS

• High power density DC/DC

• Synchronous rectification

PRODUCT SUMMARY

VDS (V) 30
R

max. () at VGS = 10 V 0.0036

DS(on)

max. () at VGS = 4.5 V 0.0050

R

DS(on)

Q

typ. (nC) 11.7

g

I

(A) 60

D

a, g

Configuration Single

ORDERING INFORMATION

Package PowerPAK SO-8
Lead (Pb)-free and halogen-free SiRA10BDP-T1-GE3

• VRMs and embedded DC/DC

SiRA10BDP

Vishay Siliconix

ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT

Drain-source voltage V
Gate-source voltage V

= 25 °C

T

C

T

= 70 °C 60

Continuous drain current (T

= 150 °C)

J

C

TA = 25 °C 30
TA = 70 °C 24

Pulsed drain current (t = 100 μs) I

T

= 25 °C

Continuous source-drain diode current

Single pulse avalanche current
Single pulse avalanche energy E

Maximum power dissipation

C

T

= 25 °C 4.6

A

L = 0.1 mH

= 25 °C

T

C

T

= 70 °C 28

C

T

= 25 °C 5

A

I

P

TA = 70 °C 3.2
Operating junction and storage temperature range TJ, T
Soldering recommendations (peak temperature)

d, e

I

DM

I

AS

DS

GS

D

S

AS

D

stg

30

+20, -16

g

60

g

b, c

b, c

150

39

b, c

20
20 mJ
43

b, c

b, c

-55 to +150
260

V

A

W

°C

THERMAL RESISTANCE RATINGS

PARAMETER SMYBOL TYPICAL MAXIMUM UNIT

Maximum junction-to-ambient
Maximum junction-to-case (drain) Steady state R

Notes

a. Based on T
b. Surface mounted on 1" x 1" FR4 board
c. t = 10 s
d. See solder profile (www.vishay.com/doc?73257

(not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not

required to ensure adequate bottom side solder interconnection
e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components
f. Maximum under steady state conditions is 70 °C/W

= 25 °C

C

g. Package limited

S18-0315-Rev. A, 19-Mar-18

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

b, f

For technical questions, contact: [e-mail]

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed copper

t  10 s R

1

thJA

thJC

20 25

2.3 2.9

°C/W

Document Number: 76396

SiRA10BDP

www.vishay.com

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

Static

Drain-source breakdown voltage V

(c)

Drain-source breakdown voltage



(transient)

V

temperature coefficient VDS/T

DS

temperature coefficient V

V

GS(th)

Gate-source threshold voltage V

Gate-source leakage I

Zero gate voltage drain current I

On-state drain current

Drain-source on-state resistance

Forward transconductance

Dynamic

b

a

a

a

Input capacitance C

Reverse transfer capacitance C

C

ratio - 0.040 0.080

rss/Ciss

Total gate charge Q

Gate-source charge Q

Gate-drain charge Q

Output charge Q

Gate resistance R

Turn-on delay time t

Rise time t

Turn-off delay time t

Fall time t

Turn-on delay time t

Rise time t

Turn-off delay time t

Fall time t

DS

V

DSt

J

GS(th)/TJ

GS(th)

GSS

DSS

I

V

D(on)

R

DS(on)

g

fs

iss

oss

rss

g

gs

-2.8-

gd

oss

g

d(on)

r

-2550

d(off)

f

d(on)

r

-3060

d(off)

f

Drain-Source Body Diode Characteristics

Continuous source-drain diode current I

Pulse diode forward current

a

Body diode voltage V

Body diode reverse recovery time t

Body diode reverse recovery charge Q

Reverse recovery fall time t

Reverse recovery rise time t

S

I

SM

SD

rr

rr

a

b

Notes

a. Pulse test: pulse width  300 μs, duty cycle  2 %
b. Guaranteed by design, not subject to production testing
c. Based on characterization, not subject to production testing




Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

VGS = 0 V, ID = 250 μA 30 - -

VGS = 0 V, I

t

transcient

ID = 250 μA

V

= VGS, ID = 250 μA 1.2 - 2.4 V

DS

D(aval)

 50 ns

= 70 A,

36 - -

-18-

--3.8-

VDS = 0 V, VGS = +20, -16 V - - ± 100 nA

V

V

DS

= 30 V, V

DS

= 30 V, V

GS

 5 V, V

DS

V

= 10 V, ID = 10 A - 0.0023 0.0036

GS

= 4.5 V, ID = 7 A - 0.0035 0.0050

V

GS

= 0 V - - 1

GS

= 0 V, TJ = 55 °C - - 10

= 10 V 25 - - A

GS

VDS = 10 V, ID = 20 A - 68 - S

- 1710 -

VDS = 15 V, V

VDS = 15 V, V

= 0 V, f = 1 MHz

GS

= 10 V, ID = 10 A - 24.1 36.2

GS

- 655 -

-68-

- 11.7 17.6

= 15 V, V

DS

VDS = 15 V, V

= 4.5 V, ID = 10 A

GS

= 0 V - 18 -

GS

-4.2-

f = 1 MHz 0.3 1.3 2.6 

-715

V

I

 10 A, V

D

= 15 V, RL = 1.5 

DD

= 10 V, Rg = 1 

GEN

-2040

-1020

-1735

V

I

 10 A, V

D

= 15 V, RL = 1.5 

DD

= 4.5 V, Rg = 1 

GEN

-3570

-1530

TC = 25 °C - - 39

--150

IS = 10 A - 0.75 1.1 V

-3870ns

IF = 10 A, di/dt = 100 A/μs,

T

= 25 °C

J

-3670nC

-20-

-18-

Vishay Siliconix

V

mV/°C

μA



pFOutput capacitance C

nCV

ns

A

ns

S18-0315-Rev. A, 19-Mar-18

2

Document Number: 76396

For technical questions, contact: [e-mail]

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

www.vishay.com

10

100

1000

10000

0

0.001

0.002

0.003

0.004

0.005

0 20406080100

Axis Title

1st line

2nd line

2nd line

R

DS(on)

- On-Resistance (Ω)

ID- Drain Current (A)

2nd line

VGS= 10 V

VGS= 4.5 V

10

100

1000

10000

0.6

0.8

1.0

1.2

1.4

1.6

-50 -25 0 25 50 75 100 125 150

Axis Title

1st line

2nd line

2nd line

R

DS(on)

- On-Resistance (Normalized)

TJ- Junction Temperature (°C)

2nd line

ID= 10 A

VGS= 10 V

VGS= 4.5 V

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

SiRA10BDP

Vishay Siliconix

100

80

60

2nd line

40

- Drain Current (A)

D

I

20

0

0 0.5 1 1.5 2 2.5 3

VDS- Drain-to-Source Voltage (V)

Axis Title

VGS= 10 V thru 4 V

VGS= 3 V

2nd line

Output Characteristics

10000

1000

100

10

100

80

60

1st line

2nd line

2nd line

40

- Drain Current (A)

D

I

20

0

TC= 125 °C

01234

VGS- Gate-to-Source Voltage (V)

Transfer Characteristics

2500

2000

1500

TC= 25 °C

Axis Title

TC=-55 °C

2nd line

Axis Title

C

10000

1000

1st line

2nd line

100

10

10000

iss

1000

1st line

2nd line

1000

C - Capacitance (pF)

500

C

rss

0

0 5 10 15 20 25 30

VDS- Drain-to-Source Voltage (V)

On-Resistance vs. Drain Current

10

ID= 10 A

8

6

2nd line

4

- Gate-to-Source Voltage (V)

GS

V

S18-0315-Rev. A, 19-Mar-18

2

0

0 5 10 15 20 25

Qg- Total Gate Charge (nC)

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

Axis Title

VDS= 7.5 V

Gate Charge

VDS= 15 V

VDS= 24 V

2nd line

10000

1000

1st line

2nd line

100

10

On-Resistance vs. Junction Temperature

3

For technical questions, contact: [e-mail]

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

C

oss

2nd line

Capacitance

100

10

Document Number: 76396

2nd line

www.vishay.com

10

100

1000

10000

0

20

40

60

80

100

0.001 0.01 0.1 1 10 100 1000

Axis Title

1st line

2nd line

2nd line

Power (W)

Time (s)

2nd line

10

100

1000

10000

0.01

0.1

1

10

100

1000

0.01 0.1 1 10 100

Axis Title

1st line

2nd line

2nd line

I

D

- Drain Current (A)

VDS- Drain-to-Source Voltage (V)

(1)

VGS> minimum VGSat which R

DS(on)

is specified

Limited by R

DS(on)

(1)

TA= 25 °C

Single pulse

100 ms

10 ms

1 ms

100 µs

1 s
10 s

DC

IDMLimited

I

D(ON)

Limited

BV

dss

Limited

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

SiRA10BDP

Vishay Siliconix

100

Axis Title

10000

TJ= 150 °C

10

1000

0.010

0.008

Axis Title

10000

ID= 10 A

1000

0.006

TJ= 25 °C

1st line

2nd line

1

- Source Current (A)

S

I

0.1

100

10

0 0.2 0.4 0.6 0.8 1.0 1.2

VSD- Source-to-Drain Voltage (V)

2nd line

Source-Drain Diode Forward Voltage

2nd line

2nd line

0.004

- On-Resistance (Ω)

DS(on)

R

0.002

TJ= 25 °C

0

0246810

VGS- Gate-to-Source Voltage (V)

2nd line

On-Resistance vs. Gate-to-Source Voltage

TJ= 125 °C

100

10

1st line

2nd line

Axis Title

1.8

10000

1.6

1.4

(V)

GS(th)

V

1.2

ID= 250 µA

1000

1st line

2nd line

100

1.0

0.8

-50 -25 0 25 50 75 100 125 150

S18-0315-Rev. A, 19-Mar-18

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

10

TJ- Temperature (°C)

2nd line

Threshold Voltage

For technical questions, contact: [e-mail]

Safe Operating Area

4

Single Pulse Power, Junction-to-Ambient

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Document Number: 76396

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10

100

1000

10000

0

10

20

30

40

50

60

0 255075100125150

Axis Title

1st line

2nd line

2nd line

Power (W)

TC- Case Temperature (°C)

2nd line

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

SiRA10BDP

Vishay Siliconix

100

80

60

Package limited

2nd line

40

- Drain Current (A)

D

I

20

0

0 25 50 75 100 125 150

TC- Case Temperature (°C)

Axis Title

2nd line

Current Derating

10000

1000

1st line

2nd line

100

10

a

Power, Junction-to-Case

Note

a. The power dissipation P

dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the

is based on TJ max. = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper

D

package limit

S18-0315-Rev. A, 19-Mar-18

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

5

For technical questions, contact: [e-mail]

Document Number: 76396

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10

100

1000

10000

0.01

0.1

1

0.0001 0.001 0.01 0.1 1 10 100 1000

Axis Title

1st line

2nd line

Normalized Effective Transient

Thermal Impedance

Square Wave Pulse Duration (s)

2nd line

0.1

0.05

0.02

Single pulse

Duty Cycle = 0.5

0.2

10

100

1000

10000

0.01

0.1

1

0.0001 0.001 0.01 0.1

Axis Title

1st line

2nd line

Normalized Effective Transient

Thermal Impedance

Square Wave Pulse Duration (s)

2nd line

0.1

0.05

0.02

Single pulse

Duty Cycle = 0.5

0.2

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

Normalized Thermal Transient Impedance, Junction-to-Ambient

SiRA10BDP

Vishay Siliconix

Normalized Thermal Transient Impedance, Junction-to-Case


















Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?76396

S18-0315-Rev. A, 19-Mar-18

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

.

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

For technical questions, contact: [e-mail]

6

Document Number: 76396

www.vishay.com

Package Information

Vishay Siliconix

PowerPAK® SO-8, (Option B)

D

D1

5678

E1

E

4321

Notes:

1.

Inch will govern

2

Dimensions exclusive of mold gate burrs

3.

Dimensions exclusive of mold flash and cutting burrs

A

A1

C

E3

K

θ

5678

H

D2

D4

E2

W

L

43 21

e

b

Bottom viewSide viewTop view

DIM.

MIN. NOM. MAX. MIN. NOM. MAX.

A 0.90 1.00 1.10 0.035 0.039 0.043

A1 0.00 0.01 0.05 0.000 0.000 0.002

b 0.35 0.40 0.50 0.014 0.016 0.020
c 0.23 0.28 0.33 0.009 0.011 0.013

D 5.00 5.15 5.30 0.197 0.203 0.209
D1 4.75 4.90 5.05 0.187 0.193 0.199
D2 4.11 4.21 4.31 0.162 0.166 0.170

D4 0.515 0.545 0.575 0.020 0.021 0.023

E 5.95 6.10 6.25 0.234 0.240 0.246
E1 5.60 5.75 5.90 0.220 0.226 0.232
E2 3.59 3.69 3.79 0.141 0.145 0.149
E3 3.25 3.30 3.35 0.128 0.130 0.132

e 1.27 BSC 0.050 BSC

K 1.20 typ. 0.047 typ.

H 0.55 0.65 0.75 0.022 0.026 0.030

L 0.51 0.56 0.71 0.020 0.022 0.028

 12° 12°

W 0.21 0.26 0.31 0.008 0.010 0.012

ECN: S18-0566-Rev. A, 11-Jun-2018
DWG: 6068

MILLIMETERS INCHES

Revison: 11-Jun-2018

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

1

Document Number: 76657

VISHAY SILICONIX

www.vishay.com

Power MOSFETs

Application Note AN821

PowerPAK® SO-8 Mounting and Thermal Considerations

by Wharton McDaniel

MOSFETs for switching applications are now available with
die on resistances around 1 m and with the capability to
handle 85 A. While these die capabilities represent a major
advance over what was available just a few years ago, it is
important for power MOSFET packaging technology to keep
pace. It should be obvious that degradation of a high
performance die by the package is undesirable. PowerPAK
is a new package technology that addresses these issues.
In this application note, PowerPAK’s construction is
described. Following this mounting information is presented
including land patterns and soldering profiles for maximum
reliability. Finally, thermal and electrical performance is
discussed.

THE PowerPAK PACKAGE

The PowerPAK package was developed around the SO-8
package (figure 1). The PowerPAK SO-8 utilizes the same
footprint and the same pin-outs as the standard SO-8. This
allows PowerPAK to be substituted directly for a standard
SO-8 package. Being a leadless package, PowerPAK SO-8
utilizes the entire SO-8 footprint, freeing space normally
occupied by the leads, and thus allowing it to hold a larger
die than a standard SO-8. In fact, this larger die is slightly
larger than a full sized DPAK die. The bottom of the die
attach pad is exposed for the purpose of providing a direct,
low resistance thermal path to the substrate the device is
mounted on. Finally, the package height is lower than the
standard SO-8, making it an excellent choice for
applications with space constraints.

PowerPAK SO-8 SINGLE MOUNTING

The PowerPAK single is simple to use. The pin arrangement
(drain, source, gate pins) and the pin dimensions are the
same as standard SO-8 devices (see figure 2). Therefore, the
PowerPAK connection pads match directly to those of the
SO-8. The only difference is the extended drain connection
area. To take immediate advantage of the PowerPAK SO-8
single devices, they can be mounted to existing SO-8 land
patterns.

Standard SO-8 PowerPAK SO-8

Fig. 2

The minimum land pattern recommended to take full
advantage of the PowerPAK thermal performance see
Application Note 826, Recommended Minimum Pad

Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs. Click on the PowerPAK SO-8 single in the index

of this document.

In this figure, the drain land pattern is given to make full
contact to the drain pad on the PowerPAK package.

This land pattern can be extended to the left, right, and top
of the drawn pattern. This extension will serve to increase
the heat dissipation by decreasing the thermal resistance
from the foot of the PowerPAK to the PC board and
therefore to the ambient. Note that increasing the drain land
area beyond a certain point will yield little decrease
in foot-to-board and foot-to-ambient thermal resistance.
Under specific conditions of board configuration, copper
weight and layer stack, experiments have found that
more than about 0.25 in
(in addition to the drain land) will yield little improvement in
thermal performance.

2

to 0.5 in2 of additional copper

APPLICATION NOTE

Fig. 1 PowerPAK 1212 Devices

Revision: 16-Mai-13

For technical questions, contact: [e-mail]

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1

Document Number: 71622

Application Note AN821

www.vishay.com

Vishay Siliconix

PowerPAK® SO-8 Mounting and Thermal Considerations

PowerPAK SO-8 DUAL

The pin arrangement (drain, source, gate pins) and the pin
dimensions of the PowerPAK SO-8 dual are the same as
standard SO-8 dual devices. Therefore, the PowerPAK
device connection pads match directly to those of the SO-8.
As in the single-channel package, the only exception is the
extended drain connection area. Manufacturers can likewise
take immediate advantage of the PowerPAK SO-8 dual
devices by mounting them to existing SO-8 dual land
patterns.

To take the advantage of the dual PowerPAK SO-8’s
thermal performance, the minimum recommended land
pattern can be found in Application Note 826,

Recommended Minimum Pad Patterns With Outline
Drawing Access for Vishay Siliconix MOSFETs. Click on the

PowerPAK 1212-8 dual in the index of this document.

The gap between the two drain pads is 24 mils. This
matches the spacing of the two drain pads on the
PowerPAK SO-8 dual package.

REFLOW SOLDERING

Vishay Siliconix surface-mount packages meet solder reflow
reliability requirements. Devices are subjected to solder
reflow as a test preconditioning and are then
reliability-tested using temperature cycle, bias humidity,
HAST, or pressure pot. The solder reflow temperature profile
used, and the temperatures and time duration, are shown in
figures 3 and 4.

For the lead (Pb)-free solder profile, see

www.vishay.com/doc?73257.

Fig. 3 Solder Reflow Temperature Profile

Ramp-Up Rate + 3 °C /s max.

Temperature at 150 - 200 °C 120 s max.

Temperature Above 217 °C 60 - 150 s

Maximum Temperature 255 + 5/- 0 °C

Time at Maximum
Temperature

Ramp-Down Rate + 6 °C/s max.

30 s

30 s

260 °C

3 °C(max) 6 ° C/s (max.)

150 - 200 °C

Maximum peak temperature at 240 °C is allowed.

Fig. 4 Solder Reflow Temperatures and Time Durations

Revision: 16-Mai-13

APPLICATION NOTE

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

For technical questions, contact: [e-mail]

60 s (min.)

Pre-Heating Zone

2

217 °C

150 s (max.)

Reflow Zone

Document Number: 71622

www.vishay.com

Si4874DY vs. Si7446DP PPAK on a 4-Layer Board

SO-8 Pattern, Trough Under Drain

Pulse Duration (sec)

)
s

ttaw/

C
( e

cn
adep

m

I

0.0001

0

1

50

60

10

100000.01

40

20

Si4874DY

Si7446DP

100

30

Rth vs. Spreading Copper

(0 %, 50 %, 100 % Back Copper)

Spreading Copper (sq in)

)sttaw/C(

ecn

adep

m

I

0.00

56

51

46

41

36

0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00

0 %

50 %

100 %

PowerPAK® SO-8 Mounting and Thermal Considerations

THERMAL PERFORMANCE

Introduction

A basic measure of a device’s thermal performance
is the junction-to-case thermal resistance, R
junction-to-foot thermal resistance, R

This parameter is

thJF

measured for the device mounted to an infinite heat sink and
is therefore a characterization of the device only, in other
words, independent of the properties of the object to which
the device is mounted. Table 1 shows a comparison of
the DPAK, PowerPAK SO-8, and standard SO-8. The
PowerPAK has thermal performance equivalent to the
DPAK, while having an order of magnitude better thermal
performance over the SO-8.

TABLE 1 - DPAK AND POWERPAK SO-8
EQUIVALENT STEADY STATE
PERFORMANCE

DPAK

Thermal

Resistance R

1.2 °C/W 1 °C/W 16 °C/W

thJC

Thermal Performance on Standard SO-8 Pad Pattern

Because of the common footprint, a PowerPAK SO-8
can be mounted on an existing standard SO-8 pad pattern.
The question then arises as to the thermal performance
of the PowerPAK device under these conditions. A
characterization was made comparing a standard SO-8 and
a PowerPAK device on a board with a trough cut out
underneath the PowerPAK drain pad. This configuration
restricted the heat flow to the SO-8 land pads. The results
are shown in figure 5.

PowerPAK

SO-8

, or the

thJC

Standard

SO-8

Application Note AN821

Vishay Siliconix

Because of the presence of the trough, this result suggests
a minimum performance improvement of 10 °C/W by using
a PowerPAK SO-8 in a standard SO-8 PC board mount.

The only concern when mounting a PowerPAK on a
standard SO-8 pad pattern is that there should be no traces
running between the body of the MOSFET. Where the
standard SO-8 body is spaced away from the pc board,
allowing traces to run underneath, the PowerPAK sits
directly on the pc board.

Thermal Performance - Spreading Copper

Designers may add additional copper, spreading copper, to
the drain pad to aid in conducting heat from a device. It is
helpful to have some information about the thermal
performance for a given area of spreading copper.

Figure 6 shows the thermal resistance of a PowerPAK SO-8
device mounted on a 2-in. 2-in., four-layer FR-4 PC board.
The two internal layers and the backside layer are solid
copper. The internal layers were chosen as solid copper to
model the large power and ground planes common in many
applications. The top layer was cut back to a smaller area
and at each step junction-to-ambient thermal resistance
measurements were taken. The results indicate that an area
above 0.3 to 0.4 square inches of spreading copper gives no
additional thermal performance improvement. A
subsequent experiment was run where the copper on the
back-side was reduced, first to 50 % in stripes to mimic
circuit traces, and then totally removed. No significant effect
was observed.

Fig. 5 PowerPAK SO-8 and Standard SO-0 Land Pad Thermal

Revision: 16-Mai-13

APPLICATION NOTE

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

Path

For technical questions, contact: [e-mail]

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Fig. 6 Spreading Copper Junction-to-Ambient Performance

3

Document Number: 71622

Application Note AN821

0.6

0.8

1.0

1.2

1.4

1.6

1.8

-50 - 25 0 25 50 75 100 125 150

V

GS

= 10 V

I

D

= 23 A

On-Resistance vs. Junction Temperature

T

J

- Junction Temperature (°C)

)dezilamroN(( ecnatsiseR-nO -R

)no(SD

)

www.vishay.com

Vishay Siliconix

PowerPAK® SO-8 Mounting and Thermal Considerations

SYSTEM AND ELECTRICAL IMPACT OF
PowerPAK SO-8

In any design, one must take into account the change in
MOSFET R

A MOSFET generates internal heat due to the current
passing through the channel. This self-heating raises the
junction temperature of the device above that of the PC
board to which it is mounted, causing increased power
dissipation in the device. A major source of this problem lies
in the large values of the junction-to-foot thermal resistance
of the SO-8 package.

PowerPAK SO-8 minimizes the junction-to-board thermal
resistance to where the MOSFET die temperature is very
close to the temperature of the PC board. Consider two
devices mounted on a PC board heated to 105 °C by other
components on the board (figure 8).

with temperature (figure 7).

DS(on)

Fig. 7 MOSFET R

DS(on)

vs. Temperature

Suppose each device is dissipating 2.7 W. Using the
junction-to-foot thermal resistance characteristics of the
PowerPAK SO-8 and the standard SO-8, the die
temperature is determined to be 107 °C for the PowerPAK
(and for DPAK) and 148 °C for the standard SO-8. This is a
2 °C rise above the board temperature for the PowerPAK
and a 43 °C rise for the standard SO-8. Referring to figure 7,
a 2 °C difference has minimal effect on R
43 °C difference has a significant effect on R

DS(on)

DS(on)

whereas a

.

Minimizing the thermal rise above the board temperature by
using PowerPAK has not only eased the thermal design but
it has allowed the device to run cooler, keep r

DS(on)

low, and
permits the device to handle more current than the same
MOSFET die in the standard SO-8 package.

CONCLUSIONS

PowerPAK SO-8 has been shown to have the same thermal
performance as the DPAK package while having the same
footprint as the standard SO-8 package. The PowerPAK
SO-8 can hold larger die approximately equal in size to the
maximum that the DPAK can accommodate implying no
sacrifice in performance because of package limitations.

Recommended PowerPAK SO-8 land patterns are provided
to aid in PC board layout for designs using this new
package.

Thermal considerations have indicated that significant
advantages can be gained by using PowerPAK SO-8
devices in designs where the PC board was laid out for
the standard SO-8. Applications experimental data gave
thermal performance data showing minimum and
typical thermal performance in a SO-8 environment, plus
information on the optimum thermal performance
obtainable including spreading copper. This further
emphasized the DPAK equivalency.

PowerPAK SO-8 therefore has the desired small size
characteristics of the SO-8 combined with the attractive
thermal characteristics of the DPAK package.

PowerPAK SO-8

107 °C

0.8 °C/W

Fig. 8 Temperature of Devices on a PC Board

Revision: 16-Mai-13

PC Board at 105 °C

APPLICATION NOTE

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Standard SO-8

148 °C

16 C/W

4

For technical questions, contact: [e-mail]

Document Number: 71622

RECOMMENDED MINIMUM PADS FOR PowerPAK® SO-8 Single

0.260

(6.61)

0.150

(3.81)

0.024

(0.61)

Application Note 826

Vishay Siliconix

Return to Index

Return to Index

0.026

(0.66)

0.050

(1.27)

0.050

(1.27)

0.032

(0.82)

Recommended Minimum Pads

Dimensions in Inches/(mm)

0.154

(3.91)

0.040

(1.02)

0.174

(4.42)

APPLICATION NOTE

Document Number: 72599 www.vishay.com
Revision: 21-Jan-08 15

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