Datasheet sihll014_irll014 Datasheet

Page 1
Power MOSFET
IRLL014, SiHLL014
Vishay Siliconix
PRODUCT SUMMARY
VDS (V) 60
(Ω)V
R
DS(on)
Q
(Max.) (nC) 8.4
g
(nC) 3.5
Q
gs
Q
(nC) 6.0
gd
Configuration Single
= 5.0 V 0.20
GS
FEATURES
• Halogen-free According to IEC 61249-2-21 Definition
• Surface Mount
• Available in Tape and Reel
• Dynamic dV/dt Rating
• Logic-Level Gate Drive
•R
•Fast Switching
Specified at VGS = 4 V and 5 V
DS(on)
• Ease of Paralleling
D
• Compliant to RoHS Directive 2002/95/EC
DESCRIPTION
SOT-223
D
S
D
G
G
S
N-Channel MOSFET
Third generation Power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The SOT-223 package is designed for surface-mounting using vapor phase, infrared, or wave soldering techniques. Its unique package design allows for easy automatic pick-and-place as with other SOT or SOIC packages but has the added advantage of improved thermal performace due to an enlarged tab for heatsinking. Power dissipation of greater than 1.25 W is possible in a typical surface mount application.
ORDERING INFORMATION
Package SOT-223 SOT-223 Lead (Pb)-free and Halogen-free SiHLL014-GE3 SiHLL014TR-GE3
Lead (Pb)-free
SnPb
Note
a. See device orientation.
IRLL014PbF IRLL014TRPbF SiHLL014-E3 SiHLL014T-E3 IRLL014 IRLL014TR SiHLL014 SiHLL014T
a
a
a
a
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER SYMBOL LIMIT UNIT
Drain-Source Voltage V Gate-Source Voltage V
T
= 25 °C
Continuous Drain Current V
Pulsed Drain Current
a
at 10 V
GS
C
T
= 100 °C 1.7
C
DS
± 10
GS
I
D
IDM 22 Linear Derating Factor 0.025 Linear Derating Factor (PCB Mount) Single Pulse Avalanche Energy Repetitive Avalanche Current Repetitive Avalanche Energy Maximum Power Dissipation T Maximum Power Dissipation (PCB Mount) Peak Diode Recovery dV/dt Operating Junction and Storage Temperature Range T
e
b
a
a
= 25 °C
e
c
C
TA = 25 °C 2.0
E
AS
I
AR
E
AR
P
D
dV/dt 4.5 V/ns
, T
J
stg
Soldering Recommendations (Peak Temperature) for 10 s 300
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. V
= 25 V, starting TJ = 25 °C, L = 16 mH, Rg = 25 Ω, IAS = 2.7 A (see fig. 12).
DD
c. I
≤ 10 A, dI/dt ≤ 90 A/μs, VDD ≤ VDS, TJ ≤ 150 °C.
SD
d. 1.6 mm from case. e. When mounted on 1" square PCB (FR-4 or G-10 material).
60
2.7
0.017 100 mJ
2.7 A
0.31 mJ
3.1
- 55 to + 150
d
V
A
W/°C
W
°C
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 91319 www.vishay.com S10-1257-Rev. C, 31-May-10 1
Page 2
IRLL014, SiHLL014
D
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Maximum Junction-to-Ambient (PCB Mount)
a
Maximum Junction-to-Case (Drain) R
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material).
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-Source Breakdown Voltage V
V
Temperature Coefficient ΔVDS/TJ Reference to 25 °C, ID = 1 mA - 0.073 - V/°C
DS
Gate-Source Threshold Voltage V
Gate-Source Leakage I
Zero Gate Voltage Drain Current I
Drain-Source On-State Resistance R
Forward Transconductance g
Dynamic
Input Capacitance C
Reverse Transfer Capacitance C
Total Gate Charge Q
Gate-Drain Charge Q
Turn-On Delay Time t
Rise Time t
Turn-Off Delay Time t
Fall Time t
Internal Drain Inductance L
Internal Source Inductance L
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current I
Pulsed Diode Forward Current
Body Diode Voltage V
Body Diode Reverse Recovery Time t
Body Diode Reverse Recovery Charge Q
Forward Turn-On Time t
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %.
a
R
thJA
thJC
DS
GS(th)
V
GSS
--60 °C/W
--40
VGS = 0 V, ID = 250 μA 60 - - V
VDS = VGS, ID = 250 μA 1.0 - 2.0 V
= ± 10 V - - ± 100 nA
GS
VDS = 60 V, VGS = 0 V - - 25
DSS
DS(on)
fs
iss
- 170 -
oss
-42-
rss
g
--3.5
gs
--6.0
gd
d(on)
r
-17-
d(off)
-26-
f
D
S
S
I
SM
SD
rr
rr
on
V
= 48 V, VGS = 0 V, TJ = 125 °C - - 250
DS
= 5.0 V ID = 1.6 A
V
GS
V
= 4.0 V ID = 1.4 A
GS
b
b
- - 0.20
- - 0.28
VDS = 25 V, ID = 1.6 A 3.2 - - S
VGS = 0 V,
V
= 25 V,
DS
f = 1.0 MHz, see fig. 5
- 400 -
--8.4
= 10 A, VDS = 48 V,
I
V
GS
= 5.0 V
D
see fig. 6 and 13
b
-9.3-
V
= 30 V, ID = 10 A,
DD
R
= 12 Ω, RD = 2.8 Ω, see fig. 10
G
Between lead, 6 mm (0.25") from package and center of
G
die contact
MOSFET symbol showing the integral reverse
G
p - n junction diode
TJ = 25 °C, IS = 2.7 A, VGS = 0 V
TJ = 25 °C, IF = 10 A, dI/dt = 100 A/μs
b
D
S
b
- 110 -
-4.0-
-6.0-
--2.7
--22
--1.6V
- 65 130 ns
b
- 0.33 0.65 μC
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
μA
Ω
pFOutput Capacitance C
nC Gate-Source Charge Q
ns
nH
A
www.vishay.com Document Number: 91319 2 S10-1257-Rev. C, 31-May-10
Page 3
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
V
GS
Top
7.5 V
1
10
5.0 V
4.0 V
3.5 V
3.0 V
2.75 V
Bottom
2.5 V
0
10
IRLL014, SiHLL014
Vishay Siliconix
1
10
150 °C
0
10
-1
10
, Drain Current (A)
D
I
-2
10
2.25 V
20 µs Pulse Width
= 25 °C
T
C
-1
10
0
10
1
10
VDS, Drain-to-Source Voltage (V)
Fig. 1 - Typical Output Characteristics, TC = 25 °C
V
GS
Top
7.5 V
5.0 V
4.0 V
1
10
3.5 V
3.0 V
2.75 V
Bottom
2.5 V
0
10
rrent (A) u
2.25 V
20 µs Pulse Width T
= 150 °C
C
1
10
, Drain C
D
I
-1
10
-2
10
-1
10
0
10
VDS, Drain-to-Source Voltage (V)
-1
10
, Drain Current (A)
-2
D
10
I
-3
10
2
25 °C
20 µs Pulse Width V
2.5 3 3.5 4 4.5 5
V
Gate-to-Source Voltage (V)
,
GS
Fig. 3 - Typical Transfer Characteristics
3.0 I
= 10 A
D
= 10 V
V
GS
2.5
2.0
1.5
(Normalized)
1.0
, Drain-to-Source On Resistance
0.5
DS(on)
0.0
R
- 60 - 40 - 20 0 20 40 60 80 100 120 140 160
T
Junction Temperature (°C)
,
J
= 25 V
DS
Fig. 2 - Typical Output Characteristics, T
= 150 °C
C
Fig. 4 - Normalized On-Resistance vs. Temperature
Document Number: 91319 www.vishay.com S10-1257-Rev. C, 31-May-10 3
Page 4
IRLL014, SiHLL014
Vishay Siliconix
700
600
V
= 0 V, f = 1 MHz
GS
= Cgs + Cgd, Cds Shorted
C
iss
= C
C
rss
gd
C
= Cds + C
oss
gd
500
400
C
iss
300
C
Capacitance (pF)
200
100
0
0
10
V
10
Drain-to-Source Voltage (V)
,
DS
oss
C
rss
1
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
10
ID = 10 A
6
6
V
= 30 V
DS
V
DS
= 48 V
4
2
, Gate-to-Source Voltage (V)
GS
V
0
0
2
4
For test circuit see figure 13
86
10
QG, Total Gate Charge (nC)
TJ = 150 °C
1
10
= 25 °C
T
0
10
J
, Reverse Drain Current (A)
SD
I
-1
10
0.4
1.61.20.8
V
2.0
GS
= 0 V
VSD, Source-to-Drain Voltage (V)
Fig. 7 - Typical Source-Drain Diode Forward Voltage
3
10
5
2
Operation in this area limited by R
2
10
5
2
10
5
2
1
, Drain Current (A)
D
I
5
2
0.1
25
0.1
1
TC = 25 °C
= 150 °C
T
J
Single Pulse
25
10
100 µs
1 ms
25
10
DS(on)
10 ms
2
25
VDS, Drain-to-Source Voltage (V)
2.4
10
3
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 8 - Maximum Safe Operating Area
www.vishay.com Document Number: 91319 4 S10-1257-Rev. C, 31-May-10
Page 5
3.0
2.5
2.0
1.5
1.0
, Drain Current (A)
D
I
0.5
0.0 25 1501251007550
TC, Case Temperature (°C)
Fig. 9 - Maximum Drain Current vs. Case Temperature
IRLL014, SiHLL014
Vishay Siliconix
R
D.U.T.
D
+
-
t
t
d(off)
f
V
DS
V
GS
R
g
10 V
Pulse width ≤ 1 µs Duty factor ≤ 0.1 %
Fig. 10a - Switching Time Test Circuit
V
DS
90 %
10 %
V
GS
t
t
d(on)
r
Fig. 10b - Switching Time Waveforms
V
DD
2
10
)
thJC
10
D = 0.50
0.20
0.10
0.05
1
0.02
0.01
-1
10
Thermal Response (Z
-2
10
-5
10
P
DM
Single Pulse (Thermal Response)
Notes:
1. Duty Factor, D = t
2. Peak Tj = PDM x Z
-4
10
-3
10
-2
10
0.1 1 10
1
10
10
t1, Rectangular Pulse Duration (s)
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
t
1
t
2
1/t2
+ T
thJC
C
2
3
Document Number: 91319 www.vishay.com S10-1257-Rev. C, 31-May-10 5
Page 6
IRLL014, SiHLL014
Vishay Siliconix
V
to obtain
Var y t
p
required I
AS
DS
R
g
D.U.T
I
AS
10 V
L
t
p
0.01 Ω
Fig. 12a - Unclamped Inductive Test Circuit
250
200
150
100
50
V
DS
t
p
+
V
DD
-
V
DS
I
AS
V
DD
Fig. 12b - Unclamped Inductive Waveforms
I
To p
Bottom
D
1.2 A
1.7 A
2.7 A
, Single Pulse Avalanche Energy (mJ)
AS
E
V
= 25 V
DD
0
25 150
50
125
10075
Starting TJ, Junction Temperature (°C)
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
Q
V
GS
Q
GS
V
G
G
Q
GD
12 V
V
GS
0.2 µF
50 kΩ
3 mA
0.3 µF
D.U.T.
+
-
Charge
I
G
Current sampling resistors
I
D
Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit
V
DS
www.vishay.com Document Number: 91319 6 S10-1257-Rev. C, 31-May-10
Page 7
Peak Diode Recovery dV/dt Test Circuit
IRLL014, SiHLL014
Vishay Siliconix
D.U.T.
+
-
R
g
Driver gate drive
P.W.
+
-
Period
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
• dV/dt controlled by R
• Driver same type as D.U.T.
I
controlled by duty factor “D”
•
SD
• D.U.T. - device under test
-
D =
g
P.W.
Period
+
+
V
DD
-
V
= 10 Va
GS
D.U.T. l
waveform
SD
Reverse recovery current
Re-applied voltage
D.U.T. V
Inductor current
Note
a. V
waveform
DS
= 5 V for logic level devices
GS
Body diode forward
current
dI/dt
Diode recovery
dV/dt
Body diode forward drop
Ripple ≤ 5 %
V
DD
I
SD
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91319
.
Document Number: 91319 www.vishay.com S10-1257-Rev. C, 31-May-10 7
Page 8
SOT-223 (HIGH VOLTAGE)
Package Information
Vishay Siliconix
3
B
B1
0.10 (0.004)
0.10 (0.004)
0.20 (0.008)
3 x B
0.10 (0.004)
H
D
3
A
4
3
E
1
2
e
e1
MILLIMETERS INCHES
DIM. MIN. MAX. MIN. MAX.
A 1.55 1.80 0.061 0.071
B 0.65 0.85 0.026 0.033
B1 2.95 3.15 0.116 0.124
C 0.25 0.35 0.010 0.014
D 6.30 6.70 0.248 0.264
E 3.30 3.70 0.130 0.146
e 2.30 BSC 0.0905 BSC
e1 4.60 BSC 0.181 BSC
H 6.71 7.29 0.264 0.287
L 0.91 - 0.036 -
L1 0.061 BSC 0.0024 BSC
θ - 10' - 10'
ECN: S-82109-Rev. A, 15-Sep-08 DWG: 5969
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions are shown in millimeters (inches).
3. Dimension do not include mold flash.
4. Outline conforms to JEDEC outline TO-261AA.
A
M
M
M
M
C
C B
M
M
C A
M
M
C B
C
L1
4 x L
θ
0.08 (0.003)
4 x C
Document Number: 91363 www.vishay.com Revision: 15-Sep-08 1
Page 9
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Disclaimer

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Document Number: 91000 www.vishay.com Revision: 11-Mar-11 1
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