Datasheet IRLD014, SiHLD014 DataSheet (Vishay)

HVMDIP

D

S

G

Available

RoHS*

COMPLIANT

Power MOSFET

IRLD014, SiHLD014

Vishay Siliconix

PRODUCT SUMMARY

VDS (V) 60

R

()V

DS(on)

Q

(Max.) (nC) 8.4

g

Q

(nC) 2.6

gs

Q

(nC) 6.4

gd

Configuration Single

= 5 V 0.20

GS

D

FEATURES

• Dynamic dV/dt Rating

• For Automatic Insertion

• End Stackable

• Logic-Level Gate Drive

•R

DS(on)

• 175 °C Operating Temperature

• Fast Switching

• Compliant to RoHS Directive 2002/95/EC

DESCRIPTION

G

S

N-Channel MOSFET

Third generation Power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
The 4 pin DIP package is a low cost machine-insertiable
case style which can be stacked in multiple combinations on
standard 0.1" pin centers. The dual drain servers as a
thermal link to the mounting surface for power dissipation
levels up to 1 W.

ORDERING INFORMATION

Package HVMDIP

Lead (Pb)-free

SnPb

IRLD014PbF
SiHLD014-E3
IRLD014
SiHLD014

Specified at VGS = 4 V and 5 V

ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT

Drain-Source Voltage V

Gate-Source Voltage V

= 25 °C

T

Continuous Drain Current V

Pulsed Drain Current

Linear Derating Factor 0.0083 W/°C

Single Pulse Avalanche Energy

Maximum Power Dissipation T

Peak Diode Recovery dV/dt

Operating Junction and Storage Temperature Range T

Soldering Recommendations (Peak Temperature) for 10 s 300

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).

= 25 V, starting TJ = 25 °C, L = 197 mH, Rg = 25 , IAS = 1.7 A (see fig. 12).

b. V

DD

c. I

 10 A, dI/dt  90 A/µs, VDD  VDS, TJ  175 °C.

SD

d. 1.6 mm from case.

* Pb containing terminations are not RoHS compliant, exemptions may apply

Document Number: 91307 www.vishay.com
S10-2465-Rev. D, 08-Nov-10 1

a

b

c

at 5.0 V

GS

A

= 100 °C 1.2

A

= 25 °C P

A

DS

± 10

GS

I

D

IDM 14

E

AS

D

dV/dt 4.5 V/ns

, T

J

stg

60

1.7

490 mJ

1.3 W

- 55 to + 175

d

V

AT

°C

IRLD014, SiHLD014

Vishay Siliconix

THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL TYP. MAX. UNIT

Maximum Junction-to-Ambient R

thJA

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

Static

Drain-Source Breakdown Voltage V

V

Temperature Coefficient VDS/TJ Reference to 25 °C, ID = 1 mA - 0.070 - V/°C

DS

Gate-Source Threshold Voltage V

Gate-Source Leakage I

Zero Gate Voltage Drain Current I

Drain-Source On-State Resistance R

Forward Transconductance g

Dynamic

Input Capacitance C

Reverse Transfer Capacitance C

Total Gate Charge Q

Gate-Drain Charge Q

Turn-On Delay Time t

Rise Time t

Turn-Off Delay Time t

Fall Time t

Internal Drain Inductance L

Internal Source Inductance L

Drain-Source Body Diode Characteristics

DS

GS(th)

V

GSS

DSS

DS(on)

fs

iss

- 170 -

oss

-42-

rss

g

--2.6

gs

--6.4

gd

d(on)

r

-17-

d(off)

-26-

f

D

V

V

GS

V

GS

V

GS

R

Between lead,
6 mm (0.25") from
package and center of

S

die contact

- 120 °C/W

VGS = 0 V, ID = 250 µA 60 - - V

VDS = VGS, ID = 250 µA 1.0 - 2.0 V

= ± 10 V - - ± 100 nA

GS

VDS = 60 V, VGS = 0 V - - 25

= 48 V, VGS = 0 V, TJ = 150 °C - - 250

DS

= 5.0 V ID = 1.0 A

= 4.0 V ID = 0.85 A

VDS = 25 V, ID = 1.0 A

VGS = 0 V

V

= 25 V

DS

f = 1.0 MHz, see fig. 5

b

b

b

- - 0.20

- - 0.28

1.9 - - S

- 400 -

--8.4

= 10 A, VDS = 48 V

I

= 5.0 V

D

see fig. 6 and 13

b

-9.3-

V

= 30 V, ID = 10 A

DD

= 12 , RD = 2.8 , see fig. 10

g

G

b

D

S

- 110 -

-4.0-

-6.0-

µA



pFOutput Capacitance C

nC Gate-Source Charge Q

ns

nH

Continuous Source-Drain Diode Current I

Pulsed Diode Forward Current

a

Body Diode Voltage V

Body Diode Reverse Recovery Time t

Body Diode Reverse Recovery Charge Q

Forward Turn-On Time t

S

I

SM

SD

rr

rr

on

MOSFET symbol
showing the

integral reverse
p - n junction diode

TJ = 25 °C, IS = 1.7 A, VGS = 0 V

TJ = 25 °C, IF = 10 A, dI/dt = 100 A/µs

Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)

D

G

S

b

--1.7

--14

--1.6V

- 93 130 ns

b

A

- 0.34 0.65 µC

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width  300 µs; duty cycle  2 %.

www.vishay.com Document Number: 91307
2 S10-2465-Rev. D, 08-Nov-10

20 µs PULSE WIDTH
T

A

= 25 °C

20 µs PULSE WIDTH
T

A

= 175 °C

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

IRLD014, SiHLD014

Vishay Siliconix

Fig. 1 - Typical Output Characteristics, TA = 25 °C

Fig. 2 - Typical Output Characteristics, T

= 175 °C

A

Fig. 3 - Typical Transfer Characteristics

Fig. 4 - Normalized On-Resistance vs. Temperature

Document Number: 91307 www.vishay.com
S10-2465-Rev. D, 08-Nov-10 3

IRLD014, SiHLD014

TA = 25 °C
T

J

= 175 °C

SINGLE PULSE

Vishay Siliconix

Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage

Fig. 7 - Typical Source-Drain Diode Forward Voltage

Fig. 8 - Maximum Safe Operating Area

www.vishay.com Document Number: 91307
4 S10-2465-Rev. D, 08-Nov-10

I

D

, Drain Current (A)

TA, Ambient Temperature (°C)

V

DS

90 %

10 %

V

GS

t

d(on)

t

r

t

d(off)

t

f

Thermal Response (Z

thJA

)

t1, Rectangular Pulse Duration (s)

t1, Rectangular Pulse Duration (s)

IRLD014, SiHLD014

Vishay Siliconix

R

D.U.T.

D

+

V

-

DD

V

DS

V

GS

R

g

10 V

Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %

Fig. 10a - Switching Time Test Circuit

Fig. 9 - Maximum Drain Current vs. Ambient Temperature

Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Ambient

Fig. 10b - Switching Time Waveforms

Document Number: 91307 www.vishay.com
S10-2465-Rev. D, 08-Nov-10 5

IRLD014, SiHLD014

R

g

I

AS

0.01 W

t

p

D.U.T.

L

V

DS

+

-

V

DD

10 V

Vary t

p

to obtain

required I

AS

D.U.T.

3 mA

V

GS

V

DS

I

G

I

D

0.3 µF

0.2 µF

50 kΩ

12 V

Current regulator

Current sampling resistors

Same type as D.U.T.

+

-

Vishay Siliconix

Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms

V

DS

t

p

V

DS

I

AS

V

DD

Fig. 12c - Maximum Avalanche Energy vs. Drain Current

Q

V

GS

Q

GS

V

G

G

Q

GD

Charge

www.vishay.com Document Number: 91307
6 S10-2465-Rev. D, 08-Nov-10

Fig. 13a - Basic Gate Charge Waveform

Fig. 13b - Gate Charge Test Circuit

Peak Diode Recovery dV/dt Test Circuit

IRLD014, SiHLD014

Vishay Siliconix

D.U.T.

+

-

R

g

Driver gate drive

P.W.

+

-

Period

Circuit layout considerations

• Low stray inductance

• Ground plane

• Low leakage inductance

current transformer

• dV/dt controlled by R

• Driver same type as D.U.T.

•

I

controlled by duty factor “D”

SD

• D.U.T. - device under test

-

D =

g

Period

P.W.

+

+

V

DD

-

V

= 10 Va

GS

D.U.T. l

Reverse
recovery
current

D.U.T. V

Re-applied
voltage

Inductor current

Note

a. V

waveform

SD

Body diode forward

waveform

DS

Body diode forward drop

Ripple ≤ 5 %

= 5 V for logic level devices

GS

current

dI/dt

Diode recovery

dV/dt

V

DD

I

SD

Fig. 14 - For N-Channel

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91307

.

Document Number: 91307 www.vishay.com
S10-2465-Rev. D, 08-Nov-10 7

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www.vishay.com

Vishay

Disclaimer



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RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.

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Revision: 13-Jun-16

1

Document Number: 91000