Datasheet IRL620S, SiHL620S DataSheet (Vishay)

N-Channel MOSFET

G

D

S

D2PAK (TO-263)

G

D

S

Power MOSFET

IRL620S, SiHL620S

Vishay Siliconix

Note

a. See device orientation.

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. V
c. I
d. 1.6 mm from case.
e. When mounted on 1" square PCB (FR-4 or G-10 material).

PRODUCT SUMMARY

VDS (V) 200

()V

R

DS(on)

Q

(Max.) (nC) 16

g

Q

(nC) 2.9

gs

Q

(nC) 9.6

gd

Configuration Single

= 10 V 0.80

GS

FEATURES

• Halogen-free According to IEC 61249-2-21
Definition

• Surface Mount

• Available in Tape and Reel

• Dynamic dV/dt Rating

• Repetitive Avalanche Rated

• Logic Level Gate Drive

•R

•Fast Switching

Specified at VGS = 4 V and 5 V

DS(on)

• Compliant to RoHS Directive 2002/95/EC

DESCRIPTION

Third generation Power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.

2

The D

PAK (TO-263) is a surface mount power package
capable of accommodating die sizes up to HEX-4. It
provides the highest power capability and the lowest
possible on- resistance in any existing surface mount
package. The D2PAK (TO-263) is suitable for high current
applications because of its low internal connection
resistance and can dissipate up to 2.0 W in a typical surface
mount application.

ORDERING INFORMATION

Package D2PAK (TO-263) D2PAK (TO-263)
Lead (Pb)-free and Halogen-free SiHL620S-GE3 SiHL620STRL-GE3

Lead (Pb)-free IRL620STRLPbF

IRL620SPbF IRL620STRLPbF
SiHL620S-E3 SiHL620STL-E3

a

a

a

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT

Drain-Source Voltage V
Gate-Source Voltage V

T

= 25 °C

Continuous Drain Current V

Pulsed Drain Current

a

GS

at 5 V

C

= 100 °C 3.3

T

C

DS

± 10

GS

I

D

IDM 21
Linear Derating Factor 0.40
Linear Derating Factor (PCB Mount)
Single Pulse Avalanche Energy
Repetitive Avalanche Current
Repetitive Avalanche Energy
Maximum Power Dissipation T
Maximum Power Dissipation (PCB Mount)
Peak Diode Recovery dV/dt
Operating Junction and Storage Temperature Range T

e

b

a

a

= 25 °C

e

c

C

TA = 25 °C 3.1

E

AS

I

AR

E

AR

P

D

dV/dt 5.0 V/ns

, T

J

stg

Soldering Recommendations (Peak Temperature) for 10 s 300

= 50 V, starting TJ = 25 °C, L = 6.9 mH, Rg = 25 , IAS = 5.2 A (see fig. 12).

DD

 5.2 A, dI/dt  95 A/μs, VDD  VDS, TJ  150 °C.

SD

200

5.2

0.025
125 mJ

5.2 A

5.0 mJ
50

- 55 to + 150

d

V

A

W/°C

W

°C

* Pb containing terminations are not RoHS compliant, exemptions may apply

Document Number: 91302

www.vishay.com

S11-1054-Rev. C, 30-May-11 1

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

www.vishay.com/doc?91000

D

S

G

S

D

G

IRL620S, SiHL620S

Vishay Siliconix

THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL TYP. MAX. UNIT

Maximum Junction-to-Ambient R

Maximum Junction-to Ambient (PCB

Maximum Junction-to-Case (Drain) R

thJA

R

thJA

thJC

Note

a. When mounted on 1" square PCB (FR-4 or G-10 material).

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

Static

Drain-Source Breakdown Voltage V

Temperature Coefficient VDS/TJ Reference to 25 °C, ID = 1 mA - 0.27 - V/°C

V

DS

Gate-Source Threshold Voltage V

Gate-Source Leakage I

Zero Gate Voltage Drain Current I

Drain-Source On-State Resistance R

Forward Transconductance g

Dynamic

Input Capacitance C

Reverse Transfer Capacitance C

Total Gate Charge Q

Gate-Drain Charge Q

Turn-On Delay Time t

Rise Time t

Turn-Off Delay Time t

Fall Time t

Internal Drain Inductance L

Internal Source Inductance L

Drain-Source Body Diode Characteristics

Continuous Source-Drain Diode Current I

Pulsed Diode Forward Current

a

Body Diode Voltage V

Body Diode Reverse Recovery Time t

Body Diode Reverse Recovery Charge Q

Forward Turn-On Time t

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width  300 μs; duty cycle  2 %.

DS

GS(th)

V

GSS

DSS

DS(on)

fs

iss

-91-

oss

-27-

rss

g

--2.9

gs

--9.6

gd

d(on)

r

-18-

d(off)

-17-

f

D

S

S

I

SM

SD

rr

rr

on

V

V

V

GS

V

GS

R

Between lead,
6 mm (0.25") from
package and center
of die contact

MOSFET symbol
showing the
integral reverse
p - n junction diode

TJ = 25 °C, IF = 5.2 A, dI/dt = 100 A/μs

Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)

-62

-40

-2.5

VGS = 0, ID = 250 μA 200 - -

VDS = VGS, ID = 250 μA 1.0 - 2.0 V

= ± 10 V - - ± 100 nA

GS

VDS = 200 V, VGS = 0 V - - 25

= 320 V, VGS = 0 V, TJ = 125 °C - - 250

DS

= 10 V ID = 3.1 A

GS

= 4.0 V ID = 2.6 A

VDS = 50 V, ID = 3.1 A

VGS = 0 V,

V

= 25 V,

DS

f = 1.0 MHz, see fig. 5

b

b

b

- - 0.80

--1.0

1.2 - - S

-360-

--16

= 5.2 A, VDS = 160 V,

I

= 5.0 V

D

see fig. 6 and 13

b

-4.2-

= 100 V, ID = 5.2 A,

V

DD

= 9.0 , RD = 20, see fig. 10

g

b

-31-

-4.5-

-7.5-

--5.2

--21

TJ = 25 °C, IS = 5.2 A, VGS = 0 V

b

--1.8V

- 180 270 ns

b

-1.11.7μC

°C/W

V

μA



pFOutput Capacitance C

nC Gate-Source Charge Q

ns

nH

A

www.vishay.com Document Number: 91302
2 S11-1054-Rev. C, 30-May-11

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

This document is subject to change without notice.

www.vishay.com/doc?91000

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

IRL620S, SiHL620S

Vishay Siliconix

Fig. 1 - Typical Output Characteristics, TC = 25 °C

Fig. 2 - Typical Output Characteristics, T

= 150 °C

C

Fig. 3 - Typical Transfer Characteristics

Fig. 4 - Normalized On-Resistance vs. Temperature

Document Number: 91302 www.vishay.com
S11-1054-Rev. C, 30-May-11 3

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

This document is subject to change without notice.

www.vishay.com/doc?91000

IRL620S, SiHL620S

Vishay Siliconix

Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage

Fig. 7 - Typical Source-Drain Diode Forward Voltage

Fig. 8 - Maximum Safe Operating Area

www.vishay.com Document Number: 91302
4 S11-1054-Rev. C, 30-May-11

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

This document is subject to change without notice.

www.vishay.com/doc?91000

V

DS

90 %

10 %

V

GS

t

d(on)

t

r

t

d(off)

t

f

IRL620S, SiHL620S

Vishay Siliconix

R

D.U.T.

D

+

V

-

DD

V

DS

V

GS

R

g

5 V

Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %

Fig. 10a - Switching Time Test Circuit

Fig. 9 - Maximum Drain Current vs. Case Temperature

Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig. 10b - Switching Time Waveforms

Document Number: 91302 www.vishay.com
S11-1054-Rev. C, 30-May-11 5

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

www.vishay.com/doc?91000

IRL620S, SiHL620S

Q

GS

Q

GD

Q

G

V

G

Charge

5 V

D.U.T.

3 mA

V

GS

V

DS

I

G

I

D

0.3 µF

0.2 µF

50 kΩ

12 V

Current regulator

Current sampling resistors

Same type as D.U.T.

+

-

Vishay Siliconix

V

Var y tp to obtain
required I

AS

DS

R

g

D.U.T.

I

AS

5 V

L

t

p

0.01 W

Fig. 12a - Unclamped Inductive Test Circuit

V

(BR)DSS

t

p

+

V

DD

-

V

DS

I

AS

V

DD

Fig. 12b - Unclamped Inductive Waveforms

Fig. 12c - Maximum Avalanche Energy vs. Drain Current

Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit

www.vishay.com Document Number: 91302
6 S11-1054-Rev. C, 30-May-11

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

www.vishay.com/doc?91000

Peak Diode Recovery dV/dt Test Circuit

IRL620S, SiHL620S

Vishay Siliconix

D.U.T.

+

-

R

g

Driver gate drive

P.W.

+

-

Period

Circuit layout considerations

• Low stray inductance

• Ground plane

• Low leakage inductance

current transformer

• dV/dt controlled by R

• Driver same type as D.U.T.

I

controlled by duty factor “D”

•

SD

• D.U.T. - device under test

-

D =

g

Period

P.W.

+

+

V

DD

-

V

= 10 Va

GS

D.U.T. l

Reverse
recovery
current

D.U.T. V

Re-applied
voltage

Inductor current

Note

a. V

waveform

SD

Body diode forward

waveform

DS

Body diode forward drop

Ripple ≤ 5 %

= 5 V for logic level devices

GS

current

dI/dt

Diode recovery

dV/dt

V

DD

I

SD

Fig. 14 - For N-Channel

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91302

.

Document Number: 91302 www.vishay.com
S11-1054-Rev. C, 30-May-11 7

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

www.vishay.com/doc?91000

TO-263AB (HIGH VOLTAGE)

(Datum A)

34

E

L1

4

D

L2

4

C

1

B

B

C

3

2

B

B

Package Information

Vishay Siliconix

A

A

5

H

Detail A

B

A

c2

Gauge
plane

0° to 8°

L

L3

L4

Detail “A”
Rotated 90° CW
scale 8:1

H

B

Seating plane

A1

2 x e

Lead tip

2 x b2

2 x b

0.010 A B

MM

Plating

(c)

Section B - B and C - C

c

± 0.004 B

5

b1, b3

(b, b2)

Scale: none

M

Base
metal

c1

A

E

D1

4

5

E1

View A - A

4

MILLIMETERS INCHES MILLIMETERS INCHES

DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX.

A 4.06 4.83 0.160 0.190 D1 6.86 - 0.270 -

A1 0.00 0.25 0.000 0.010 E 9.65 10.67 0.380 0.420

b 0.51 0.99 0.020 0.039 E1 6.22 - 0.245 -

b1 0.51 0.89 0.020 0.035 e 2.54 BSC 0.100 BSC

b2 1.14 1.78 0.045 0.070 H 14.61 15.88 0.575 0.625

b3 1.14 1.73 0.045 0.068 L 1.78 2.79 0.070 0.110

c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.066

c1 0.38 0.58 0.015 0.023 L2 - 1.78 - 0.070

c2 1.14 1.65 0.045 0.065 L3 0.25 BSC 0.010 BSC

D 8.38 9.65 0.330 0.380 L4 4.78 5.28 0.188 0.208

ECN: S-82110-Rev. A, 15-Sep-08
DWG: 5970

Notes

1. Dimensioning and tolerancing per ASME Y14.5M-1994.

2. Dimensions are shown in millimeters (inches).

3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the
outmost extremes of the plastic body at datum A.

4. Thermal PAD contour optional within dimension E, L1, D1 and E1.

5. Dimension b1 and c1 apply to base metal only.

6. Datum A and B to be determined at datum plane H.

7. Outline conforms to JEDEC outline to TO-263AB.

Document Number: 91364 www.vishay.com
Revision: 15-Sep-08 1

RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead

0.420

(10.668)

0.635
(16.129)

0.355

AN826

Vishay Siliconix

(9.017)

Return to Index

0.135

(3.429)

0.200

(5.080)

Recommended Minimum Pads

Dimensions in Inches/(mm)

0.050

(1.257)

0.145

(3.683)

Document Number: 73397
11-Apr-05

www.vishay.com

1

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Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the
definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment
(EEE) - recast, unless otherwise specified as non-compliant.

Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.

Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free
requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21
conform to JEDEC JS709A standards.

Revision: 02-Oct-12

1

Document Number: 91000