Datasheet IRL540S, SiHL540S DataSheet (Vishay)

N-Channel MOSFET

G

D

S

Power MOSFET

IRL540S, SiHL540S

Vishay Siliconix

PRODUCT SUMMARY

VDS (V) 100

()V

R

DS(on)

Q

(Max.) (nC) 64

g

Q

(nC) 9.4

gs

Q

(nC) 27

gd

Configuration Single

= 5 V 0.077

GS

FEATURES

• Halogen-free According to IEC 61249-2-21
Definition

• Surface Mount

• Available in Tape and Reel

• Dynamic dV/dt Rating

• Repetitive Avalanche Rated

• Logic-Level Gate Drive

•R

• 175 °C Operating Temperature

Specified at VGS = 4 V and 5 V

DS(on)

• Compliant to RoHS Directive 2002/95/EC

DESCRIPTION

D2PAK (TO-263)

D

G

S

Third generation Power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.

2

The D

PAK (TO-263) is a surface mount power package
capable of accommodating die size up to HEX-4. It provides
the highest power capability and the lowest possible
on-resistance in any existing surface mount package. The

2

D

PAK (TO-263) is suitable for high current applications
because of its low internal connection resistance and can
dissipate up to 2.0 W in a typical surface mount application.

ORDERING INFORMATION

Package
Lead (Pb)-free and Halogen-free SiHL540S-GE3

Lead (Pb)-free

Note

a. See device orientation.

2

PAK (TO-263) D2PAK (TO-263)

D

SiHL540STRL-GE3
IRL540SPbF
SiHL540S-E3

IRL540STRLPbF

SiHL540STL-E3

a

a

a

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT

Drain-Source Voltage
Gate-Source Voltage

Continuous Drain Current

Pulsed Drain Current

a

V

GS

at 5 V

= 25 °C

T

C

= 100 °C

T

C

V

DS

V

GS

I

D

IDM

Linear Derating Factor 1.0

Linear Derating Factor (PCB Mount)
Single Pulse Avalanche Energy
Avalanche Current

a

Repetiitive Avalanche Energy
Maximum Power Dissipation

Maximum Power Dissipation (PCB Mount)
Peak Diode Recovery dV/dt
Operating Junction and Storage Temperature Range

e

b

a

= 25 °C

T

e

c

C

TA = 25 °C

E

AS

I

AR

E

AR

P

D

dV/dt 5.5 V/ns

, T

T

J

stg

Soldering Recommendations (Peak Temperature) for 10 s

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. V

= 25 V, starting TJ = 25 °C, L = 841 μH, Rg = 25 , IAS = 28 A (see fig. 12).

DD

c. I

 28 A, dI/dt  170 A/μs, VDD  VDS, TJ  175 °C.

SD

d. 1.6 mm from case.
e. When mounted on 1" square PCB (FR-4 or G-10 material).

100

± 10

28
20

110

0.025
440 mJ

28 A
15 mJ

150

3.7

- 55 to + 175

d

300

V

A

W/°C

W

°C

* Pb containing terminations are not RoHS compliant, exemptions may apply

Document Number: 90386

www.vishay.com

S11-1045-Rev. C, 30-May-11 1

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

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D

G

IRL540S, SiHL540S

Vishay Siliconix

THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL TYP. MAX. UNIT

Maximum Junction-to-Ambient R

Maximum Junction-to-Ambient
(PCB Mount)

a

Maximum Junction-to-Case (Drain) R

thJA

R

thJA

thJC

Note

a. When mounted on 1" square PCB (FR-4 or G-10 material).

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

Static

Drain-Source Breakdown Voltage V

Temperature Coefficient VDS/TJ Reference to 25 °C, ID = 1 mA - 0.12 - V/°C

V

DS

Gate-Source Threshold Voltage V

Gate-Source Leakage I

Zero Gate Voltage Drain Current I

Drain-Source On-State Resistance R

Forward Transconductance g

Dynamic

Input Capacitance C

Reverse Transfer Capacitance C

Total Gate Charge Q

Gate-Drain Charge Q

Turn-On Delay Time t

Rise Time t

Turn-Off Delay Time t

Fall Time t

Internal Drain Inductance L

Internal Source Inductance L

Drain-Source Body Diode Characteristics

Continuous Source-Drain Diode Current I

Pulsed Diode Forward Current

a

Body Diode Voltage V

Body Diode Reverse Recovery Time t

Body Diode Reverse Recovery Charge Q

Forward Turn-On Time t

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width  300 μs; duty cycle  2 %.

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2 S11-1045-Rev. C, 30-May-11

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

DS

GS(th)

V

GSS

DSS

DS(on)

fs

iss

- 560 -

oss

- 140 -

rss

g

--9.4

gs

--27

gd

d(on)

r

-35-

d(off)

-80-

f

D

V

V

GS

V

GS

V

GS

R

Between lead,
6 mm (0.25") from
package and center of

S

S

I

SM

SD

rr

rr

on

die contact

MOSFET symbol
showing the
integral reverse
p - n junction diode

TJ = 25 °C, IF = 28 A, dI/dt = 100 A/μs

This document is subject to change without notice.

-62

-40

°C/W

-1.0

VGS = 0, ID = 250 μA 100 - - V

VDS = VGS, ID = 250 μA 1.0 - 2.0 V

= ± 10 V - - ± 100 nA

GS

VDS = 100 V, VGS = 0 V - - 25

= 80 V, VGS = 0 V, TJ = 150 °C - - 250

DS

= 5 V ID = 17 A

= 4 V ID = 14 A

VDS = 50 V, ID = 17 A

VGS = 0 V,

V

= 25 V,

DS

f = 1.0 MHz, see fig. 5

b

b

b

- - 0.077

- - 0.11

12 - - S

- 2200 -

--64

= 28 A, VDS = 80 V,

I

= 5 V

D

see fig. 6 and 13

b

-8.5-

V

= 50 V, ID = 28 A,

DD

= 9.0 , RD = 1.7 , see fig. 10

g

b

- 170 -

-4.5-

-7.5-

G

TJ = 25 °C, IS = 28 A, VGS = 0 V

D

S

b

--28

- - 110

--2.5V

- 200 260 ns

b

-1.72.9μC

Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)

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μA



pFOutput Capacitance C

nC Gate-Source Charge Q

ns

nH

A

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

IRL540S, SiHL540S

Vishay Siliconix

Fig. 1 - Typical Output Characteristics, TC = 25 °C

Fig. 2 - Typical Output Characteristics, T

= 175 °C

C

Fig. 3 - Typical Transfer Characteristics

Fig. 4 - Normalized On-Resistance vs. Temperature

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THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

This document is subject to change without notice.

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IRL540S, SiHL540S

Vishay Siliconix

Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage

Fig. 7 - Typical Source-Drain Diode Forward Voltage

Fig. 8 - Maximum Safe Operating Area

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V

DS

90 %

10 %

V

GS

t

d(on)

t

r

t

d(off)

t

f

R

g

I

AS

0.01 Ω

t

p

D.U.T.

L

V

DS

+

-

V

DD

5 V

Var y t

p

to obtain

required I

AS

I

AS

V

DS

V

DD

V

DS

t

p

IRL540S, SiHL540S

Vishay Siliconix

R

D.U.T.

D

+

V

-

DD

V

DS

V

GS

R

g

5 V

Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %

Fig. 10a - Switching Time Test Circuit

Fig. 9 - Maximum Drain Current vs. Case Temperature

Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig. 10b - Switching Time Waveforms

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Fig. 12a - Unclamped Inductive Test Circuit

Fig. 12b - Unclamped Inductive Waveforms

This document is subject to change without notice.

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IRL540S, SiHL540S

D.U.T.

3 mA

V

GS

V

DS

I

G

I

D

0.3 µF

0.2 µF

50 kΩ

12 V

Current regulator

Current sampling resistors

Same type as D.U.T.

+

-

Vishay Siliconix

Fig. 12c - Maximum Avalanche Energy vs. Drain Current

Q

V

GS

Q

GS

V

G

G

Q

GD

Charge

Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit

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Peak Diode Recovery dV/dt Test Circuit

IRL540S, SiHL540S

Vishay Siliconix

D.U.T.

+

-

R

g

Driver gate drive

P.W.

+

-

Period

Circuit layout considerations

• Low stray inductance

• Ground plane

• Low leakage inductance

current transformer

• dV/dt controlled by R

• Driver same type as D.U.T.

I

controlled by duty factor “D”

•

SD

• D.U.T. - device under test

-

D =

g

Period

P.W.

+

+

V

DD

-

V

= 10 Va

GS

D.U.T. l

Reverse
recovery
current

D.U.T. V

Re-applied
voltage

Inductor current

Note

a. V

waveform

SD

Body diode forward

waveform

DS

Body diode forward drop

Ripple ≤ 5 %

= 5 V for logic level devices

GS

current

dI/dt

Diode recovery

dV/dt

V

DD

I

SD

Fig. 14 - For N-Channel

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?90386

.

Document Number: 90386 www.vishay.com
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This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

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TO-263AB (HIGH VOLTAGE)

(Datum A)

34

E

L1

4

D

L2

4

C

1

B

B

C

3

2

B

B

Package Information

Vishay Siliconix

A

A

5

H

Detail A

B

A

c2

Gauge
plane

0° to 8°

L

L3

L4

Detail “A”
Rotated 90° CW
scale 8:1

H

B

Seating plane

A1

2 x e

Lead tip

2 x b2

2 x b

0.010 A B

MM

Plating

(c)

Section B - B and C - C

c

± 0.004 B

5

b1, b3

(b, b2)

Scale: none

M

Base
metal

c1

A

E

D1

4

5

E1

View A - A

4

MILLIMETERS INCHES MILLIMETERS INCHES

DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX.

A 4.06 4.83 0.160 0.190 D1 6.86 - 0.270 -

A1 0.00 0.25 0.000 0.010 E 9.65 10.67 0.380 0.420

b 0.51 0.99 0.020 0.039 E1 6.22 - 0.245 -

b1 0.51 0.89 0.020 0.035 e 2.54 BSC 0.100 BSC

b2 1.14 1.78 0.045 0.070 H 14.61 15.88 0.575 0.625

b3 1.14 1.73 0.045 0.068 L 1.78 2.79 0.070 0.110

c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.066

c1 0.38 0.58 0.015 0.023 L2 - 1.78 - 0.070

c2 1.14 1.65 0.045 0.065 L3 0.25 BSC 0.010 BSC

D 8.38 9.65 0.330 0.380 L4 4.78 5.28 0.188 0.208

ECN: S-82110-Rev. A, 15-Sep-08
DWG: 5970

Notes

1. Dimensioning and tolerancing per ASME Y14.5M-1994.

2. Dimensions are shown in millimeters (inches).

3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the
outmost extremes of the plastic body at datum A.

4. Thermal PAD contour optional within dimension E, L1, D1 and E1.

5. Dimension b1 and c1 apply to base metal only.

6. Datum A and B to be determined at datum plane H.

7. Outline conforms to JEDEC outline to TO-263AB.

Document Number: 91364 www.vishay.com
Revision: 15-Sep-08 1

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

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Revision: 13-Jun-16

1

Document Number: 91000