Datasheet SiHG22N60S DataSheet (Vishay)

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TO-247AC

G

D

S

SiHG22N60S

Vishay Siliconix

S Series Power MOSFET

PRODUCT SUMMARY

VDS at TJ max. (V) 650

R

max. at 25 °C (Ω)VGS = 10 V 0.190

DS(on)

Q

max. (nC) 98

g

Q

(nC) 17

gs

Q

(nC) 25

gd

Configuration Single

FEATURES

• Generation one

• High EAR capability

• Lower figure-of-merit R

• 100 % avalanche tested

• Ultra low R

• dV/dt ruggedness

• Ultra low gate charge (Qg)

D

• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912

APPLICATIONS

G

S

N-Channel MOSFET

• PFC power supply stages

• Hard switching topologies

• Solar inverters

•UPS

• Motor control

• Lighting

• Server telecom

ORDERING INFORMATION

Package TO-247AC

Lead (Pb)-free SiHG22N60S-E3

Lead (Pb)-free and Halogen-free SiHG22N60S-GE3

x Q

on

g

on

Available

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT

Drain-Source Voltage V

Gate-Source Voltage V

T

= 25 °C

Continuous Drain Current V

Pulsed Drain Current

a

at 10 V

GS

C

= 100 °C 13

C

DS

± 30

GS

I

D

IDM 65

Linear Derating Factor TO-247 2 W/°C

Single Pulse Avalanche Energy

Repetitive Avalanche Energy

Maximum Power Dissipation TO-247 P

Drain-Source Voltage Slope T

Reverse Diode dV/dt

d

Operating Junction and Storage Temperature Range T

Soldering Recommendations (Peak Temperature)

b

a

= 125 °C

J

c

for 10 s 300

E

AS

E

AR

D

dV/dt

, T

J

stg

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature.

= 50 V, starting TJ = 25 °C, L = 28.2 mH, Rg = 25 Ω, IAS = 7 A.

b. V

DD

c. 1.6 mm from case.
d. I

≤ ID, dI/dt = 100 A/μs, starting TJ = 25 °C.

SD

S15-0982-Rev. H, 27-Apr-15

1

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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

600

22

690

25

250 W

37

5.3

-55 to +150

Document Number: 91393

V

AT

mJ

V/ns

°C

SiHG22N60S

S

D

G

www.vishay.com

THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL TYP. MAX. UNIT

Maximum Junction-to-Ambient TO-247 R

Maximum Junction-to-Case (Drain) TO-247 R

thJA

thJC

-62

-0.5

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

Static

Drain-Source Breakdown Voltage V

V

Temperature Coefficient ΔVDS/TJ Reference to 25 °C, ID = 1 mA - 0.70 - V/°C

DS

Gate-Source Threshold Voltage (N) V

Gate-Source Leakage I

Zero Gate Voltage Drain Current I

Drain-Source On-State Resistance R

Forward Transconductance

a

g

DS

GS(th)

GSS

DSS

VGS = 10 V ID = 11 A - 0.160 0.190 Ω

DS(on)

fs

Dynamic

Input Capacitance C

Reverse Transfer Capacitance C

Total Gate Charge Q

iss

296 1480 2960

oss

6.6 33 66

rss

g

V

Gate-Drain Charge Q

Turn-On Delay Time t

Rise Time t

Turn-Off Delay Time t

Fall Time t

Gate Input Resistance R

-25-

gd

d(on)

r

- 77 115

d(off)

-5990

f

g

Drain-Source Body Diode Characteristics

Continuous Source-Drain Diode Current I

Pulsed Diode Forward Current I

Diode Forward Voltage V

Reverse Recovery Time t

Reverse Recovery Charge Q

Reverse Recovery Current I

S

SM

SD

rr

rr

RRM

MOSFET symbol
showing the
integral reverse
p - n junction diode

Note

a. C

(TR) is a fixed capacitance that gives the same charging time as C

oss eff.

VGS = 0 V, ID = 1 mA 600 - - V

VDS = VGS, ID = 250 μA 2.0 - 4.0 V

V

= ± 20 V - - ± 100 nA

GS

V

= ± 30 V - - ± 1 μA

GS

VDS = 600 V, VGS = 0 V - - 1

= 600 V, VGS = 0 V, TJ = 150 °C - - 100

V

DS

VDS = 50 V, ID = 13 A - 9.4 - S

VGS = 0 V,

V

= 25 V,

DS

f = 1.0 MHz

= 10 V ID = 22 A, VDS = 480 V

GS

= 380 V, ID = 22 A,

V

DD

R

= 9.1 Ω, VGS = 10 V

g

f = 1 MHz, open drain 0.13 0.65 1.3 Ω

TJ = 25 °C, IS = 22 A, VGS = 0 V - - 1.2 V

TJ = 25 °C, IF = IS,

dI/dt = 100 A/μs, V

while VDS is rising from 0 % to 80 % VDS.

oss

= 25 V

R

Vishay Siliconix

°C/W

562 2810 5620

- 75 110

-2450

- 68 100

--22

--65

-462-ns

-8.3-μC

-30-A

μA

pFOutput Capacitance C

nC Gate-Source Charge Qgs -17-

ns

A

S15-0982-Rev. H, 27-Apr-15

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VDS, Drain-to-Source Voltage (V)

I

D

, Drain Current (A)

0

10

20

30

40

50

04812162024

V

GS

Top 15 V

14 V
13 V
12 V
11 V
10 V

9 V

8 V
7 V
6 V
5 V

Bottom 4 V

TJ = 25 °C

4 V

0

6

12

18

24

30

0 4 8 12162024

4.0 V

VDS, Drain-to-Source Voltage (V)

I

D

, Drain Current (A)

V

GS

Top 15 V

14 V
13 V
12 V
11 V
10 V

9 V

8 V
7 V
6 V
5 V

Bottom 4 V

TJ = 150 °C

I

D

, Drain Current (A)

V

GS

,

Gate-to-Source Voltage (V)

0

10

20

30

40

50

60

46810

TJ = 25 °C

TJ = 150 °C

2

10

100

1000

10 000

100 000

110100

Capacitance (pF)

V

DS

,

Drain-to-Source Voltage (V)

VGS = 0 V, f = 1 MHz
C

iss

= Cgs + Cgd • C

ds

shorted

C

rss

= C

gd

C

oss

= Cds + C

gd

C

rss

C

iss

C

oss

0.0

2.0

4.0

6.0

8.0

10.0

12.0

0102030405060708090100

V

DS

= 120 V

V

DS

= 300 V

V

DS

= 480 V

ID = 22 A

QG, Total Gate Charge (nC)

V

GS

, Gate-to-Source Voltage (V)

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

SiHG22N60S

Vishay Siliconix

3.5

I

= 22 A

3

D

= 10 V

V

2.5

1.5

(Normalized)

, Drain-to-Source On Resistance

0.5

DS(on)

R

GS

2

1

0

- 60 - 40 - 20 0 20 40 60 80 100 120 140 160 180

T

Junction Temperature (°C)

,

J

Fig. 1 - Typical Output Characteristics, TJ = 25 °C

Fig. 2 - Typical Output Characteristics, T

= 150 °C

J

Fig. 4 - Normalized On-Resistance vs. Temperature

Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

S15-0982-Rev. H, 27-Apr-15

Fig. 3 - Typical Transfer Characteristics

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Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage

3

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0.1

1

10

100

1000

1 10 100 1000 10 000

100 µs

Operation in this area limited

by R

DS(on)

TC = 25 °C
T

J

= 150 °C

Single Pulse

VDS, Drain-to-Source Voltage (V)

I

D

, Drain Current (A)

1 ms

10 ms

550

575

600

625

650

675

700

725

- 60 - 40 - 20 0 20 40 60 80 100 120 140160 180

T

J

,

Junction Temperature (°C)

V

DS

,

Drain-to-Source Breakdown

Voltage (V)

SiHG22N60S

Vishay Siliconix

1000

100

10

= 150 °C

T

J

1

0.1

0.01

T

J

= 25 °C

, Reverse Drain Current (A)

SD

0.001

I

V

= 0 V

0.0001

0.2 0.4 0.6 0.8 1 1.2 1.4

GS

VSD, Source-to-Drain Voltage (V)

Fig. 7 - Typical Source-Drain Diode Forward Voltage

25

20

15

10

, Drain Current (A)

D

I

5

0

25 50 75 100 125 150

TC, Case Temperature (°C)

Fig. 9 - Maximum Drain Current vs. Case Temperature

Fig. 8 - Maximum Safe Operating Area

1

0.1

S15-0982-Rev. H, 27-Apr-15

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

normalized Effective Transient

Thermal Impedance

0.01

Fig. 10 - Drain-to-Source Breakdown Voltage

Duty Cycle = 0.5

0.2

0.1

0.05

0.02

Single Pulse

-4

10

-3

10

-2

10

0.1 1

Square Wave Pulse Duration (s)

Fig. 11 - Normalized Thermal Transient Impedance, Junction-to-Case

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Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %

R

D

V

GS

R

g

D.U.T.

10 V

+

-

V

DS

V

DD

90 %

10 %

t

d(on)

t

r

t

d(off)

t

f

R

g

I

AS

0.01 Ω

t

p

D.U.T

L

V

DS

+

-

V

DD

10 V

Var y t

p

to obtain

required I

AS

Q

GS

Q

GD

Q

G

V

G

Charge

V

GS

SiHG22N60S

Vishay Siliconix

Fig. 12 - Switching Time Test Circuit

V

DS

V

GS

Fig. 13 - Switching Time Waveforms

Fig. 16 - Basic Gate Charge Waveform

Current regulator

Same type as D.U.T.

50 kΩ

0.2 µF

12 V

V

GS

0.3 µF

D.U.T.

3 mA

I

G

Current sampling resistors

I

D

+

V

DS

-

Fig. 17 - Gate Charge Test Circuit

Fig. 14 - Unclamped Inductive Test Circuit

Fig. 15 - Unclamped Inductive Waveforms

S15-0982-Rev. H, 27-Apr-15

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

V

DS

t

p

V

DS

I

AS

V

DD

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

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SiHG22N60S

Vishay Siliconix

Peak Diode Recovery dV/dt Test Circuit

D.U.T.

+

-

R

g

Driver gate drive

P.W.

+

-

Period

Circuit layout considerations

• Low stray inductance

• Ground plane

• Low leakage inductance

current transformer

• dV/dt controlled by R

• Driver same type as D.U.T.

I

controlled by duty factor “D”

•

SD

• D.U.T. - device under test

-

D =

g

Period

P.W.

+

+

V

DD

-

= 10 Va

V

GS

D.U.T. l

Reverse
recovery
current

D.U.T. V

Re-applied
voltage

Inductor current

Note

a. V

waveform

SD

Body diode forward

waveform

DS

Body diode forward drop

Ripple ≤ 5 %

= 5 V for logic level devices

GS

current

dI/dt

Diode recovery

dV/dt

V

DD

I

SD

Fig. 18 - For N-Channel

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91393

.

S15-0982-Rev. H, 27-Apr-15

6

Document Number: 91393

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0.10 AC

M M

E

E/2

(2)

(4)

R/2

B

2 x R

S

D

See view B

2 x e

b4

3 x b

2 x b2

L

C

L1

1

2

3

Q

D

A

A2

A

A

A1

C

Ø k BD

M M

A

ØP

(Datum B)

ØP1

D1

4

E1

0.01 BD

M M

View A - A

Thermal pad

D2

DDE E

C

C

View B

(b1, b3, b5)

Base metal

c1

(b, b2, b4)

Section C - C, D - D, E - E

(c)

Planting

4

3

5

7

4

4

4

Lead Assignments

1. Gate

2. Drain

3. Source

4. Drain

Package Information

Vishay Siliconix

TO-247AC (High Voltage)

MILLIMETERS INCHES MILLIMETERS INCHES

DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX.

A 4.58 5.31 0.180 0.209 D2 0.51 1.30 0.020 0.051
A1 2.21 2.59 0.087 0.102 E 15.29 15.87 0.602 0.625
A2 1.17 2.49 0.046 0.098 E1 13.72 - 0.540 -

b 0.99 1.40 0.039 0.055 e 5.46 BSC 0.215 BSC
b1 0.99 1.35 0.039 0.053 Ø k 0.254 0.010
b2 1.53 2.39 0.060 0.094 L 14.20 16.25 0.559 0.640
b3 1.65 2.37 0.065 0.093 L1 3.71 4.29 0.146 0.169
b4 2.42 3.43 0.095 0.135 N 7.62 BSC 0.300 BSC
b5 2.59 3.38 0.102 0.133 Ø P 3.51 3.66 0.138 0.144

c 0.38 0.86 0.015 0.034 Ø P1 - 7.39 - 0.291
c1 0.38 0.76 0.015 0.030 Q 5.31 5.69 0.209 0.224

D 19.71 20.82 0.776 0.820 R 4.52 5.49 0.178 0.216
D1 13.08 - 0.515 - S 5.51 BSC 0.217 BSC

ECN: X13-0103-Rev. D, 01-Jul-13
DWG: 5971

Notes

1. Dimensioning and tolerancing per ASME Y14.5M-1994.

2. Contour of slot optional.

3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at
the outermost extremes of the plastic body.

4. Thermal pad contour optional with dimensions D1 and E1.

5. Lead finish uncontrolled in L1.

6. Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154").

7. Outline conforms to JEDEC outline TO-247 with exception of dimension c.

8. Xian and Mingxin actually photo.

Revision: 01-Jul-13

Document Number: 91360

1

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

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particular product with the properties described in the product specification is suitable for use in a particular application.
Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over
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including but not limited to the warranty expressed therein.

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Revision: 13-Jun-16

1

Document Number: 91000