Datasheet SIHG20N50CE3 Specification

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N-Channel MOSFET
G
D
S
TO-247
G
D
S
PRODUCT SUMMARY
VDS (V) at TJ max. 560
R
(Ω)V
DS(on)
Q
max. (nC) 76
g
Q
(nC) 21
gs
Q
(nC) 34
gd
Configuration Single
= 10 V 0.270
GS
Power MOSFET
FEATURES
• Low figure-of-merit Ron x Q
• 100 % avalanche tested
• High peak current capability
• dv/dt ruggedness
• Improved T
• Improved gate charge
• High power dissipations capability
• Material categorization: for definitions of compliance please see www.vishay.com/doc?99912
SiHG20N50C
Vishay Siliconix
g
Available
rr/Qrr
ORDERING INFORMATION
Package TO-247AC
Lead (Pb)-free SiHG20N50C-E3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER SYMBOL LIMIT UNIT
Drain-source voltage V
Gate-source voltage V
T
= 25 °C
Continuous drain current (T
Pulsed drain current
b
= 150 °C)
J
a
VGS at 10 V
C
= 100 °C 11
C
DS
± 30
GS
I
D
IDM 80
Linear derating factor 1.8 W/°C
Single pulse avalanche energy
Maximum power dissipation P
Reverse diode dV/dt
d
Operating junction and storage temperature range T
Soldering recommendations (peak temperature)
c
E
AS
D
dV/dt 5 V/ns
, T
J
d
For 10 s 300
stg
Notes
a. Limited by maximum junction temperature b. Repetitive rating; pulse width limited by maximum junction temperature c. V
= 50 V, starting TJ = 25 °C, L = 2.5 mH, Rg = 25 Ω, IAS = 17 A
DD
d. I
18 A, di/dt 380 A/μs, VDD VDS, TJ 150 °C
SD
e. 1.6 mm from case
500
20
361 mJ
250 W
-55 to +150
V
AT
°C
THERMAL RESISTANCE RATINGS
PARAMETER SYMBOL TYP. MAX. UNIT
Maximum junction-to-ambient R
Maximum junction-to-case (drain) R
thJA
thJC
S21-0453-Rev. E, 10-May-2021
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-40
-0.5
1
Document Number: 91382
°C/W
Page 2
SiHG20N50C
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SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-source breakdown voltage V
V
temperature coefficient ΔVDS/T
DS
Gate-source threshold voltage (N) V
Gate-source leakage I
Zero gate voltage drain current I
Drain-source on-state resistance R
Forward transconductance g
Dynamic
Input capacitance C
Reverse transfer capacitance C
Total gate charge Q
Gate-drain charge Q
Turn-on delay time t
Rise time t
Turn-off delay time t
Fall time t
Gate input resistance R
Drain-Source Body Diode Characteristics
Continuous source-drain diode current I
Pulsed diode forward current I
DS
GS(th)
GSS
DSS
DS(on)
fs
iss
oss
rss
g
-29-
gd
d(on)
r
d(off)
f
g
S
SM
VGS = 0 V, ID = 250 μA 500 - - V
Reference to 25 °C, ID = 1 mA - 0.7 - V/°C
J
VDS = VGS, ID = 250 μA 3.0 - 5.0 V
VGS = ± 30 V - - ± 100 nA
VDS = 500 V, VGS = 0 V - - 25
= 400 V, VGS = 0 V, TJ = 125 °C - - 250
V
DS
VGS = 10 V ID = 10 A - 0.225 0.270 Ω
VDS = 50 V, ID = 10 A - 6.4 - S
VGS = 0 V, V
= 25 V,
DS
f = 1 MHz
VGS = 10 V ID = 18 A, VDS = 400 V
VDD = 250 V, ID = 18 A, Rg = 9.1 Ω
f = 1 MHz, open drain - 1.1 - Ω
MOSFET symbol showing the
integral reverse p - n junction diode
D
G
S
Vishay Siliconix
- 2451 2942
- 300 360
-2632
-6576
-80-
-27-
-32-
-44-
--20
--80
μA
pFOutput capacitance C
nCGate-source charge Qgs -21-
ns
A
Diode forward voltage V
Reverse recovery time t
Reverse recovery charge Q
Reverse recovery current I
S21-0453-Rev. E, 10-May-2021
SD
rr
rr
RRM
TJ = 25 °C, IS = 18 A, VGS = 0 V - - 1.5 V
TJ = 25 °C, IF = IS, di/dt = 100 A/μs
, V
2
= 35 V
R
-503- ns
-6.7-μC
-30- A
Document Number: 91382
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VDS, Drain-to-Source Voltage (V)
I
D
, Drain Current (A)
0
10
20
30
40
50
60
70
0612 18
24
30
7.0 V
Bottom
To p
V
GS
15 V 14 V 13 V 12 V 11 V 10 V
9.0 V
8.0 V
7.0 V
6.0 V
5.0 V
TJ = 25 °C
0
10
20
30
40
0 6 12 18 24 30
7.0 V
VDS, Drain-to-Source Voltage (V)
I
D
, Drain Current (A)
Bottom
To p
V
GS
15 V 14 V 13 V 12 V 11 V 10 V
9.0 V
8.0 V
7.0 V
6.0 V
5.0 V
TJ = 150 °C
T
J
,
Junction Temperature (°C)
R
DS(on)
, Drain-to-Source On Resistance
(Normalized)
0
0.5
1
1.5
2
2.5
3
- 60 - 40 - 20 0 20 40 60 80 100 120 140 160
ID = 17 A
V
GS
= 10 V
QG, Total Gate Charge (nC)
V
GS
, Gate-to-Source Voltage (V)
0
4
8
12
16
20
0306090120
ID = 17 A
V
DS
= 250 V
V
DS
= 100 V
V
DS
= 400 V
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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
SiHG20N50C
Vishay Siliconix
Fig. 1 - Typical Output Characteristics, TC = 25 °C
Fig. 2 - Typical Output Characteristics, T
100
TJ= 150 °C
10
= 150 °C
C
Fig. 4 - Normalized On-Resistance vs. Temperature
5
10
4
10
3
10
Capacitance (pF)
2
10
10
1101001000
V
Drain-to-Source Voltage (V)
,
DS
V
= 0 V, f = 1 MHz
GS
= Cgs + Cgd, Cds Shorted
C
iss
= C
C
rss
gd
C
= Cds + C
oss
gd
C
iss
C
oss
C
rss
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
1
, Drain Current (A)
D
0.1
I
0.01
Fig. 3 - Typical Transfer Characteristics
S21-0453-Rev. E, 10-May-2021
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
T
= 25 °C
J
5678910
V
Gate-to-Source Voltage (V)
,
GS
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
3
Document Number: 91382
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VSD, Source-to-Drain Voltage (V)
I
SD
, Reverse Drain Current (A)
0.1
1
10
100
0.2 0.5 0.8 1.1 1.4
TJ = 150 °C
T
J
= 25 °C
V
GS
= 0 V
VDS, Drain-to-Source Voltage (V)
I
D
, Drain Current (A)
TC = 25 °C T
J
= 150 °C
Single Pulse
Operation in this area limited
by R
DS(on)
1 ms
10 ms
100 µs
1000
1
10
100
10
100 1000
10 000
0.1
I
D
, Drain Current (A)
TC, Case Temperature (°C)
0
5
10
15
20
25 50 75 100 125 150
10
-4
10
-3
10
-2
0.1 1
Normalized Effective Transient
Thermal Impedance
0.01
0.1
1
Pulse Time (s)
Single Pulse
0.02
0.05
0.1
0.2
Duty Cycle = 0.5
SiHG20N50C
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Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 8 - Maximum Safe Operating Area
Vishay Siliconix
S21-0453-Rev. E, 10-May-2021
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 10 - Normalized Thermal Transient Impedance, Junction-to-Case (TO-247)
4
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Document Number: 91382
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Pulse width 1 µs Duty factor 0.1 %
R
D
V
GS
R
g
D.U.T.
10 V
+
-
V
DS
V
DD
90 %
10 %
t
d(on)
t
r
t
d(off)
t
f
R
g
I
AS
0.01 Ω
t
p
D.U.T
L
V
DS
+
-
V
DD
10 V
Var y tp to obtain required I
AS
Q
GS
Q
GD
Q
G
V
G
Charge
10 V
Fig. 11 - Switching Time Test Circuit
SiHG20N50C
Vishay Siliconix
Fig. 15 - Basic Gate Charge Waveform
V
DS
V
GS
Fig. 12 - Switching Time Waveforms
Fig. 13 - Unclamped Inductive Test Circuit
Current regulator
Same type as D.U.T.
50 kΩ
0.2 µF
12 V
0.3 µF
D.U.T.
V
GS
3 mA
I
G
Current sampling resistors
I
D
Fig. 16 - Gate Charge Test Circuit
+
V
DS
-
V
DS
t
p
V
DS
I
AS
V
DD
Fig. 14 - Unclamped Inductive Waveforms
S21-0453-Rev. E, 10-May-2021
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Document Number: 91382
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SiHG20N50C
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
D.U.T.
+
-
R
g
Driver gate drive
P.W.
+
-
Period
Circuit layout considerations
Low stray inductance
Ground plane
Low leakage inductance
current transformer
dV/dt controlled by R
Driver same type as D.U.T.
I
controlled by duty factor “D”
SD
D.U.T. - device under test
-
D =
g
Period
P.W.
+
+
V
DD
-
V
= 10 Va
GS
D.U.T. l
waveform
SD
Reverse recovery current
Re-applied voltage
D.U.T. V
Inductor current
Note
a. V
waveform
DS
= 5 V for logic level devices
GS
Body diode forward
current
dI/dt
Diode recovery
dV/dt
Body diode forward drop
Ripple 5 %
V
DD
I
SD
Fig. 17 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91382
S21-0453-Rev. E, 10-May-2021
.
6
Document Number: 91382
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VERSION 1: FACILITY CODE = 9
Package Information
Vishay Siliconix
TO-247AC (High Voltage)
MILLIMETERS MILLIMETERS
DIM. MIN. MAX. NOTES DIM. MIN. MAX. NOTES
A 4.83 5.21 D1 16.25 16.85 5
A1 2.29 2.55 D2 0.56 0.76
A2 1.50 2.49 E 15.50 15.87 4
b 1.12 1.33 E1 13.46 14.16 5
b1 1.12 1.28 E2 4.52 5.49 3
b2 1.91 2.39 6 e 5.44 BSC
b3 1.91 2.34 L 14.90 15.40
b4 2.87 3.22 6, 8 L1 3.96 4.16 6
b5 2.87 3.18 Ø P 3.56 3.65 7
c 0.55 0.69 6 Ø P1 7.19 ref.
c1 0.55 0.65 Q 5.31 5.69
D 20.40 20.70 4 S 5.54 5.74
Notes
(1)
Package reference: JEDEC® TO247, variation AC
(2)
All dimensions are in mm
(3)
Slot required, notch may be rounded
(4)
Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm per side. These dimensions are measured at the outermost extremes of the plastic body
(5)
Thermal pad contour optional with dimensions D1 and E1
(6)
Lead finish uncontrolled in L1
(7)
Ø P to have a maximum draft angle of 1.5° to the top of the part with a maximum hole diameter of 3.91 mm
(8)
Dimension b2 and b4 does not include dambar protrusion. Allowable dambar protrusion shall be 0.1 mm total in excess of b2 and b4 dimension at maximum material condition
Revision: 19-Oct-2020
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
1
Document Number: 91360
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0.10 AC
M M
E
E/2
(2)
(4)
R/2
B
2 x R
S
D
See view B
2 x e
b4
3 x b
2 x b2
L
C
L1
1
2
3
Q
D
A
A2
A
A
A1
C
Ø k BD
M M
A
ØP
(Datum B)
ØP1
D1
4
E1
0.01 BD
M M
View A - A
Thermal pad
D2
DDE E
C
C
View B
(b1, b3, b5)
Base metal
c1
(b, b2, b4)
Section C - C, D - D, E - E
(c)
Planting
4
3
5
7
4
4
4
Lead Assignments
1. Gate
2. Drain
3. Source
4. Drain
VERSION 2: FACILITY CODE = Y
Package Information
Vishay Siliconix
MILLIMETERS MILLIMETERS
DIM. MIN. MAX. NOTES DIM. MIN. MAX. NOTES
A 4.58 5.31 D2 0.51 1.30
A1 2.21 2.59 E 15.29 15.87
A2 1.17 2.49 E1 13.72 -
b 0.99 1.40 e 5.46 BSC
b1 0.99 1.35 Ø k 0.254
b2 1.53 2.39 L 14.20 16.25
b3 1.65 2.37 L1 3.71 4.29
b4 2.42 3.43 Ø P 3.51 3.66
b5 2.59 3.38 Ø P1 - 7.39
c 0.38 0.86 Q 5.31 5.69
c1 0.38 0.76 R 4.52 5.49
D 19.71 20.82 S 5.51 BSC
D1 13.08 -
Notes
(1)
Dimensioning and tolerancing per ASME Y14.5M-1994
(2)
Contour of slot optional
(3)
Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outermost extremes of the plastic body
(4)
Thermal pad contour optional with dimensions D1 and E1
(5)
Lead finish uncontrolled in L1
(6)
Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154")
(7)
Outline conforms to JEDEC outline TO-247 with exception of dimension c
Revision: 19-Oct-2020
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Document Number: 91360
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c1
c
b, b2, b4
Plating
Base metal
b1, b3, b5
0.01 M
DB
E1
D1
P
A
P1
D2
K
A2
D
A
A1
C
b2
b
b4
e
L
C
L1
D
S
R
Q
N
R/2
E
B
M
M
DB
M
0.10 MCAM
VERSION 3: FACILITY CODE = N
Package Information
Vishay Siliconix
MILLIMETERS MILLIMETERS
DIM. MIN. MAX. DIM. MIN. MAX.
A 4.65 5.31 D2 0.51 1.35
A1 2.21 2.59 E 15.29 15.87
A2 1.17 1.37 E1 13.46 -
b 0.99 1.40 e 5.46 BSC
b1 0.99 1.35 k 0.254
b2 1.65 2.39 L 14.20 16.10
b3 1.65 2.34 L1 3.71 4.29
b4 2.59 3.43 N 7.62 BSC
b5 2.59 3.38 P 3.56 3.66
c 0.38 0.89 P1 - 7.39
c1 0.38 0.84 Q 5.31 5.69
D 19.71 20.70 R 4.52 5.49
D1 13.08 - S 5.51 BSC
ECN: E20-0545-Rev. F, 19-Oct-2020 DWG: 5971
Notes
(1)
Dimensioning and tolerancing per ASME Y14.5M-1994
(2)
Contour of slot optional
(3)
Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outermost extremes of the plastic body
(4)
Thermal pad contour optional with dimensions D1 and E1
(5)
Lead finish uncontrolled in L1
(6)
Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154")
Revision: 19-Oct-2020
3
Document Number: 91360
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Disclaimer
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