Datasheet IRFZ48S, IRFZ48L, SiHFZ48S, SiHFZ48L DataSheet (Vishay)

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D2PAK (TO-263)

G

D

S

I2PAK (TO-262)

G

D

S

Available

Available

IRFZ48S, IRFZ48L, SiHFZ48S, SiHFZ48L

Vishay Siliconix

Power MOSFET

PRODUCT SUMMARY

VDS (V) 60

R

()V

DS(on)

Q

(Max.) (nC) 110

g

Q

(nC) 29

gs

Q

(nC) 36

gd

Configuration Single

GS

= 10 V 0.018

D

G

S

N-Channel MOSFET

FEATURES

• Advanced process technology

• Surface mount (IRFZ48S, SiHFZ48S)

• Low-profile through-hole (IRFZ48L, SiHFZ48L)

• 175 °C operating temperature

•Fast switching

• Material categorization: for definitions of
compliance please see

www.vishay.com/doc?99912

Note

*

Thi s datasheet pro vi des information about parts that are
RoHS-compliant and / or parts that are non-RoHS-compliant. For
example, parts with lead (Pb) terminations are not RoHS-compliant.
Please see the information / tables in this datasheet for details.





DESCRIPTION

Third generation power MOSFETs from Vishay utilize
advanced processing techniques to achieve extremely low
on-resistance per silicon area. This benefit, combined with
the fast switching speed and ruggedized device design that
Power MOSFETs are well known for, provides the designer
with an extremely efficient and reliable device for use in a
wide variety of applications.
The D2PAK is a surface mount power package capable of
accommodating die sizes up to HEX-4. It provides the
highest power capability and the lowest possible
on-resistance in any existing surface mount package. The
D2PAK is suitable for high current applications because of
its low internal connection resistance and can dissipate up
to 2 W in a typical surface mount application.
The through-hole version (IRFZ48L, SiHFZ48L) is available
for low-profile applications.

ORDERING INFORMATION

Package D2PAK (TO-263) I2PAK (TO-262)

Lead (Pb)-free and halogen-free SiHFZ48S-GE3 SiHFZ48L-GE3

Lead (Pb)-free IRFZ48SPbF -

Note

a. See device orientation.

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT

Drain-Source Voltage V
Gate-Source Voltage V

T

= 25 °C

Continuous Drain Current

Pulsed Drain Current

a, e

f

VGS at 10 V

C

= 100 °C 50

C

DS

± 20

GS

I

D

IDM 290

Linear Derating Factor 1.3 W/°C

c, e

b, e

T

= 25 °C

C

T

= 25 °C 3.7

A

Single Pulse Avalanche Energy

Maximum Power Dissipation

Peak Diode Recovery dV/dt
Operating Junction and Storage Temperature Range T
Soldering Recommendations (Peak temperature)

d

for 10 s 300

E

AS

P

D

dV/dt 4.5 V/ns

, T

J

stg

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. V

= 25 V, Starting TJ = 25 °C, L = 22 μH, Rg = 25 , IAS = 72 A (see fig. 12).

DD

c. ISD  72 A, dI/dt  200 A/μs, VDD  VDS, TJ  175 °C.
d. 1.6 mm from case.
e. Uses IRFZ48, SiHFZ48 data and test conditions.
f. Calculated continuous current based on maximum allowable junction temperature.

S15-1659-Rev. D, 20-Jul-15

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1

60

50

100 mJ
190

-55 to +175

Document Number: 90377

V

AT

W

°C

IRFZ48S, IRFZ48L, SiHFZ48S, SiHFZ48L

S

D

G

www.vishay.com

THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL TYP. MAX. UNIT

Maximum Junction-to-Ambient 
(PCB mount)

a

Maximum Junction-to-Case (Drain) R

R

thJA

thJC

-40

-0.8

Note

a. When mounted on 1" square PCB (FR-4 or G-10 material). 

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

Static

Drain-Source Breakdown Voltage V

V

Temperature Coefficient VDS/TJ Reference to 25 °C, ID = 1 mA

DS

Gate-Source Threshold Voltage V

Gate-Source Leakage I

Zero Gate Voltage Drain Current I

Drain-Source On-State Resistance R

Forward Transconductance g

DS

GS(th)

V

GSS

DSS

VGS = 10 V ID = 43 A

DS(on)

fs

Dynamic

Input Capacitance C

Reverse Transfer Capacitance C

Total Gate Charge Q

Gate-Drain Charge Q

Turn-On Delay Time t

Rise Time t

Turn-Off Delay Time t

Fall Time t

Internal Source Inductance L

iss

- 1300 -

oss

- 190 -

rss

g

--29

gs

--36

gd

d(on)

r

- 210 -

d(off)

- 250 -

f

S

V

R

Between lead, and center of die contact - 7.5 - nH

Drain-Source Body Diode Characteristics

Continuous Source-Drain Diode Current I

Pulsed Diode Forward Current

a

Body Diode Voltage V

Body Diode Reverse Recovery Time t

Body Diode Reverse Recovery Charge Q

Forward Turn-On Time t

S

I

SM

SD

rr

rr

on

MOSFET symbol
showing the 
integral reverse
p - n junction diode

TJ = 25 °C, IF = 72 A, dI/dt = 100 A/μs

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width  300 μs; duty cycle  2 %.
c. Uses IRFZ48/SiHFZ48 data and test conditions.
d. Calculated continuous current based on maximum allowable junction temperature.

VGS = 0, ID = 250 μA 60 - - V

c

VDS = VGS, ID = 250 μA 2.0 - 4.0 V

= ± 20 V - - ± 100 nA

GS

VDS = 60 V, VGS = 0 V - - 25

= 48 V, VGS = 0 V, TJ = 150 °C - - 250

V

DS

VDS = 25 V, ID = 43 A

b

b

VGS = 0 V,

V

= 25 V,

DS

f = 1.0 MHz, see fig. 5

= 72 A, VDS = 48 V,

I

= 10 V

GS

V

= 9.1 , RD = 0.34 , see fig. 10

g

D

see fig. 6 and 13

= 30 V, ID = 72 A,

DD

TJ = 25 °C, IS = 72 A, VGS = 0 V

c

b, c

b, c

b

b, c

Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)

Vishay Siliconix

°C / W

-0.060-V/°C

- - 0.018 

27 - - S

- 2400 -

--110

-8.1-

- 250 -

--50

--290

--2.0V

- 120 180 ns

- 500 800 μC

c

μA

pFOutput Capacitance C

nC Gate-Source Charge Q

ns

A

S15-1659-Rev. D, 20-Jul-15

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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

For technical questions, contact: [e-mail]

2

Document Number: 90377

IRFZ48S, IRFZ48L, SiHFZ48S, SiHFZ48L

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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

Vishay Siliconix

Fig. 1 - Typical Output Characteristics

Fig. 2 - Typical Output Characteristics

Fig. 3 - Typical Transfer Characteristics

Fig. 4 - Normalized On-Resistance vs. Temperature

S15-1659-Rev. D, 20-Jul-15

For technical questions, contact: [e-mail]

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Document Number: 90377

IRFZ48S, IRFZ48L, SiHFZ48S, SiHFZ48L

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Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

Vishay Siliconix

Fig. 7 - Typical Source-Drain Diode Forward Voltage

Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage

S15-1659-Rev. D, 20-Jul-15

For technical questions, contact: [e-mail]

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Fig. 8 - Maximum Safe Operating Area

Document Number: 90377

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Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %

R

D

V

GS

R

g

D.U.T.

10 V

+

-

V

DS

V

DD

V

DS

90 %

10 %

V

GS

t

d(on)

t

r

t

d(off)

t

f

R

g

I

AS

0.01 Ω

t

p

D.U.T.

L

V

DS

+

-

V

DD

10 V

Var y t

p

to obtain

required I

AS

I

AS

V

DS

V

DD

V

DS

t

p

IRFZ48S, IRFZ48L, SiHFZ48S, SiHFZ48L

Vishay Siliconix

Fig. 10a - Switching Time Test Circuit

Fig. 9 - Maximum Drain Current vs. Case Temperature

Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig. 10b - Switching Time Waveform

Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms

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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

5

For technical questions, contact: [e-mail]

Document Number: 90377

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Q

GS

Q

GD

Q

G

V

G

Charge

10 V

IRFZ48S, IRFZ48L, SiHFZ48S, SiHFZ48L

Vishay Siliconix

Fig. 12c - Maximum Avalanche Energy vs. Drain Current

Current regulator

Same type as D.U.T.

50 kΩ

0.2 µF

12 V

V

GS

0.3 µF

D.U.T.

3 mA

I

G

Current sampling resistors

I

D

+

-

Fig. 13a - Maximum Avalanche Energy vs. Drain Current Fig. 13b - Gate Charge Test Circuit

V

DS

S15-1659-Rev. D, 20-Jul-15

6

Document Number: 90377

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P.W.

Period

dI/dt

Diode recovery

dV/dt

Ripple ≤ 5 %

Body diode forward drop

Re-applied
voltage

Reverse
recovery
current

Body diode forward

current

V

GS

= 10 Va

I

SD

Driver gate drive

D.U.T. l

SD

waveform

D.U.T. V

DS

waveform

Inductor current

D =

P.W.

Period

+

-

+

+

+

-

-

-

Peak Diode Recovery dV/dt Test Circuit

V

DD

• dV/dt controlled by R

g

• Driver same type as D.U.T.

•

I

SD

controlled by duty factor “D”

• D.U.T. - device under test

D.U.T.

Circuit layout considerations

• Low stray inductance

• Ground plane

• Low leakage inductance

current transformer

R

g

Note

a. V

GS

= 5 V for logic level devices

V

DD

IRFZ48S, IRFZ48L, SiHFZ48S, SiHFZ48L

Vishay Siliconix

Fig. 14 - For N-Channel

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









Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?90377

S15-1659-Rev. D, 20-Jul-15

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

.

7

For technical questions, contact: [e-mail]

Document Number: 90377

TO-263AB (HIGH VOLTAGE)

(Datum A)

34

E

L1

4

D

L2

4

C

1

B

B

C

3

2

B

B

Package Information

Vishay Siliconix

A

A

5

H

Detail A

B

A

c2

Gauge
plane

0° to 8°

L

L3

L4

Detail “A”
Rotated 90° CW
scale 8:1

H

B

Seating plane

A1

2 x e

Lead tip

2 x b2

2 x b

0.010 A B

MM

Plating

(c)

Section B - B and C - C

c

± 0.004 B

5

b1, b3

(b, b2)

Scale: none

M

Base
metal

c1

A

E

D1

4

5

E1

View A - A

4

MILLIMETERS INCHES MILLIMETERS INCHES

DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX.

A 4.06 4.83 0.160 0.190 D1 6.86 - 0.270 -

A1 0.00 0.25 0.000 0.010 E 9.65 10.67 0.380 0.420

b 0.51 0.99 0.020 0.039 E1 6.22 - 0.245 -

b1 0.51 0.89 0.020 0.035 e 2.54 BSC 0.100 BSC

b2 1.14 1.78 0.045 0.070 H 14.61 15.88 0.575 0.625

b3 1.14 1.73 0.045 0.068 L 1.78 2.79 0.070 0.110

c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.066

c1 0.38 0.58 0.015 0.023 L2 - 1.78 - 0.070

c2 1.14 1.65 0.045 0.065 L3 0.25 BSC 0.010 BSC

D 8.38 9.65 0.330 0.380 L4 4.78 5.28 0.188 0.208

ECN: S-82110-Rev. A, 15-Sep-08
DWG: 5970

Notes

1. Dimensioning and tolerancing per ASME Y14.5M-1994.

2. Dimensions are shown in millimeters (inches).

3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the
outmost extremes of the plastic body at datum A.

4. Thermal PAD contour optional within dimension E, L1, D1 and E1.

5. Dimension b1 and c1 apply to base metal only.

6. Datum A and B to be determined at datum plane H.

7. Outline conforms to JEDEC outline to TO-263AB.

Document Number: 91364 www.vishay.com
Revision: 15-Sep-08 1

I2PAK (TO-262) (HIGH VOLTAGE)

(Datum A)

E

L1

Package Information

Vishay Siliconix

A

A

B

c2

A

E

D

L2

0.010 A B

Lead tip

B

2 x e

M

Seating

plane

C

C

B

M

3 x b2

3 x b

L

A1

A

E1

Section A - A

Plating

c

b1, b3

(b, b2)

Section B - B and C - C

Scale: None

c

D1

Base
metal

c1

MILLIMETERS INCHES MILLIMETERS INCHES

DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX.

A 4.06 4.83 0.160 0.190 D 8.38 9.65 0.330 0.380

A1 2.03 3.02 0.080 0.119 D1 6.86 - 0.270 -

b 0.51 0.99 0.020 0.039 E 9.65 10.67 0.380 0.420

b1 0.51 0.89 0.020 0.035 E1 6.22 - 0.245 -

b2 1.14 1.78 0.045 0.070 e 2.54 BSC 0.100 BSC

b3 1.14 1.73 0.045 0.068 L 13.46 14.10 0.530 0.555

c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.065

c1 0.38 0.58 0.015 0.023 L2 3.56 3.71 0.140 0.146

c2 1.14 1.65 0.045 0.065

ECN: S-82442-Rev. A, 27-Oct-08
DWG: 5977

Notes

1. Dimensioning and tolerancing per ASME Y14.5M-1994.

2. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm per side. These dimensions are measured at the outmost
extremes of the plastic body.

3. Thermal pad contour optional within dimension E, L1, D1, and E1.

4. Dimension b1 and c1 apply to base metal only.

Document Number: 91367 www.vishay.com
Revision: 27-Oct-08 1

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Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over
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Revision: 13-Jun-16

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Document Number: 91000