Datasheet IRFR420A, IRFU420A, SiHFR420A, SiHFU420A DataSheet (Vishay)

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N-Channel MOSFET

G

D

S

IRFR420A, IRFU420A, SiHFR420A, SiHFU420A

Vishay Siliconix

Power MOSFET

PRODUCT SUMMARY

VDS (V) 500

R

()V

DS(on)

Q

max. (nC) 17

g

Q

(nC) 4.3

gs

Q

(nC) 8.5

gd

Configuration Single

= 10 V 3.0

GS

FEATURES

• Low gate Charge Qg results in simple drive
requirement

• Improved gate, avalanche and dynamic dV/dt
ruggedness

• Fully characterized capacitance and
avalanche voltage and current

• Effective C

specified

oss

• Material categorization: for definitions of compliance

DPAK

(TO-252)

D

IPAK

(TO-251)

D

S

G

S

D

G

please see www.vishay.com/doc?99912

APPLICATIONS

• Switch mode power supply (SMPS)

• Uninterruptible power supply

• High speed power switching

ORDERING INFORMATION

Package DPAK (TO-252) DPAK (TO-252) DPAK (TO-252) IPAK (TO-251)

Lead (Pb)-free and Halogen-free SiHFR420A-GE3 SiHFR420ATR-GE3

Lead (Pb)-free IRFR420APbF IRFR420ATRPbF

Note

a. See device orientation.

a

SiHFR420ATRL-GE3 SiHFU420A-GE3

a

IRFR420ATRLPbF IRFU420APbF

Available

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT

Drain-Source Voltage V

Gate-Source Voltage V

T

= 25 °C

Continuous Drain Current V

Pulsed Drain Current

a

at 10 V

GS

C

= 100 °C 2.1

C

DS

± 30

GS

I

D

IDM 10

Linear Derating Factor 0.67 W/°C

Single Pulse Avalanche Energy

Repetitive Avalanche Current

Repetitive Avalanche Energy

Maximum Power Dissipation T

Peak Diode Recovery dV/dt

Operating Junction and Storage Temperature Range T

Soldering Recommendations (Peak temperature)

b

a

a

= 25 °C P

c

d

C

for 10 s 300

E

AS

I

AR

E

AR

D

dV/dt 3.4 V/ns

, T

J

stg

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Starting T
c. I

SD

= 25 °C, L = 45 mH, Rg = 25 , IAS = 2.5 A (see fig. 12).

J

 2.5 A, dI/dt  270 A/μs, VDD  VDS, TJ  150 °C.

d. 1.6 mm from case.

S16-1522-Rev. D, 08-Aug-16

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500

3.3

140 mJ

2.5 A

5.0 mJ

83 W

-55 to +150

Document Number: 91274

V

AT

°C

IRFR420A, IRFU420A, SiHFR420A, SiHFU420A

S

D

G

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THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL TYP. MAX. UNIT

Maximum Junction-to-Ambient R

Maximum Junction-to-Case (Drain) R

thJA

thCS

thJC

-62

0.50 -

-1.5

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

Static

Drain-Source Breakdown Voltage V

V

Temperature Coefficient VDS/TJ Reference to 25 °C, ID = 1 mA - 0.60 - V/°C

DS

Gate-Source Threshold Voltage V

Gate-Source Leakage I

Zero Gate Voltage Drain Current I

Drain-Source On-State Resistance R

Forward Transconductance g

DS

GS(th)

V

GSS

DSS

VGS = 10 V ID = 1.5 A

DS(on)

fs

Dynamic

Input Capacitance C

Reverse Transfer Capacitance C

Output Capacitance C

Effective Output Capacitance C

Total Gate Charge Q

Gate-Drain Charge Q

Turn-On Delay Time t

Rise Time t

Turn-Off Delay Time t

Fall Time t

iss

-53-

oss

-2.7-

rss

oss

eff. VDS = 0 V to 400 V

oss

g

--4.3

gs

--8.5

gd

d(on)

r

-16-

d(off)

-13-

f

Drain-Source Body Diode Characteristics

Continuous Source-Drain Diode Current I

Pulsed Diode Forward Current

a

Body Diode Voltage V

Body Diode Reverse Recovery Time t

Body Diode Reverse Recovery Charge Q

Forward Turn-On Time t

S

I

SM

SD

rr

rr

on

MOSFET symbol
showing the 
integral reverse
p - n junction diode

TJ = 25 °C, IF = 2.5 A, dI/dt = 100 A/μs

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width  300 μs; duty cycle  2 %.
c. C

eff. is a fixed capacitance that gives the same charging time as C

oss

VGS = 0 V, ID = 250 μA 500 - - V

VDS = VGS, ID = 250 μA 2.0 - 4.5 V

= ± 30 V - - ± 100 nA

GS

VDS = 500 V, VGS = 0 V - - 25

= 400 V, VGS = 0 V, TJ = 125 °C - - 250

V

DS

b

VDS = 50 V, ID = 1.5 A 1.4 - - S

VGS = 0 V,

V

= 25 V,

DS

f = 1.0 MHz, see fig. 5

= 1.0 V, f = 1.0 MHz - 490 -

V

DS

= 0 V

V

GS

V

= 10 V

GS

V

DD

R

= 21 , RD = 97 , see fig. 10

g

TJ = 25 °C, IS = 2.5 A, VGS = 0 V

= 400 V, f = 1.0 MHz - 15 -

DS

= 2.5 A, VDS = 400 V,

I

D

see fig. 6 and 13

= 250 V, ID = 2.5 A,

c

b

b

b

b

Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)

while VDS is rising from 0 % to 80 % VDS.

oss

Vishay Siliconix

°C/WCase-to-Sink, Flat, Greased Surface R

--3.0

- 340 -

-28-

--17

-8.1-

-12-

--3.3

--10

--1.6V

- 330 500 ns

- 760 1140 μC

μA

pFOutput Capacitance C

pFV

nC Gate-Source Charge Q

ns

A

S16-1522-Rev. D, 08-Aug-16

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

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Document Number: 91274

IRFR420A, IRFU420A, SiHFR420A, SiHFU420A

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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

Vishay Siliconix

10

1

0.1

TOP

BOTTOM

VGS
15V
10V

8.0V

7.0V

6.0V

5.5V

5.0V

4.5V

4.5V

D

I , Drain-to-Source Current (A)

20μs PULSE WIDTH

°

T = 25 C

0.01

0.1 1 10 100

V , Drain-to-Source Voltage (V)

DS

J

Fig. 1 - Typical Output Characteristics

10

TOP

BOTTOM

VGS
15V
10V

8.0V

7.0V

6.0V

5.5V

5.0V

4.5V

10

°

T = 150 C

J

1

°

T = 25 C

J

0.1

D

I , Drain-to-Source Current (A)

V = 50V

DS

0.01

4.0 5.0 6.0 7.0 8.0 9.0

V , Gate-to-Source Voltage (V)

GS

20μs PULSE WIDTH

Fig. 3 - Typical Transfer Characteristics

3.0

2.5

2.0

I =

D

2.5A

1

4.5V

D

I , Drain-to-Source Current (A)

20μs PULSE WIDTH

0.1
1 10 100

V , Drain-to-Source Voltage (V)

DS

T = 150 C

°

J

Fig. 2 - Typical Output Characteristics

1.5

(Normalized)

1.0

0.5

DS(on)

R , Drain-to-Source On Resistance

0.0

-60 -40 -20 0 20 40 60 80 100 120 140 160

T , Junction Temperature ( C)

J

V =

GS

°

10V

Fig. 4 - Normalized On-Resistance vs. Temperature

S16-1522-Rev. D, 08-Aug-16

3

Document Number: 91274

For technical questions, contact: [e-mail]

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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

www.vishay.com

IRFR420A, IRFU420A, SiHFR420A, SiHFU420A

Vishay Siliconix

10 000

1000

)
F
p

(
e
c
n
a

t

i

100

c
a
p
a

C
,

C

10

1

1 10 100 1000

V

= 0V, f = 1 MHz

GS

C

= C

iss

gs

C

= C

rss

gd

C

= C

C

ds

C

C

+ C

iss

oss

rss

oss

+ Cgd, C

gd

ds

shorted

VDS, Drain-to-Source Voltage (V)

Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

20

I =

2.5A

D

15

V = 400V

DS

V = 250V

DS

V = 100V

DS

10

°

T = 150 C

J

1

°

T = 25 C

J

SD

I , Reverse Drain Current (A)

V = 0 V

0.1

0.4 0.6 0.8 1.0 1.2

V ,Source-to-Drain Voltage (V)

SD

GS

Fig. 7 - Typical Source-Drain Diode Forward Voltage

100

OPERATION IN THIS AREA LIMITED

10

BY R

DS(on)

10us

10

5

GS

V , Gate-to-Source Voltage (V)

FOR TEST CIRCUIT

0

0 4 8 12 16

Q , Total Gate Charge (nC)

G

SEE FIGURE

13

Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage

100us

1

D

I , Drain Current (A)I , Drain Current (A)

°

= 25 C

C

T T= 150 C
Single Pulse

0.1
10 100 1000 10000

°

J

V , Drain-to-Source Voltage (V)

DS

1ms

10ms

Fig. 8 - Maximum Safe Operating Area

S16-1522-Rev. D, 08-Aug-16

4

Document Number: 91274

For technical questions, contact: [e-mail]

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

IRFR420A, IRFU420A, SiHFR420A, SiHFU420A

Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %

R

D

V

GS

R

g

D.U.T.

10 V

+

-

V

DS

V

DD

V

DS

90 %

10 %

V

GS

t

d(on)

t

r

t

d(off)

t

f

0.01

0.1

1

10

0.00001 0.0001 0.001 0.01 0.1 1

Not es:

1. Duty factor D = t / t

2. Peak T = Px Z + T

1 2

JDMthJC

C

P

t

t

DM

1

2

t , Rectangular Pulse Duration (s)

Thermal Response (Z

thJC

)

1

0.01

0.02

0.05

0.10

0.20

D = 0.50

SINGLE PULSE

(THERMAL RESPONSE)

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5.0

4.0

3.0

Vishay Siliconix

2.0

D

I , Drain Current (A)

1.0

0.0
25 50 75 100 125 150

T , Case Temperature ( C)

C

°

Fig. 9 - Maximum Drain Current vs. Case Temperature

Fig. 10a - Switching Time Test Circuit

Fig. 10b - Switching Time Waveforms

Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case

15 V

V

DS

R

S16-1522-Rev. D, 08-Aug-16

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

g

20 V

t

Fig. 12a - Unclamped Inductive Test Circuit

L

D.U.T

I

AS

0.01 Ω

p

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Driver

+

V

A

DD

-

5

For technical questions, contact: [e-mail]

I

AS

Fig. 12b - Unclamped Inductive Waveforms

V

DS

t

p

Document Number: 91274

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25 50 75 100 125 150

0

50

100

150

200

250

300

Starting TJ, Junction Temperature (°C)

E

AS

, Single Pulse Avalanche Energy (mJ)

I

D

TOP

BOTTOM

1.1 A

1.6 A

2.5 A

0.0 0.5 1.0 1.5 2.0 2.5

IAV, Avalanche Current ( A)

550

600

650

700

V

D

S

a

v

,

A

v

a

l

a

n

c

h

e

V

o

l

t

a

g

e

(

V

)

IRFR420A, IRFU420A, SiHFR420A, SiHFU420A

Vishay Siliconix

Q

G

10 V

Q

GS

V

G

Fig. 13a - Basic Gate Charge Waveform

Current regulator

Same type as D.U.T.

Q

GD

Charge

Fig. 12c - Maximum Avalanche Energy vs. Drain Current

Fig. 12d - Maximum Avalanche Energy vs. Drain Current

50 kΩ

0.2 µF

12 V

V

GS

0.3 µF

D.U.T.

3 mA

I

G

Current sampling resistors

I

D

Fig. 13b - Gate Charge Test Circuit

+

V

DS

-

S16-1522-Rev. D, 08-Aug-16

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Document Number: 91274

IRFR420A, IRFU420A, SiHFR420A, SiHFU420A

P.W.

Period

dI/dt

Diode recovery

dV/dt

Ripple ≤ 5 %

Body diode forward drop

Re-applied
voltage

Reverse
recovery
current

Body diode forward

current

V

GS

= 10 Va

I

SD

Driver gate drive

D.U.T. l

SD

waveform

D.U.T. V

DS

waveform

Inductor current

D =

P.W.

Period

+

-

+

+

+

-

-

-

Peak Diode Recovery dV/dt Test Circuit

V

DD

• dV/dt controlled by R

g

• Driver same type as D.U.T.

•

I

SD

controlled by duty factor “D”

• D.U.T. - device under test

D.U.T.

Circuit layout considerations

• Low stray inductance

• Ground plane

• Low leakage inductance

current transformer

R

g

Note

a. V

GS

= 5 V for logic level devices

V

DD

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Vishay Siliconix

Fig. 14 - For N-Channel











Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91274

S16-1522-Rev. D, 08-Aug-16

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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

.

7

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Document Number: 91274

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Package Information

Vishay Siliconix

TO-252AA Case Outline

E

b3

L3

A

C2

DIM. MIN. MAX. MIN. MAX.

MILLIMETERS INCHES

A 2.18 2.38 0.086 0.094

A1 - 0.127 - 0.005

b 0.64 0.88 0.025 0.035

D

H

b2 0.76 1.14 0.030 0.045

b3 4.95 5.46 0.195 0.215

C 0.46 0.61 0.018 0.024

C2 0.46 0.89 0.018 0.035

L4

L5

L

D 5.97 6.22 0.235 0.245

D1 4.10 - 0.161 -

E 6.35 6.73 0.250 0.265

b

e1

b2

e

C

A1

E1 4.32 - 0.170 -

H 9.40 10.41 0.370 0.410

e 2.28 BSC 0.090 BSC

e1 4.56 BSC 0.180 BSC

gage plane height (0.5 mm)

L 1.40 1.78 0.055 0.070

L3 0.89 1.27 0.035 0.050

D1

L4 - 1.02 - 0.040

L5 1.01 1.52 0.040 0.060

ECN: T16-0236-Rev. P, 16-May-16

E1

DWG: 5347

Notes

• Dimension L3 is for reference only.

Revision: 16-May-16

1

Document Number: 71197

For technical questions, contact: [e-mail]

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TO-251AA (HIGH VOLTAGE)

Package Information

Vishay Siliconix

4

E1

View A - A

Thermal PAD

D1

4

(Datum A)

3

E

b4

θ2

5

C

L3

L1

B

B

2 x e

Lead tip

A

4

L2

D

C

L

3 x b2

3 x b

0.010 C BMA

0.010 BA

B

3

M

0.25

C

4

0.25

Plating

(c)

Section B - B and C - C

5

b1, b3

(b, b2)

Base
metal

c1

A

c2

θ1

5

A

C

Seating
plane

A

A1

c

MILLIMETERS INCHES MILLIMETERS INCHES

DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX.

A 2.18 2.39 0.086 0.094 D1 5.21 - 0.205 -

A1 0.89 1.14 0.035 0.045 E 6.35 6.73 0.250 0.265

b 0.64 0.89 0.025 0.035 E1 4.32 - 0.170 -

b1 0.65 0.79 0.026 0.031 e 2.29 BSC 2.29 BSC

b2 0.76 1.14 0.030 0.045 L 8.89 9.65 0.350 0.380

b3 0.76 1.04 0.030 0.041 L1 1.91 2.29 0.075 0.090

b4 4.95 5.46 0.195 0.215 L2 0.89 1.27 0.035 0.050

c 0.46 0.61 0.018 0.024 L3 1.14 1.52 0.045 0.060

c1 0.41 0.56 0.016 0.022 θ1 0' 15' 0' 15'

c2 0.46 0.86 0.018 0.034 θ2 25' 35' 25' 35'

D 5.97 6.22 0.235 0.245

ECN: S-82111-Rev. A, 15-Sep-08
DWG: 5968

Notes

1. Dimensioning and tolerancing per ASME Y14.5M-1994.

2. Dimension are shown in inches and millimeters.

3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.13 mm (0.005") per side. These dimensions are measured at the
outermost extremes of the plastic body.

4. Thermal pad contour optional with dimensions b4, L2, E1 and D1.

5. Lead dimension uncontrolled in L3.

6. Dimension b1, b3 and c1 apply to base metal only.

7. Outline conforms to JEDEC outline TO-251AA.

Document Number: 91362 www.vishay.com
Revision: 15-Sep-08 1

RECOMMENDED MINIMUM PADS FOR DPAK (TO-252)

0.224

(5.690)

Application Note 826

Vishay Siliconix

0.243
(6.180)

Return to Index

Return to Index

0.420
(10.668)

0.180

(4.572)

Recommended Minimum Pads

Dimensions in Inches/(mm)

0.087

0.090

0.055

(1.397)

(2.202)

(2.286)

APPLICATION NOTE

Document Number: 72594 www.vishay.com
Revision: 21-Jan-08 3

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Disclaimer



ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.

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“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
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Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over
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including but not limited to the warranty expressed therein.

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Revision: 13-Jun-16

1

Document Number: 91000