Datasheet IRFR1N60A, IRFU1N60A, SiHFR1N60A, SiHFU1N60A DataSheet (Vishay)

IRFR1N60A, IRFU1N60A, SiHFR1N60A, SiHFU1N60A

DPAK

(TO-252)

IPAK

(TO-251)

G

D

S

S

D

G

D

www.vishay.com

Vishay Siliconix

Power MOSFET

PRODUCT SUMMARY

VDS (V) 600

R

(Max.) ()V

DS(on)

Q

(Max.) (nC) 14

g

Q

(nC) 2.7

gs

Q

(nC) 8.1

gd

Configuration Single

= 10 V 7.0

GS

FEATURES

• Low Gate Charge Qg Results in Simple Drive
Requirement

• Improved Gate, Avalanche and Dynamic
dV/dt Ruggedness

• Fully Characterized Capacitance and
Avalanche Voltage and Current

• Material categorization: For definitions of
compliance please see www.vishay.com/doc?99912

D

APPLICATIONS

• Switch Mode Power Supply (SMPS)

• Uninterruptible Power Supply

G

• Power Factor Correction

TYPICAL SMPS TOPOLOGIES

• Low Power Single Transistor Flyback

S

N-Channel MOSFET

ORDERING INFORMATION

Package DPAK (TO-252) DPAK (TO-252) DPAK (TO-252) DPAK (TO-252) IPAK (TO-251)

Lead (Pb)-free and
Halogen-free

Lead (Pb)-free

SiHFR1N60A-GE3 SiHFR1N60ATRL-GE3

IRFR1N60APbF IRFR1N60ATRLPbF

SiHFR1N60A-E3 SiHFR1N60ATL-E3

a

SiHFR1N60ATR-GE3aSiHFR1N60ATRR-GE3aSiHFU1N60A-GE3

a

IRFR1N60ATRPbF

a

SiHFR1N60AT-E3

a

IRFR1N60ATRRPbF

a

SiHFR1N60ATR-E3

a

IRFU1N60APbF

a

SiHFU1N60A-E3

Note

a. See device orientation.

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT

Drain-Source Voltage V

Gate-Source Voltage V

T

= 25 °C

Continuous Drain Current V

Pulsed Drain Current

a

at 10 V

GS

C

= 100 °C 0.89

C

DS

± 30

GS

I

D

IDM 5.6

Linear Derating Factor 0.28 W/°C

Single Pulse Avalanche Energy

Repetitive Avalanche Current

Repetitive Avalanche Energy

Maximum Power Dissipation T

Peak Diode Recovery dV/dt

Operating Junction and Storage Temperature Range T

Soldering Recommendations (Peak Temperature)

b

a

a

= 25 °C P

c

d

C

for 10 s 300

E

AS

I

AR

E

AR

D

dV/dt 3.8 V/ns

, T

J

stg

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Starting T
c. I

SD

d. 1.6 mm from case.

= 25 °C, L = 95 mH, Rg = 25 , IAS = 1.4 A (see fig. 12).

J

 1.4 A, dI/dt  180 A/μs, VDD  VDS, TJ  150 °C.

600

1.4

93 mJ

1.4 A

3.6 mJ

36 W

- 55 to + 150

V

AT

°C

S13-0171-Rev. D, 04-Feb-13

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

1

Document Number: 91267

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IRFR1N60A, IRFU1N60A, SiHFR1N60A, SiHFU1N60A

S

D

G

www.vishay.com

THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL TYP. MAX. UNIT

Maximum Junction-to-Ambient R

Maximum Junction-to-Ambient
(PCB Mount)

a

Maximum Junction-to-Case (Drain) R

thJA

R

thJA

thJC

-110

-50

-3.5

Note

a. When mounted on 1" square PCB (FR-4 or G-10 material).

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

Static

Drain-Source Breakdown Voltage V

Gate-Source Threshold Voltage V

Gate-Source Leakage I

Zero Gate Voltage Drain Current I

Drain-Source On-State Resistance R

Forward Transconductance g

DS

GS(th)

V

GSS

DSS

VGS = 10 V ID = 0.84 A

DS(on)

fs

Dynamic

Input Capacitance C

Output Capacitance C

Reverse Transfer Capacitance C

Output Capacitance C

Effective Output Capacitance C

Total Gate Charge Q

Gate-Drain Charge Q

Turn-On Delay Time t

Rise Time t

Turn-Off Delay Time t

Fall Time t

iss

- 32.6 -

oss

-2.4-

rss

oss

eff. VDS = 0 V to 480 V

oss

g

--2.7

gs

--8.1

gd

d(on)

r

-18-

d(off)

-20-

f

Drain-Source Body Diode Characteristics

Continuous Source-Drain Diode Current I

Pulsed Diode Forward Current

a

Body Diode Voltage V

Body Diode Reverse Recovery Time t

Body Diode Reverse Recovery Charge Q

Forward Turn-On Time t

S

I

SM

SD

rr

rr

on

MOSFET symbol
showing the

integral reverse
p - n junction diode

TJ = 25 °C, IF = 1.4 A, dI/dt = 100 A/μs

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width  300 μs; duty cycle  2 %.
c. C

eff. is a fixed capacitance that gives the same charging time as C

oss

VGS = 0 V, ID = 250 μA 600 - -

VDS = VGS, ID = 250 μA 2.0 - 4.0

= ± 30 V - - ± 100 nA

GS

VDS = 600 V, VGS = 0 V - - 25

V

= 480 V, VGS = 0 V, TJ = 150 °C - - 250

DS

b

VDS = 50 V, ID = 0.84 A 0.88 - - S

VGS = 0 V,

V

= 25 V,

DS

f = 1.0 MHz, see fig. 5

= 1.0 V, f = 1.0 MHz - 320 -

V

DS

V

= 0 V

GS

V

= 10 V

GS

R

= 2.15 , RD = 178 , see fig. 10

g

TJ = 25 °C, IS = 1.4 A, VGS = 0 V

V

= 480 V, f = 1.0 MHz - 11.5 -

DS

= 1.4 A, VDS = 400 V,

I

D

see fig. 6 and 13

= 250 V, ID = 1.4 A,

V

DD

c

b

b

b

b

Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)

while VDS is rising from 0 to 80 % VDS.

oss

Vishay Siliconix

°C/W

--7.0

- 229 -

- 130 -

--14

-9.8-

-14-

--1.4

--5.6

--1.6V

- 290 440 ns

- 510 760 μC

V

μA

pF

nC Gate-Source Charge Q

ns

A

S13-0171-Rev. D, 04-Feb-13

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

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Document Number: 91267

IRFR1N60A, IRFU1N60A, SiHFR1N60A, SiHFU1N60A

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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

Vishay Siliconix

10

1

0.1

D

I , Drain-to-Source Current (A)

0.01

0.1 1 10 100

VGS

TOP

15V
10V

8.0V

7.0V

6.0V

5.5V

5.0V

BOTTOM

4.5V

4.5V

20μs PULSE WIDTH
T = 25 C

J

V , Drain-to-Source Voltage (V)

DS

°

Fig. 1 - Typical Output Characteristics

10

TOP

BOTTOM

VGS
15V
10V

8.0V

7.0V

6.0V

5.5V

5.0V

4.5V

10

°

T = 150 C

J

1

°

T = 25 C

J

D

I , Drain-to-Source Current (A)

V = 100V

DS

0.1

4.0 5.0 6.0 7.0 8.0 9.0

V , Gate-to-Source Voltage (V)

GS

20μs PULSE WIDTH

Fig. 3 - Typical Transfer Characteristics

3.0

2.5

2.0

I =

D

1.4A

1

4.5V

D

I , Drain-to-Source Current (A)

20μs PULSE WIDTH

°

T = 150 C

0.1
1 10 100

V , Drain- to-Sour ce Voltage (V)

DS

J

Fig. 2 - Typical Output Characteristics

1.5

(Normalized)

1.0

0.5

DS(on)

R , Drain-to-Source On Resistance

0.0

-60 -40 -20 0 20 40 60 80 100 120 140 160

T , Junction Temperature ( C)

J

V =

GS

°

Fig. 4 - Normalized On-Resistance vs. Temperature

10V

S13-0171-Rev. D, 04-Feb-13

3

Document Number: 91267

For technical questions, contact: [e-mail]

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

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IRFR1N60A, IRFU1N60A, SiHFR1N60A, SiHFU1N60A

1

10

100

1000

10000

1 10 100 1000

C, Capacitance (pF)

DS

V , Drain-to-Source Voltage (V)

A

V = 0V, f = 1MHz
C = C + C , C SHORTED
C = C
C = C + C

GS
iss gs gd ds
rss gd
oss ds gd

C

iss

C

oss

C

rss

0 2 4 6 8 10 12 14

0

4

8

12

16

20

Q , Total Gate Charge (nC)

V , Gate-to-Source Voltage (V)

G

GS

FOR TEST CIRCUIT

SEE FIGURE

I =

D

13

1.4A

V = 120V

DS

V = 300V

DS

V = 480V

DS

www.vishay.com

Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

Vishay Siliconix

10

°

T = 150 C

J

1

°

T = 25 C

J

SD

I , Reverse Drain Current (A)

V = 0 V

0.1

0.4 0.6 0.8 1.0 1.2

V ,Source-to-Drain Voltage (V)

SD

Fig. 7 - Typical Source-Drain Diode Forward Voltage

GS

Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage

100

OPERATION IN THIS AREA LIMITED

10

1

D

I , Drain Current (A)I , Drain Current (A)

°

= 25 C

C

T T= 150 C
Single Pulse

0.1
10 100 1000 10000

°

J

V , Drain-to-Source Voltage (V)

DS

BY R

DS(on)

10us

100us

1ms

10ms

Fig. 8 - Maximum Safe Operating Area

S13-0171-Rev. D, 04-Feb-13

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

4

For technical questions, contact: [e-mail]

Document Number: 91267

IRFR1N60A, IRFU1N60A, SiHFR1N60A, SiHFU1N60A

Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %

R

D

V

GS

R

g

D.U.T.

10 V

+

-

V

DS

V

DD

V

DS

90 %

10 %

V

GS

t

d(on)

t

r

t

d(off)

t

f

0.01

0.1

1

10

0.00001 0.0001 0.001 0.01 0.1 1

Notes:

1. Duty factor D = t / t

2. Peak T =P x Z + T

1 2

J DM thJC C

P

t

t

DM

1

2

t , Rectangular Pulse Duration (sec)

Thermal Response (Z )

1

thJC

0.01

0.02

0.05

0.10

0.20

D = 0.50

SINGLE PULSE

(THERMAL RESPONSE)

www.vishay.com

1.6

1.2

0.8

D

I , Drain Current (A)

0.4

0.0
25 50 75 100 125 150

T , Case Temperature ( C)

C

Fig. 9 - Maximum Drain Current vs. Case Temperature

°

Vishay Siliconix

Fig. 10a - Switching Time Test Circuit

Fig. 10b - Switching Time Waveforms

Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case

15 V

V

DS

S13-0171-Rev. D, 04-Feb-13

R

g

20 V

t

Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

L

D.U.T

I

AS

0.01 Ω

p

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Driver

+

V

A

DD

-

5

For technical questions, contact: [e-mail]

I

AS

V

DS

t

p

Document Number: 91267

IRFR1N60A, IRFU1N60A, SiHFR1N60A, SiHFU1N60A

25 50 75 100 125 150

0

40

80

120

160

200

Starting T , Junction Temperature ( C)

E , Single Pulse Avalanche Energy (mJ)

J

AS

°

I

D

TOP

BOTTOM

0.65A

0.9A

1.4A

Q

GS

Q

GD

Q

G

V

G

Charge

V

GS

670

690

710

730

750

770

0.0 0.4 0.8 1.2 1.6

A

DSav

av

I , Avalanche Current (A)

V , Avalanche Voltage (V)

www.vishay.com

Vishay Siliconix

Fig. 12c - Maximum Avalanche Energy vs. Drain Current

Fig. 13a - Maximum Avalanche Energy vs. Drain Current

Fig. 12d - Basic Gate Charge Waveform

Current regulator

Same type as D.U.T.

50 kΩ

0.2 µF

12 V

V

GS

0.3 µF

D.U.T.

3 mA

I

G

Current sampling resistors

I

D

+

V

DS

-

Fig. 13b - Gate Charge Test Circuit

S13-0171-Rev. D, 04-Feb-13

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Document Number: 91267

IRFR1N60A, IRFU1N60A, SiHFR1N60A, SiHFU1N60A

P.W.

Period

dI/dt

Diode recovery

dV/dt

Ripple ≤ 5 %

Body diode forward drop

Re-applied
voltage

Reverse
recovery
current

Body diode forward

current

V

GS

= 10 Va

I

SD

Driver gate drive

D.U.T. l

SD

waveform

D.U.T. V

DS

waveform

Inductor current

D =

P.W.

Period

+

-

+

+

+

-

-

-

Peak Diode Recovery dV/dt Test Circuit

V

DD

• dV/dt controlled by R

g

• Driver same type as D.U.T.

•

I

SD

controlled by duty factor “D”

• D.U.T. - device under test

D.U.T.

Circuit layout considerations

• Low stray inductance

• Ground plane

• Low leakage inductance

current transformer

R

g

Note

a. V

GS

= 5 V for logic level devices

V

DD

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Vishay Siliconix

Fig. 14 - For N-Channel

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91267

S13-0171-Rev. D, 04-Feb-13

.

For technical questions, contact: [e-mail]

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Document Number: 91267

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Package Information

Vishay Siliconix

TO-252AA Case Outline

E

b3

L3

A

C2

DIM. MIN. MAX. MIN. MAX.

MILLIMETERS INCHES

A 2.18 2.38 0.086 0.094

A1 - 0.127 - 0.005

b 0.64 0.88 0.025 0.035

D

H

b2 0.76 1.14 0.030 0.045

b3 4.95 5.46 0.195 0.215

C 0.46 0.61 0.018 0.024

C2 0.46 0.89 0.018 0.035

L4

L5

L

D 5.97 6.22 0.235 0.245

D1 4.10 - 0.161 -

E 6.35 6.73 0.250 0.265

b

e1

b2

e

C

A1

E1 4.32 - 0.170 -

H 9.40 10.41 0.370 0.410

e 2.28 BSC 0.090 BSC

e1 4.56 BSC 0.180 BSC

gage plane height (0.5 mm)

L 1.40 1.78 0.055 0.070

L3 0.89 1.27 0.035 0.050

D1

L4 - 1.02 - 0.040

L5 1.01 1.52 0.040 0.060

ECN: T16-0236-Rev. P, 16-May-16

E1

DWG: 5347

Notes

• Dimension L3 is for reference only.

Revision: 16-May-16

1

Document Number: 71197

For technical questions, contact: [e-mail]

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TO-251AA (HIGH VOLTAGE)

Package Information

Vishay Siliconix

4

E1

View A - A

Thermal PAD

D1

4

(Datum A)

3

E

b4

θ2

5

C

L3

L1

B

B

2 x e

Lead tip

A

4

L2

D

C

L

3 x b2

3 x b

0.010 C BMA

0.010 BA

B

3

M

0.25

C

4

0.25

Plating

(c)

Section B - B and C - C

5

b1, b3

(b, b2)

Base
metal

c1

A

c2

θ1

5

A

C

Seating
plane

A

A1

c

MILLIMETERS INCHES MILLIMETERS INCHES

DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX.

A 2.18 2.39 0.086 0.094 D1 5.21 - 0.205 -

A1 0.89 1.14 0.035 0.045 E 6.35 6.73 0.250 0.265

b 0.64 0.89 0.025 0.035 E1 4.32 - 0.170 -

b1 0.65 0.79 0.026 0.031 e 2.29 BSC 2.29 BSC

b2 0.76 1.14 0.030 0.045 L 8.89 9.65 0.350 0.380

b3 0.76 1.04 0.030 0.041 L1 1.91 2.29 0.075 0.090

b4 4.95 5.46 0.195 0.215 L2 0.89 1.27 0.035 0.050

c 0.46 0.61 0.018 0.024 L3 1.14 1.52 0.045 0.060

c1 0.41 0.56 0.016 0.022 θ1 0' 15' 0' 15'

c2 0.46 0.86 0.018 0.034 θ2 25' 35' 25' 35'

D 5.97 6.22 0.235 0.245

ECN: S-82111-Rev. A, 15-Sep-08
DWG: 5968

Notes

1. Dimensioning and tolerancing per ASME Y14.5M-1994.

2. Dimension are shown in inches and millimeters.

3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.13 mm (0.005") per side. These dimensions are measured at the
outermost extremes of the plastic body.

4. Thermal pad contour optional with dimensions b4, L2, E1 and D1.

5. Lead dimension uncontrolled in L3.

6. Dimension b1, b3 and c1 apply to base metal only.

7. Outline conforms to JEDEC outline TO-251AA.

Document Number: 91362 www.vishay.com
Revision: 15-Sep-08 1

RECOMMENDED MINIMUM PADS FOR DPAK (TO-252)

0.224

(5.690)

Application Note 826

Vishay Siliconix

0.243
(6.180)

Return to Index

Return to Index

0.420
(10.668)

0.180

(4.572)

Recommended Minimum Pads

Dimensions in Inches/(mm)

0.087

0.090

0.055

(1.397)

(2.202)

(2.286)

APPLICATION NOTE

Document Number: 72594 www.vishay.com
Revision: 21-Jan-08 3

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Revision: 13-Jun-16

1

Document Number: 91000