Datasheet IRFS9N60A, SiHFS9N60A DataSheet (Vishay)

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N-Channel MOSFET
G
D
S
D2PAK (TO-263)
G
D
S
IRFS9N60A, SiHFS9N60A
Vishay Siliconix
Power MOSFET
PRODUCT SUMMARY
VDS (V) 600
R
()V
DS(on)
Q
max. (nC) 49
g
Q
(nC) 13
gs
Q
(nC) 20
gd
Configuration Single
= 10 V 0.75
GS
FEATURES
• Low gate charge Qg results in simple drive requirement
• Improved gate, avalanche and dynamic dV/dt ruggedness
• Fully characterized capacitance and avalanche voltage and current
• Material categorization: for definitions of compliance please see www.vishay.com/doc?99912
Note
*
Thi s datasheet pro vi des information about parts that are RoHS-compliant and / or parts that are non-RoHS-compliant. For example, parts with lead (Pb) terminations are not RoHS-compliant. Please see the information / tables in this datasheet for details.
APPLICATIONS
• Switch mode power supply (SMPS)
• Uninterruptible power supply
• High speed power switching
APPLICABLE OFF LINE SMPS TOPOLOGIES
• Active clamped forward
•Main switch
ORDERING INFORMATION
Package D2PAK (TO-263) D2PAK (TO-263) D2PAK (TO-263)
Lead (Pb)-free and Halogen-free SiHFS9N60A-GE3 SiHFS9N60ATRR-GE3
Lead (Pb)-free
IRFS9N60APbF IRFS9N60ATRRPbF
SiHFS9N60A-E3 SiHFS9N60ATR-E3
Note
a. See device orientation.
a
SiHFS9N60ATRL-GE3
a
IRFS9N60ATRLPbF
a
SiHFS9N60ATL-E3
Available
Available
  
a
a
a
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER SYMBOL LIMIT UNIT
Drain-Source Voltage V
Gate-Source Voltage V
T
= 25 °C
Continuous Drain Current V
Pulsed Drain Current
a
at 10 V
GS
C
= 100 °C 5.8
C
DS
± 30
GS
I
D
IDM 37
Linear Derating Factor 1.3 W/°C
Single Pulse Avalanche Energy
Repetitive Avalanche Current
Repetitive Avalanche Energy
Maximum Power Dissipation T
Peak Diode Recovery dV/dt
Operating Junction and Storage Temperature Range T
Soldering Recommendations (Peak temperature)
b
a
a
= 25 °C P
c
d
C
for 10 s 300
E
AS
I
AR
E
AR
D
dV/dt 5.0 V/ns
, T
J
stg
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Starting T c. I
SD
= 25 °C, L = 6.8 mH, Rg = 25 , IAS = 9.2 A (see fig. 12).
J
9.2 A, dI/dt 50 A/μs, VDD VDS, TJ 150 °C.
d. 1.6 mm from case.
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600
9.2
290 mJ
9.2 A
17 mJ
170 W
-55 to +150
Document Number: 91287
V
AT
°C
Page 2
IRFS9N60A, SiHFS9N60A
S
D
G
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THERMAL RESISTANCE RATINGS
PARAMETER SYMBOL TYP. MAX. UNIT
Maximum Junction-to-Ambient R
Maximum Junction-to-Case (Drain) R
thJA
thJC
-40
-0.75
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-Source Breakdown Voltage V
Temperature Coefficient
V
DS
Gate-Source Threshold Voltage V
Gate-Source Leakage I
Zero Gate Voltage Drain Current I
Drain-Source On-State Resistance R
Forward Transconductance g
DS
V
DS/TJ
GS(th)
V
GSS
DSS
VGS = 10 V ID = 5.5 A
DS(on)
fs
Dynamic
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Output Capacitance C
Effective Output Capacitance C
Total Gate Charge Q
Gate-Drain Charge Q
Turn-On Delay Time t
Rise Time t
Turn-Off Delay Time t
Fall Time t
Gate Input Resistance R
iss
- 180 -
oss
-7.1-
rss
oss
eff. VDS = 0 V to 480 V
oss
g
--13
gs
--20
gd
d(on)
r
-30-
d(off)
-22-
f
g
V
V
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current I
Pulsed Diode Forward Current
a
Body Diode Voltage V
Body Diode Reverse Recovery Time t
Body Diode Reverse Recovery Charge Q
Forward Turn-On Time t
S
I
SM
SD
rr
rr
on
MOSFET symbol showing the integral reverse p - n junction diode
TJ = 25 °C, IF = 9.2 A, dI/dt = 100 A/μs
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width 300 μs; duty cycle  2 %. c. C
eff. is a fixed capacitance that gives the same charging time as C
oss
VGS = 0, ID = 250 μA 600 - - V
Reference to 25 °C, I
= 1 mA
D
VDS = VGS, ID = 250 μA 2.0 - 4.0 V
= ± 30 V - - ± 100 nA
GS
VDS = 600 V, VGS = 0 V - - 25
= 480 V, VGS = 0 V, TJ = 125 °C - - 250
V
DS
b
VDS = 25 V, ID = 3.1 A 5.5 - - S
VGS = 0 V,
V
= 25 V,
DS
f = 1.0 MHz, see fig. 5
= 1.0 V, f = 1.0 MHz - 1957 -
V
DS
GS
= 10 V
GS
= 0 V
V
= 480 V, f = 1.0 MHz - 49 -
DS
= 9.2 A, VDS = 400 V
I
D
see fig. 6 and 13
V
= 300 V, ID = 9.2 A
DD
R
= 9.1 , RD = 35.5
g
see fig. 10
b
c
b
f = 1 MHz, open drain 0.5 - 3.2
TJ = 25 °C, IS = 9.2 A, VGS = 0 V
b
b
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
while VDS is rising from 0 to 80 % VDS.
oss
Vishay Siliconix
°C/W
-0.66-
- - 0.75
- 1400 -
-96-
--49
-13-
-25-
--9.2
--37
--1.5V
- 530 800 ns
-3.04.C
V/°C
μA
pF
nC Gate-Source Charge Q
ns
A
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Document Number: 91287
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0.1
1
10
100
0.1 1 10 100
20µs PULSE WIDTH T = 25 C
J
°
TOP
BOTTOM
VGS 15V 10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.7V
V , Drain-to-Source Voltage (V)
I , Drain-to-Source Current (A)
DS
D
4.7V
1
10
100
1 10 100
20µs PULSE WIDTH T = 150 C
J
°
TOP
BOTTOM
VGS 15V 10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.7V
V , Drain-to-Source Voltage (V)
I , Drain-to-Source Current (A)
DS
D
4.7V
0.1
1
10
100
4.0 5.0 6.0 7.0 8.0 9.0 10.0
V = 50V 20µs PULSE WIDTH
DS
V , Gate-to-Source Voltage (V)
I , Drain-to-Source Current (A)
GS
D
T = 25 C
J
°
T = 150 C
J
°
-60 -40 -20 0 20 40 60 80 100 120 140 160
0.0
0.5
1.0
1.5
2.0
2.5
3.0
T , Junction Temperature ( C)
r
DS(on)
, Drain-to-Source On Resistance
(Normalized)
J
°
V =
I =
GS
D
10V
9.2A
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
IRFS9N60A, SiHFS9N60A
Vishay Siliconix
Fig. 1 - Typical Output Characteristics
Fig. 2 - Typical Output Characteristics
Fig. 3 - Typical Transfer Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
S16-0763-Rev. D, 02-May-16
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0
400
800
1200
1600
2000
2400
1 10 100 1000
C, Capacitance (pF)
DS
V , Drain-to-Source Voltage (V)
A
V = 0V, f = 1MHz C = C + C , C SHORTED C = C C = C + C
GS iss g s gd d s rss gd oss ds gd
iss
oss
rss
0 10 20 30 40 50
0
4
8
12
16
20
Q , Total Gate Charge (nC)
V , Gate-to-Source Voltage (V)
G
GS
FOR TEST CIRCUIT
SEE FIGURE
I =
D
13
9.2A
V = 120V
DS
V = 300V
DS
V = 480V
DS
0.1
1
10
100
0.2 0.5 0.7 1.0 1.2
V ,Source-to-Drain Voltage (V)
I , Reverse Drain Current (A)
SD
SD
V = 0 V
GS
T = 25 C
J
°
T = 150 C
J
°
0.1
1
10
100
1000
10 100 1000 10000
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
Single Pulse
T T= 150 C
= 25 C
°
°
J
C
V , Drain-to-Source Voltage (V)
I , Drain Current (A)I , Drain Current (A)
DS
D
10us
100us
1ms
10ms
IRFS9N60A, SiHFS9N60A
Vishay Siliconix
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 1 - Maximum Safe Operating Area
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25 50 75 100 125 150
0.0
2.0
4.0
6.0
8.0
10.0
T , Case Temperature ( C)
I , Drain Current (A)
°
C
D
Pulse width 1 µs Duty factor 0.1 %
R
D
V
GS
R
g
D.U.T.
10 V
+
-
V
DS
V
DD
V
DS
90 %
10 %
V
GS
t
d(on)
t
r
t
d(off)
t
f
0.01
0.1
1
0.00001 0.0001 0.001 0.01 0.1 1
Notes:
1. Duty factor D = t / t
2. Peak T =P x Z + T
1 2
J DM thJC C
P
t
t
DM
1
2
t , Rectangular Pulse Duration (sec)
Thermal Response
(Z )
1
thJC
0.01
0.02
0.05
0.10
0.20
D = 0.50
SINGLE PULSE
(THERMAL RESPONSE)
A
R
g
I
AS
0.01 Ω
t
p
D.U.T
L
V
DS
+
-
V
DD
Driver
15 V
20 V
IRFS9N60A, SiHFS9N60A
Vishay Siliconix
Fig. 10a - Switching Time Test Circuit
Fig. 8 - Maximum Drain Current vs. Case Temperature
Fig. 10b - Switching Time Waveforms
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
V
t
p
DS
I
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Fig. 12a - Unclamped Inductive Test Circuit
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AS
Fig. 12b - Unclamped Inductive Waveforms
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25 50 75 100 125 150
0
100
200
300
400
500
600
Starting T , Junction Temperature ( C)
E , Single Pulse Avalanche Energy (mJ)
J
AS
°
I
D
TOP
BOTTOM
4.1A
5.8A
9.2A
Q
GS
Q
GD
Q
G
V
G
Charge
10 V
IRFS9N60A, SiHFS9N60A
Vishay Siliconix
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
0.2 µF
12 V
V
GS
0.3 µF
D.U.T.
3 mA
I
G
Current sampling resistors
I
D
+
-
Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit
V
DS
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Document Number: 91287
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IRFS9N60A, SiHFS9N60A
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
D.U.T.
+
-
R
g
Driver gate drive
P.W.
+
Circuit layout considerations
• Low stray inductance
Ground plane
• Low leakage inductance current transformer
-
• dV/dt controlled by R
• Driver same type as D.U.T. controlled by duty factor “D”
• I
SD
• D.U.T. - device under test
Period
-
g
D =
P.W.
Period
+
+
V
DD
-
VGS = 10 V a
waveform
SD
Body diode forward
Body diode forward drop
Ripple ≤ 5 %
= 5 V for logic level devices
GS
current
dI/dt
Diode recovery
dV/dt
V
DD
I
SD
Reverse recovery current
Re-applied voltage
D.U.T. I
D.U.T. VDSwaveform
Inductor current
Note
a. V
Fig. 14 - For N-Channel
        
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91287
S16-0763-Rev. D, 02-May-16
.
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Page 8
TO-263AB (HIGH VOLTAGE)
(Datum A)
34
E
L1
4
D
L2
4
C
1
B
B
C
3
2
B
B
Package Information
Vishay Siliconix
A
A
5
H
Detail A
B
A
c2
Gauge plane
0° to
L
L3
L4
Detail “A” Rotated 90° CW scale 8:1
H
B
Seating plane
A1
2 x e
Lead tip
2 x b2
2 x b
0.010 A B
MM
Plating
(c)
Section B - B and C - C
c
± 0.004 B
5
b1, b3
(b, b2)
Scale: none
M
Base metal
c1
A
E
D1
4
5
E1
View A - A
4
MILLIMETERS INCHES MILLIMETERS INCHES
DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX.
A 4.06 4.83 0.160 0.190 D1 6.86 - 0.270 -
A1 0.00 0.25 0.000 0.010 E 9.65 10.67 0.380 0.420
b 0.51 0.99 0.020 0.039 E1 6.22 - 0.245 -
b1 0.51 0.89 0.020 0.035 e 2.54 BSC 0.100 BSC
b2 1.14 1.78 0.045 0.070 H 14.61 15.88 0.575 0.625
b3 1.14 1.73 0.045 0.068 L 1.78 2.79 0.070 0.110
c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.066
c1 0.38 0.58 0.015 0.023 L2 - 1.78 - 0.070
c2 1.14 1.65 0.045 0.065 L3 0.25 BSC 0.010 BSC
D 8.38 9.65 0.330 0.380 L4 4.78 5.28 0.188 0.208
ECN: S-82110-Rev. A, 15-Sep-08 DWG: 5970
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions are shown in millimeters (inches).
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outmost extremes of the plastic body at datum A.
4. Thermal PAD contour optional within dimension E, L1, D1 and E1.
5. Dimension b1 and c1 apply to base metal only.
6. Datum A and B to be determined at datum plane H.
7. Outline conforms to JEDEC outline to TO-263AB.
Document Number: 91364 www.vishay.com Revision: 15-Sep-08 1
Page 9
RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead
0.420
(10.668)
0.635 (16.129)
0.355
AN826
Vishay Siliconix
(9.017)
Return to Index
0.135
(3.429)
0.200
(5.080)
Recommended Minimum Pads
Dimensions in Inches/(mm)
0.050
(1.257)
0.145
(3.683)
Document Number: 73397 11-Apr-05
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Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
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Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special, consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular purpose, non-infringement and merchantability.
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Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the Vishay product could result in personal injury or death. Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.
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Revision: 13-Jun-16
1
Document Number: 91000
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