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N-Channel MOSFET
G
D
S
Available
Available
IRFS11N50A, SiHFS11N50A
Vishay Siliconix
Power MOSFET
PRODUCT SUMMARY
VDS (V) 500
R
()V
DS(on)
Q
(Max.) (nC) 52
g
Q
(nC) 13
gs
Q
(nC) 18
gd
Configuration Single
= 10 V 0.52
GS
FEATURES
• Low Gate Charge Qg results in Simple Drive
Requirement
• Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
• Fully Characterized Capacitance and
Avalanche Voltage and Current
• Effective C
Specified
oss
• Material categorization: For definitions of compliance
D2PAK (TO-263)
D
G
S
please see www.vishay.com/doc?99912
Note
*
Thi s datasheet pro vi des information about parts that are
RoHS-compliant and/or parts that are non-RoHS-compliant. For
example, parts with lead (Pb) terminations are not RoHS-compliant.
Please see the information/tables in this datasheet for details.
APPLICATIONS
• Switch Mode Power Supply (SMPS)
• Uninterruptible Power Supply
• High Speed Power Switching
TYPICAL SMPS TOPOLOGIES
• Two Transistor Forward
• Half and Full Bridge
• Power Factor Correction Boost
ORDERING INFORMATION
Package D2PAK (TO-263) D2PAK (TO-263) D2PAK (TO-263)
Lead (Pb)-free and Halogen-free SiHFS11N50A-GE3 SiHFS11N50ATRR-GE3
Lead (Pb)-free IRFS11N50APbF IRFS11N50ATRRP
Note
a. See device orientation.
a
a
SiHFS11N50ATRL-GE3
IRFS11N50ATRLP
a
a
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER SYMBOL LIMIT UNIT
Drain-Source Voltage V
Gate-Source Voltage V
T
= 25 °C
Continuous Drain Current V
Pulsed Drain Current
a
at 10 V
GS
C
= 100 °C
C
DS
GS
I
D
IDM
Linear Derating Factor
Single Pulse Avalanche Energy
Repetitive Avalanche Current
Repetitive Avalanche Energy
Maximum Power Dissipation T
Peak Diode Recovery dV/dt
Operating Junction and Storage Temperature Range T
Soldering Recommendations (Peak Temperature)
b
a
a
= 25 °C P
c
d
C
for 10 s
E
AS
I
AR
E
AR
D
dV/dt
, T
J
stg
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Starting T
c. I
SD
d. 1.6 mm from case.
S13-1927-Rev. E, 09-Sep-13
= 25 °C, L = 4.5 mH, Rg = 25 , IAS = 11 A (see fig. 12).
J
11 A, dI/dt 140 A/μs, VDD VDS, TJ 150 °C.
1
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
500
± 30
11
7.0
44
1.3
275
11
17
170
6.9
- 55 to + 150
300
Document Number: 91286
V
AT
W/°C
mJ
A
mJ
W
V/ns
°C
Page 2
IRFS11N50A, SiHFS11N50A
www.vishay.com
THERMAL RESISTANCE RATINGS
PARAMETER SYMBOL TYP. MAX. UNIT
Maximum Junction-to-Case (Drain) R
Maximum Junction-to-Ambient R
thJC
thCS
thJA
-0.75
0.50 -
-62
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-Source Breakdown Voltage V
Temperature Coefficient
V
DS
Gate-Source Threshold Voltage V
Gate-Source Leakage I
Zero Gate Voltage Drain Current I
Drain-Source On-State Resistance R
Forward Transconductance g
DS
V
DS/TJ
GS(th)
V
GSS
DSS
VGS = 10 V ID = 6.6 A
DS(on)
fs
Dynamic
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Output Capacitance C
Effective Output Capacitance C
Total Gate Charge Q
Gate-Drain Charge Q
Turn-On Delay Time t
Rise Time t
Turn-Off Delay Time t
Fall Time t
iss
- 208 -
oss
-8.1-
rss
oss
eff. VDS = 0 V to 400 V
oss
g
--13
gs
--18
gd
d(on)
r
-32-
d(off)
-28-
f
V
V
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current I
Pulsed Diode Forward Current
a
Body Diode Voltage V
Body Diode Reverse Recovery Time t
Body Diode Reverse Recovery Charge Q
Forward Turn-On Time t
S
I
SM
SD
rr
rr
on
MOSFET symbol
showing the
integral reverse
p - n junction diode
TJ = 25 °C, IF = 11 A, dI/dt = 100 A/μs
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width 300 μs; duty cycle 2 %.
c. C
eff. is a fixed capacitance that gives the same charging time as C
oss
VGS = 0, ID = 250 μA 500 - - V
Reference to 25 °C, I
= 1 mA
D
VDS = VGS, ID = 250 μA 2.0 - 4.0 V
= ± 30 V - - ± 100 nA
GS
VDS = 500 V, VGS = 0 V - - 25
= 400 V, VGS = 0 V, TJ = 125 °C - - 250
V
DS
b
VDS = 50 V, ID = 6.6 A 6.1 - - S
VGS = 0 V,
= 25 V,
V
DS
f = 1.0 MHz, see fig. 5
= 1.0 V, f = 1.0 MHz - 2000 -
V
DS
= 0 V
GS
= 10 V
GS
TJ = 25 °C, IS = 11 A, VGS = 0 V
V
= 400 V, f = 1.0 MHz - 55 -
DS
= 11 A, VDS = 400 V
I
D
see fig. 6 and 13
V
= 250 V, ID = 11 A
DD
R
= 9.1 , RD = 22
g
see fig. 10
c
b
b
D
G
S
b
b
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
while VDS is rising fom 0 % VDS to 80 % VDS.
oss
Vishay Siliconix
°C/WCase-to-Sink, Flat, Greased Surface R
-0.060-
- - 0.52
- 1423 -
-97-
--52
-14-
-35-
--11
--44
--1.5V
- 510 770 ns
-3.45.1μC
V/°C
μA
pF
nC Gate-Source Charge Q
ns
A
S13-1927-Rev. E, 09-Sep-13
2
Document Number: 91286
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Page 3
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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
IRFS11N50A, SiHFS11N50A
Vishay Siliconix
Fig. 1 - Typical Output Characteristics
Fig. 2 - Typical Output Characteristics
Fig. 3 - Typical Transfer Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
S13-1927-Rev. E, 09-Sep-13
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Document Number: 91286
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IRFS11N50A, SiHFS11N50A
Vishay Siliconix
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
S13-1927-Rev. E, 09-Sep-13
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
4
Document Number: 91286
Page 5
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Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
R
D
V
GS
R
g
D.U.T.
10 V
+
-
V
DS
V
DD
Fig. 9 - Maximum Drain Current vs. Case Temperature
IRFS11N50A, SiHFS11N50A
Vishay Siliconix
Fig. 10a - Switching Time Test Circuit
V
DS
90 %
10 %
V
GS
t
t
d(on)
r
Fig. 10b - Switching Time Waveforms
t
d(off)
t
f
S13-1927-Rev. E, 09-Sep-13
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
V
15 V
V
DS
R
g
20 V
L
D.U.T.
I
AS
0.01 Ω
t
p
Driver
Fig. 12a - Unclamped Inductive Test Circuit
t
p
+
V
A
DD
-
I
AS
Fig. 12b - Unclamped Inductive Waveforms
5
DS
Document Number: 91286
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Page 6
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Q
GS
Q
GD
Q
G
V
G
Charge
V
GS
D.U.T.
3 mA
V
GS
V
DS
I
G
I
D
0.3 µF
0.2 µF
50 kΩ
12 V
Current regulator
Current sampling resistors
Same type as D.U.T.
+
-
IRFS11N50A, SiHFS11N50A
Vishay Siliconix
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Fig. 13a - Basic Gate Charge Waveform
Fig. 12d - Typical Drain-to-Source Voltage
vs. Avalanche Current
Fig. 13b - Gate Charge Test Circuit
S13-1927-Rev. E, 09-Sep-13
6
Document Number: 91286
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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IRFS11N50A, SiHFS11N50A
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
D.U.T.
+
-
R
g
Driver gate drive
P.W.
+
-
Period
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
• dV/dt controlled by R
• Driver same type as D.U.T.
I
controlled by duty factor “D”
•
SD
• D.U.T. - device under test
-
D =
g
P.W.
Period
+
+
V
DD
-
V
= 10 Va
GS
D.U.T. l
Reverse
recovery
current
D.U.T. V
Re-applied
voltage
Inductor current
Note
a. V
waveform
SD
Body diode forward
waveform
DS
Body diode forward drop
Ripple ≤ 5 %
= 5 V for logic level devices
GS
current
dI/dt
Diode recovery
dV/dt
V
DD
I
SD
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91286
.
S13-1927-Rev. E, 09-Sep-13
7
Document Number: 91286
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Page 8
TO-263AB (HIGH VOLTAGE)
(Datum A)
34
E
L1
4
D
L2
4
C
1
B
B
C
3
2
B
B
Package Information
Vishay Siliconix
A
A
5
H
Detail A
B
A
c2
Gauge
plane
0° to 8°
L
L3
L4
Detail “A”
Rotated 90° CW
scale 8:1
H
B
Seating plane
A1
2 x e
Lead tip
2 x b2
2 x b
0.010 A B
MM
Plating
(c)
Section B - B and C - C
c
± 0.004 B
5
b1, b3
(b, b2)
Scale: none
M
Base
metal
c1
A
E
D1
4
5
E1
View A - A
4
MILLIMETERS INCHES MILLIMETERS INCHES
DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX.
A 4.06 4.83 0.160 0.190 D1 6.86 - 0.270 -
A1 0.00 0.25 0.000 0.010 E 9.65 10.67 0.380 0.420
b 0.51 0.99 0.020 0.039 E1 6.22 - 0.245 -
b1 0.51 0.89 0.020 0.035 e 2.54 BSC 0.100 BSC
b2 1.14 1.78 0.045 0.070 H 14.61 15.88 0.575 0.625
b3 1.14 1.73 0.045 0.068 L 1.78 2.79 0.070 0.110
c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.066
c1 0.38 0.58 0.015 0.023 L2 - 1.78 - 0.070
c2 1.14 1.65 0.045 0.065 L3 0.25 BSC 0.010 BSC
D 8.38 9.65 0.330 0.380 L4 4.78 5.28 0.188 0.208
ECN: S-82110-Rev. A, 15-Sep-08
DWG: 5970
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions are shown in millimeters (inches).
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the
outmost extremes of the plastic body at datum A.
4. Thermal PAD contour optional within dimension E, L1, D1 and E1.
5. Dimension b1 and c1 apply to base metal only.
6. Datum A and B to be determined at datum plane H.
7. Outline conforms to JEDEC outline to TO-263AB.
Document Number: 91364 www.vishay.com
Revision: 15-Sep-08 1
Page 9
RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead
0.420
(10.668)
0.635
(16.129)
0.355
AN826
Vishay Siliconix
(9.017)
Return to Index
0.135
(3.429)
0.200
(5.080)
Recommended Minimum Pads
Dimensions in Inches/(mm)
0.050
(1.257)
0.145
(3.683)
Document Number: 73397
11-Apr-05
www.vishay.com
1
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Disclaimer
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“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
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product with the properties described in the product specification is suitable for use in a particular application. Parameters
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Material Category Policy
Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the
definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment
(EEE) - recast, unless otherwise specified as non-compliant.
Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.
Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free
requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21
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Revision: 02-Oct-12
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