Datasheet IRFP32N50K, SiHFP32N50K DataSheet (Vishay)

IRFP32N50K, SiHFP32N50K

N-Channel MOSFET

G

D

S

TO-247AC

G

D

S

Available

RoHS*

COMPLIANT

Power MOSFET

Vishay Siliconix

PRODUCT SUMMARY

VDS (V) 500

R

(Ω)V

DS(on)

Q

(Max.) (nC) 190

g

Q

(nC) 59

gs

Q

(nC) 84

gd

Configuration Single

= 10 V 0.135

GS

FEATURES

• Low Gate Charge Qg Results in Simple Drive
Requirement

• Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness

• Fully Characterized Capacitance and Avalanche Voltage
and Current

•Low R

• Compliant to RoHS Directive 2002/95/EC

APPLICATIONS

• Switch Mode Power Supply (SMPS)

• Uninterruptible Power Supply

• High Speed Power Switching

• Hard Switching and High Frequency Circuits

ORDERING INFORMATION

Package TO-247AC

Lead (Pb)-free

SnPb

IRFP32N50KPbF
SiHFP32N50K-E3
IRFP32N50K
SiHFP32N50K

DS(on)

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT

Drain-Source Voltage V

Gate-Source Voltage V

T

= 25 °C

Continuous Drain Current V

Pulsed Drain Current

a

at 10 V

GS

C

= 100 °C 20

C

DS

± 30

GS

I

D

IDM 130

Linear Derating Factor 3.7 W/°C

Single Pulse Avalanche Energy

Repetitive Avalanche Current

Repetitive Avalanche Energy

Maximum Power Dissipation T

Peak Diode Recovery dV/dt

Operating Junction and Storage Temperature Range T

b

a

a

= 25 °C P

c

C

E

AS

I

AR

E

AR

D

dV/dt 13 V/ns

, T

J

stg

Soldering Recommendations (Peak Temperature) for 10 s 300

Mounting Torque 6-32 or M3 screw

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature.
b. Starting T
c. I

SD

= 25 °C, L = 0.87 mH, Rg = 25 Ω, IAS = 32 A.

J

≤ 32 A, dI/dt ≤ 197 A/μs, VDD ≤ VDS, TJ ≤ 150 °C.

d. 1.6 mm from case.

* Pb containing terminations are not RoHS compliant, exemptions may apply

Document Number: 91221 www.vishay.com
S11-0448-Rev. C, 14-Mar-11 1

THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

This datasheet is subject to change without notice.

500

32

450 mJ

32 A

46 mJ

460 W

- 55 to + 150

d

10 lbf · in

1.1 N · m

www.vishay.com/doc?91000

V

AT

°C

IRFP32N50K, SiHFP32N50K

Vishay Siliconix

THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL TYP. MAX. UNIT

Maximum Junction-to-Ambient R

Maximum Junction-to-Case (Drain) R

thJA

thCS

thJC

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

Static

Drain-Source Breakdown Voltage V

Temperature Coefficient ΔVDS/TJ Reference to 25 °C, ID = 1 mA - 0.54 - V/°C

V

DS

Gate-Source Threshold Voltage V

Gate-Source Leakage I

Zero Gate Voltage Drain Current I

Drain-Source On-State Resistance R

Forward Transconductance g

Dynamic

Input Capacitance C

Output Capacitance C

Reverse Transfer Capacitance C

Output Capacitance C

Effective Output Capacitance C

Total Gate Charge Q

Gate-Drain Charge Q

Turn-On Delay Time t

Rise Time t

Turn-Off Delay Time t

Fall Time t

Drain-Source Body Diode Characteristics

Continuous Source-Drain Diode Current I

Pulsed Diode Forward Current

a

Body Diode Voltage V

Body Diode Reverse Recovery Time t

Body Diode Reverse Recovery Charge Q

Body Diode Reverse Recovery Current I

Forward Turn-On Time t

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature.
b. Pulse width ≤ 400 μs; duty cycle ≤ 2 %.
c. C

eff. is a fixed capacitance that gives the same charging time as C

oss

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2 S11-0448-Rev. C, 14-Mar-11

THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

DS

GS(th)

V

GSS

DSS

VGS = 10 V ID = 32 A

DS(on)

fs

iss

- 550 -

oss

-45-

rss

oss

eff. VDS = 0 V to 400 V

oss

g

--84

gd

d(on)

r

-48-

d(off)

-54-

f

S

V

V

GS

V

GS

MOSFET symbol
showing the
integral reverse

I

SM

SD

rr

RRM

on

rr

p - n junction diode

TJ = 25 °C, IF = 32 A, dI/dt = 100 A/μs

This datasheet is subject to change without notice.

-40

0.24 -

°C/WCase-to-Sink, Flat, Greased Surface R

-0.26

VGS = 0 V, ID = 250 μA 500 - - V

VDS = VGS, ID = 250 μA 3.0 - 5.0 V

= ± 30 V - - ± 100 nA

GS

VDS = 500 V, VGS = 0 V - - 50

= 400 V, VGS = 0 V, TJ = 150 °C - - 250

DS

b

- 0.135 0.16 Ω

VDS = 50 V, ID = 32 A 14 - - S

VGS = 0 V,

V

= 25 V,

DS

f = 1.0 MHz, see fig. 5

= 1.0 V, f = 1.0 MHz - 5630 -

V

DS

= 0 V

V

= 400 V, f = 1.0 MHz - 155 -

DS

c

- 5280 -

- 265 -

- - 190

= 10 V ID = 32 A, VDS = 400 Vb

-28-

= 250 V, ID = 32 A,

V

DD

Rg = 4.3 Ω, V

GS

= 10 V

b

G

TJ = 25 °C, IS = 32 A, VGS = 0 V

D

S

b

- 120 -

--32

- - 130

--1.5V

- 530 800 ns

b

- 9.0 13.5 μC

-30-A

Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)

while VDS is rising from 0 % to 80 % VDS.

oss

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μA

pF

nC Gate-Source Charge Qgs --59

ns

A

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

VDS, Drain-to-Source Voltage (V)

I

D

, Drain-to-Source Current (A)

0.1

1

10

100

0.01

0.1

1

10

1000

VGS
15 V
12 V
10 V

8.0 V

7.0 V

6.0 V

5.5 V

5.0 V

Top

Bottom

5.0 V

20 μs PULSE WIDTH
TJ = 25 °C

100

VGS
15 V
12 V
10 V

8.0 V

7.0 V

6.0 V

5.5 V

5.0 V

Bottom

Top

5.0 V

20 μs PULSE WIDTH
TJ = 150 °C

I

D

, Drain-to-Source Current (A)

0.1

1

10

100

VDS, Drain-to-Source Voltage (V)

0.1

1

10

100

TJ, Junction Temperature

R

DS(on)

, Drain-to-Source On Resistance (Normalized)

- 60

- 20

- 40

0

20

40

6080100

120

140

160

0.0

0.5

1.0

1.5

2.0

2.5

3.0
ID = 32 A

VGS = 10 V

IRFP32N50K, SiHFP32N50K

Vishay Siliconix

1000

Fig. 1 - Typical Output Characteristics

100

TJ = 150 °C

10

, Drain-to-Source Current (A)

1

D

I

0.1
5

4

VGS, Gate-to-Source Voltage (V)

Fig. 3 - Typical Transfer Characteristics

TJ = 25 °C

7

VDS = 50 V
20 μs PULSE WIDTH

8

911

12

Document Number: 91221 www.vishay.com
S11-0448-Rev. C, 14-Mar-11 3

THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

Fig. 2 - Typical Output Characteristics

Fig. 4 - Normalized On-Resistance vs. Temperature

This datasheet is subject to change without notice.

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IRFP32N50K, SiHFP32N50K

1

10

100

1000

10

100

1000

10 000

100 000

C, Capacitance (pF)

VDS, Drain-to-Source Voltage (V)

C

rss

C

oss

C

iss

VGS = 0 V, f = 1 MHz
C

iss

= Cgs + Cgd, Cds SHORTED

C

rss

= C

gd

C

oss

= Cds + C

gd

VSD, Source-to-Drain Voltage (V)

I

SD

, Reverse Drain Current (A)

1000

0.2

0.9

0.6

1.3

1.6

0.1

100

10

1

TJ = 150 °C

TJ = 25 °C

VGS = 0 V

OPERATING IN THIS AREA LIMITED

BY R

DS(on)

10 ms

1 ms

100 μs

10 μs

TC = 25 °C
TJ = 150 °C
Single Pulse

10

100

1000

10000

1

10

100

1000

I

D

, Drain Current (A)

VDS, Drain-to-Source Voltage (V)

Vishay Siliconix

www.vishay.com Document Number: 91221
4 S11-0448-Rev. C, 14-Mar-11

THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

20

16

12

8

, Gate-to-Source Voltage (V)

GS

V

4

0

0

ID = 32 A

40

QG, Total Gate Charge (nC)

80

VDS = 400 V
VDS = 250 V
VDS = 100 V

120

160

Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage

This datasheet is subject to change without notice.

Fig. 7 - Typical Source-Drain Diode Forward Voltage

200

Fig. 8 - Maximum Safe Operating Area

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IRFP32N50K, SiHFP32N50K

TC, Case Temperature (°C)

I

D

, Drain Current (A)

50

75

100

125

150

0

5

10

15

20

25

25

30

35

V

DS

90 %

10 %

V

GS

t

d(on)

t

r

t

d(off)

t

f

0.001

0.01

0.1

1

0.00001

0.0001 0.001 0.01 0.1 1

t , Rectangular Pulse Duration (sec)

Thermal Response (Z

thJC

)

0.01

0.05

0.20

D = 0.50

SINGLE PULSE

(THERMAL RESPONSE)

0.02

0.10

t

1

t

2

Notes:

1. Duty factor D = t1/ t

2

2. Peak TJ = PDM x Z

thJC

+ T

C

P

DM

Vishay Siliconix

R

D.U.T.

D

+

V

-

DD

V

DS

V

GS

R

G

10 V

Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %

Fig. 10a - Switching Time Test Circuit

Fig. 9 - Maximum Drain Current vs. Case Temperature

Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig. 10b - Switching Time Waveforms

Document Number: 91221 www.vishay.com
S11-0448-Rev. C, 14-Mar-11 5

THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

This datasheet is subject to change without notice.

www.vishay.com/doc?91000

IRFP32N50K, SiHFP32N50K

A

R

G

I

AS

0.01 Ω

t

p

D.U.T

L

V

DS

+

-

V

DD

Driver

15 V

20 V

D.U.T.

3 mA

V

GS

V

DS

I

G

I

D

0.3 µF

0.2 µF

50 kΩ

12 V

Current regulator

Current sampling resistors

Same type as D.U.T.

+

-

Vishay Siliconix

Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms

V

DS

t

p

I

AS

10 V

800

I
TOP 7 A

D

10 A

640

BOTTOM 16 A

480

320

, Single Pulse Avalanche Energy (mJ)

160

AS

E

0

25

50

75

100

125

150

Starting TJ, Junction Temperature (°C)

Fig. 12c - Maximum Avalanche Energy vs. Drain Current

Q

G

Q

GS

V

G

Q

GD

Charge

Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit

This datasheet is subject to change without notice.

www.vishay.com/doc?91000

www.vishay.com Document Number: 91221
6 S11-0448-Rev. C, 14-Mar-11

THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

P.W.

Period

dI/dt

Diode recovery

dV/dt

Ripple ≤ 5 %

Body diode forward drop

Re-applied
voltage

Reverse
recovery
current

Body diode forward

current

V

GS

= 10 Va

I

SD

Driver gate drive

D.U.T. l

SD

waveform

D.U.T. V

DS

waveform

Inductor current

D =

P.W.

Period

+

-

+

+

+

-

-

-

Peak Diode Recovery dV/dt Test Circuit

V

DD

• dV/dt controlled by R

g

• Driver same type as D.U.T.

•

I

SD

controlled by duty factor “D”

• D.U.T. - device under test

D.U.T.

Circuit layout considerations

• Low stray inductance

• Ground plane

• Low leakage inductance

current transformer

R

g

Note

a. V

GS

= 5 V for logic level devices

V

DD

IRFP32N50K, SiHFP32N50K

Vishay Siliconix

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon

Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and

reliability data, see www.vishay.com/ppg?91221

Document Number: 91221 www.vishay.com
S11-0448-Rev. C, 14-Mar-11 7

THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

.

This datasheet is subject to change without notice.

Fig. 14 - For N-Channel

www.vishay.com/doc?91000

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0.10 AC

M M

E

E/2

(2)

(4)

R/2

B

2 x R

S

D

See view B

2 x e

b4

3 x b

2 x b2

L

C

L1

1

2

3

Q

D

A

A2

A

A

A1

C

Ø k BD

M M

A

ØP

(Datum B)

ØP1

D1

4

E1

0.01 BD

M M

View A - A

Thermal pad

D2

DDE E

C

C

View B

(b1, b3, b5)

Base metal

c1

(b, b2, b4)

Section C - C, D - D, E - E

(c)

Planting

4

3

5

7

4

4

4

Lead Assignments

1. Gate

2. Drain

3. Source

4. Drain

Package Information

Vishay Siliconix

TO-247AC (High Voltage)

MILLIMETERS INCHES MILLIMETERS INCHES

DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX.

A 4.58 5.31 0.180 0.209 D2 0.51 1.30 0.020 0.051
A1 2.21 2.59 0.087 0.102 E 15.29 15.87 0.602 0.625
A2 1.17 2.49 0.046 0.098 E1 13.72 - 0.540 -

b 0.99 1.40 0.039 0.055 e 5.46 BSC 0.215 BSC
b1 0.99 1.35 0.039 0.053 Ø k 0.254 0.010
b2 1.53 2.39 0.060 0.094 L 14.20 16.25 0.559 0.640
b3 1.65 2.37 0.065 0.093 L1 3.71 4.29 0.146 0.169
b4 2.42 3.43 0.095 0.135 N 7.62 BSC 0.300 BSC
b5 2.59 3.38 0.102 0.133 Ø P 3.51 3.66 0.138 0.144

c 0.38 0.86 0.015 0.034 Ø P1 - 7.39 - 0.291
c1 0.38 0.76 0.015 0.030 Q 5.31 5.69 0.209 0.224

D 19.71 20.82 0.776 0.820 R 4.52 5.49 0.178 0.216
D1 13.08 - 0.515 - S 5.51 BSC 0.217 BSC

ECN: X13-0103-Rev. D, 01-Jul-13
DWG: 5971

Notes

1. Dimensioning and tolerancing per ASME Y14.5M-1994.

2. Contour of slot optional.

3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at
the outermost extremes of the plastic body.

4. Thermal pad contour optional with dimensions D1 and E1.

5. Lead finish uncontrolled in L1.

6. Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154").

7. Outline conforms to JEDEC outline TO-247 with exception of dimension c.

8. Xian and Mingxin actually photo.

Revision: 01-Jul-13

Document Number: 91360

1

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Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over
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Revision: 13-Jun-16

1

Document Number: 91000