Datasheet IRFBC40AS, SiHFBC40AS DataSheet (Vishay)

N-Channel MOSFET

G

D

S

D2PAK (TO-263)

G

D

S

Power MOSFET

IRFBC40AS, SiHFBC40AS

Vishay Siliconix

PRODUCT SUMMARY

VDS (V) 600

()V

R

DS(on)

Q

(Max.) (nC) 42

g

Q

(nC) 10

gs

Q

(nC) 20

gd

Configuration Single

= 10 V 1.2

GS

FEATURES

• Halogen-free According to IEC 61249-2-21
Definition

• Low Gate Charge Q
Requirement

• Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness

• Fully Characterized Capacitance and Avalanche Voltage
and Current

• Effective C

Specified

oss

results in Simple Drive

g

• Compliant to RoHS Directive 2002/95/EC

APPLICATIONS

• Switch Mode Power Supply (SMPS)

• Uninterruptible Power Supply

• High Speed Power Switching

TYPICAL SMPS TOPOLOGIES

• Single Transistor Forward

ORDERING INFORMATION

Package D2PAK (TO-263) D2PAK (TO-263) D2PAK (TO-263)

a

Lead (Pb)-free and Halogen-free SiHFBC40AS-GE3 SiHFBC40ASTRL-GE3

Lead (Pb)-free

IRFBC40ASPbF IRFBC40ASTRLPbF

SiHFBC40AS-E3 SiHFBC40ASTL-E3

Note

a. See device orientation.

SiHFBC40ASTRR-GE3a

a

IRFBC40ASTRRPbFa

a

SiHFBC40ASTR-E3

a

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT

Drain-Source Voltage V

Gate-Source Voltage V

T

= 25 °C

Continuous Drain Current

Pulsed Drain Current

a, e

e

VGS at 10 V

C

T

= 100 °C 3.9

C

DS

± 30

GS

I

D

IDM 25

Linear Derating Factor 1.0 W/°C

c, e

b

a

a

= 25 °C P

C

E

AS

I

AR

E

AR

D

dV/dt 6.0 V/ns

, T

J

stg

Single Pulse Avalanche Energy

Repetitive Avalanche Current

Repetitive Avalanche Energy

Maximum Power Dissipation T

Peak Diode Recovery dV/dt

Operating Junction and Storage Temperature Range T

Soldering Recommendations (Peak Temperature) for 10 s 300

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Starting T
c. I

SD

d. 1.6 mm from case.

= 25 °C, L = 29.6 mH, Rg = 25 , IAS = 6.2 A (see fig. 12).

J

 6.2 A, dI/dt  88 A/μs, VDD  VDS, TJ  150 °C.

e. Uses IRFBC40A, SiHFBC40A data and test conditions.

* Pb containing terminations are not RoHS compliant, exemptions may apply

Document Number: 91113

www.vishay.com

S11-1053-Rev. C, 30-May-11 1

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

600

6.2

570 mJ

6.2 A

13 mJ

125 W

- 55 to + 150

d

www.vishay.com/doc?91000

V

A

°C

IRFBC40AS, SiHFBC40AS

Vishay Siliconix

THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL TYP. MAX. UNIT

Maximum Junction-to-Ambient R

Maximum Junction-to-Case (Drain) R

thJA

thJC

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

Static

Drain-Source Breakdown Voltage V

Temperature Coefficient

V

DS

Gate-Source Threshold Voltage V

Gate-Source Leakage I

Zero Gate Voltage Drain Current I

Drain-Source On-State Resistance R

Forward Transconductance g

Dynamic

Input Capacitance C

Output Capacitance C

Reverse Transfer Capacitance C

Output Capacitance C

Output Capacitance Effective C

Total Gate Charge Q

Gate-Drain Charge Q

Turn-On Delay Time t

Rise Time t

Turn-Off Delay Time t

Fall Time t

Drain-Source Body Diode Characteristics

Continuous Source-Drain Diode Current I

Pulsed Diode Forward Current

a

Body Diode Voltage V

Body Diode Reverse Recovery Time t

Body Diode Reverse Recovery Charge Q

Forward Turn-On Time t

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width  300 μs; duty cycle  2 %.
c. C

eff. is a fixed capacitance that gives the same charging time as C

OSS

d. Uses IRHFBC40A/SiHFBC40A data and test conditions.

DS

V

DS/TJ

GS(th)

V

GSS

DSS

VGS = 10 V ID = 3.7 A

DS(on)

fs

iss

- 136 -

oss

-7.0-

rss

oss

eff. VDS = 0 V to 480 V

oss

g

--

gs

--

gd

d(on)

r

-31-

d(off)

-18-

f

S

V

V

GS

V

GS

MOSFET symbol
showing the
integral reverse

I

SM

SD

rr

rr

on

p - n junction diode

TJ = 25 °C, IF = 6.2 A, dI/dt = 100 A/μs

-40

-1.0

°C/W

VGS = 0 V, ID = 250 μA 600 - - V

Reference to 25 °C, I

= 1 mA

D

d

-0.66-

VDS = VGS, ID = 250 μA 2.0 - 4.0 V

= ± 30 V - - ± 100 nA

GS

VDS = 600 V, VGS = 0 V - - 25

= 480 V, VGS = 0 V, TJ = 125 °C - - 250

DS

b

--1.2

VDS = 50 V, ID = 3.7 A 3.4 - - S

VGS = 0 V,

V

= 25 V,

DS

f = 1.0 MHz, see fig. 5

= 1.0 V, f = 1.0 MHz - 1487 -

V

DS

= 0 V

= 10 V

V

= 480 V, f = 1.0 MHz - 36 -

DS

= 6.2 A, VDS = 480 V,

I

D

see fig. 6 and 13

c

b

- 1036 -

-48-

--

42

10

20

-13-

V

= 300 V, ID = 6.2 A,

DD

R

= 9.1 , RD = 47

g

see fig. 10

b

G

TJ = 25 °C, IS = 6.2 A, VGS = 0 V

D

S

b

-23-

--6.2

--25

--1.5V

- 431 647 ns

b

-1.82.8μC

Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)

while VDS is rising fom 0 to 80 % VDS.

oss

V/°C

μA

pF

nC Gate-Source Charge Q

ns

A

www.vishay.com Document Number: 91113
2 S11-1053-Rev. C, 30-May-11

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

www.vishay.com/doc?91000

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

IRFBC40AS, SiHFBC40AS

Vishay Siliconix

Fig. 1 - Typical Output Characteristics

Fig. 2 - Typical Output Characteristics

Fig. 3 - Typical Transfer Characteristics

Fig. 4 - Normalized On-Resistance vs. Temperature

Document Number: 91113 www.vishay.com
S11-1053-Rev. C, 30-May-11 3

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

This document is subject to change without notice.

www.vishay.com/doc?91000

IRFBC40AS, SiHFBC40AS

Vishay Siliconix

Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage

Fig. 7 - Typical Source-Drain Diode Forward Voltage

Fig. 8 - Maximum Safe Operating Area

www.vishay.com Document Number: 91113
4 S11-1053-Rev. C, 30-May-11

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

This document is subject to change without notice.

www.vishay.com/doc?91000

V

DS

90 %

10 %

V

GS

t

d(on)

t

r

t

d(off)

t

f

A

R

g

I

AS

0.01 Ω

t

p

D.U.T

L

V

DS

+

-

V

DD

Driver

15 V

20 V

I

AS

V

DS

t

p

IRFBC40AS, SiHFBC40AS

Vishay Siliconix

R

D.U.T.

D

+

V

-

DD

V

DS

V

GS

R

g

10 V

Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %

Fig. 10a - Switching Time Test Circuit

Fig. 9 - Maximum Drain Current vs. Case Temperature

Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig. 10b - Switching Time Waveforms

Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms

Document Number: 91113 www.vishay.com
S11-1053-Rev. C, 30-May-11 5

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

This document is subject to change without notice.

www.vishay.com/doc?91000

IRFBC40AS, SiHFBC40AS

D.U.T.

3 mA

V

GS

V

DS

I

G

I

D

0.3 µF

0.2 µF

50 kΩ

12 V

Current regulator

Current sampling resistors

Same type as D.U.T.

+

-

Vishay Siliconix

Fig. 12c - Maximum Avalanche Energy vs. Drain Current

Q

10 V

V

Q

GS

G

G

Q

GD

Charge

Fig. 13a - Basic Gate Charge Waveform

Fig. 12d - Maximum Avalanche Energy vs. Drain Current

Fig. 13b - Gate Charge Test Circuit

www.vishay.com Document Number: 91113
6 S11-1053-Rev. C, 30-May-11

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

www.vishay.com/doc?91000

P.W.

Period

dI/dt

Diode recovery

dV/dt

Ripple ≤ 5 %

Body diode forward drop

Re-applied
voltage

Reverse
recovery
current

Body diode forward

current

V

GS

= 10 Va

I

SD

Driver gate drive

D.U.T. l

SD

waveform

D.U.T. V

DS

waveform

Inductor current

D =

P.W.

Period

+

-

+

+

+

-

-

-

Peak Diode Recovery dV/dt Test Circuit

V

DD

• dV/dt controlled by R

g

• Driver same type as D.U.T.

•

I

SD

controlled by duty factor “D”

• D.U.T. - device under test

D.U.T.

Circuit layout considerations

• Low stray inductance

• Ground plane

• Low leakage inductance

current transformer

R

g

Note

a. V

GS

= 5 V for logic level devices

V

DD

IRFBC40AS, SiHFBC40AS

Vishay Siliconix

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91113

Document Number: 91113 www.vishay.com
S11-1053-Rev. C, 30-May-11 7

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

.

This document is subject to change without notice.

Fig. 14 - For N-Channel

www.vishay.com/doc?91000

TO-263AB (HIGH VOLTAGE)

(Datum A)

34

E

L1

4

D

L2

4

C

1

B

B

C

3

2

B

B

Package Information

Vishay Siliconix

A

A

5

H

Detail A

B

A

c2

Gauge
plane

0° to 8°

L

L3

L4

Detail “A”
Rotated 90° CW
scale 8:1

H

B

Seating plane

A1

2 x e

Lead tip

2 x b2

2 x b

0.010 A B

MM

Plating

(c)

Section B - B and C - C

c

± 0.004 B

5

b1, b3

(b, b2)

Scale: none

M

Base
metal

c1

A

E

D1

4

5

E1

View A - A

4

MILLIMETERS INCHES MILLIMETERS INCHES

DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX.

A 4.06 4.83 0.160 0.190 D1 6.86 - 0.270 -

A1 0.00 0.25 0.000 0.010 E 9.65 10.67 0.380 0.420

b 0.51 0.99 0.020 0.039 E1 6.22 - 0.245 -

b1 0.51 0.89 0.020 0.035 e 2.54 BSC 0.100 BSC

b2 1.14 1.78 0.045 0.070 H 14.61 15.88 0.575 0.625

b3 1.14 1.73 0.045 0.068 L 1.78 2.79 0.070 0.110

c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.066

c1 0.38 0.58 0.015 0.023 L2 - 1.78 - 0.070

c2 1.14 1.65 0.045 0.065 L3 0.25 BSC 0.010 BSC

D 8.38 9.65 0.330 0.380 L4 4.78 5.28 0.188 0.208

ECN: S-82110-Rev. A, 15-Sep-08
DWG: 5970

Notes

1. Dimensioning and tolerancing per ASME Y14.5M-1994.

2. Dimensions are shown in millimeters (inches).

3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the
outmost extremes of the plastic body at datum A.

4. Thermal PAD contour optional within dimension E, L1, D1 and E1.

5. Dimension b1 and c1 apply to base metal only.

6. Datum A and B to be determined at datum plane H.

7. Outline conforms to JEDEC outline to TO-263AB.

Document Number: 91364 www.vishay.com
Revision: 15-Sep-08 1

RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead

0.420

(10.668)

0.635
(16.129)

0.355

AN826

Vishay Siliconix

(9.017)

Return to Index

0.135

(3.429)

0.200

(5.080)

Recommended Minimum Pads

Dimensions in Inches/(mm)

0.050

(1.257)

0.145

(3.683)

Document Number: 73397
11-Apr-05

www.vishay.com

1

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Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the
definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment
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Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.

Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free
requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21
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Revision: 02-Oct-12

1

Document Number: 91000