Datasheet IRFB20N50K, SiHFB20N50K DataSheet (Vishay)

IRFB20N50K, SiHFB20N50K

Power MOSFET

Vishay Siliconix

PRODUCT SUMMARY

VDS (V) 500

(Ω)V

R

DS(on)

Q

(Max.) (nC) 110

g

(nC) 33

Q

gs

Q

(nC) 54

gd

Configuration Single

TO-220

= 10 V 0.21

GS

D

FEATURES

• Low Gate Charge Qg Results in Simple Drive
Requirement

• Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness

• Fully Characterized Capacitance and Avalanche Voltage
and Current

•Low R

• Compliant to RoHS Directive 2002/95/EC

APPLICATIONS

• Switch Mode Power Supply (SMPS)

G

S

D

G

N-Channel MOSFET

S

• Uninterruptible Power Supply

• High Speed Power Switching

• Hard Switched and High Frequency Circuits

ORDERING INFORMATION

Package TO-220

Lead (Pb)-free

SnPb

IRFB20N50KPbF
SiHFB20N50K-E3
IRFB20N50K
SiHFB20N50K

Available

RoHS*

COMPLIANT

DS(on)

ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted

PARAMETER SYMBOL LIMIT UNIT

Drain-Source Voltage V

Gate-Source Voltage V

= 25 °C

T

Continuous Drain Current V

Pulsed Drain Current

a

at 10 V

GS

C

= 100 °C 12

C

DS

± 30

GS

I

D

IDM 80

Linear Derating Factor 2.2 W/°C

Single Pulse Avalanche Energy

Repetitive Avalanche Current

Repetitive Avalanche Energy

Maximum Power Dissipation T

Peak Diode Recovery dV/dt

b

a

a

= 25 °C P

C

c

Operating Junction and Storage Temperature Range T

E

AS

I

AR

E

AR

D

dV/dt 10 V/ns

, T

J

stg

Soldering Recommendations (Peak Temperature) for 10 s 300

Mounting Torque 6-32 or M3 screw 10 N

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature.
b. Starting T
c. I

SD

= 25 °C, L = 1.6 mH, Rg = 25 Ω, IAS = 20 A.

J

≤ 20 A, dI/dt ≤ 350 A/µs, VDD ≤ VDS, TJ ≤ 150 °C.

d. 1.6 mm from case.

* Pb containing terminations are not RoHS compliant, exemptions may apply

Document Number: 91101 www.vishay.com
S09-2236-Rev. D, 05-Apr-10 1

500

20

330 mJ

20 A

28 mJ

280 W

- 55 to + 150

d

V

AT

°C

IRFB20N50K, SiHFB20N50K

Vishay Siliconix

THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL TYP. MAX. UNIT

Maximum Junction-to-Ambient R

Maximum Junction-to-Case (Drain) R

thJA

thCS

thJC

SPECIFICATIONS TJ = 25 °C, unless otherwise noted

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

Static

Drain-Source Breakdown Voltage V

V

Temperature Coefficient ΔVDS/TJ Reference to 25 °C, ID = 1 mA - 0.61 - V/°C

DS

Gate-Source Threshold Voltage V

Gate-Source Leakage I

Zero Gate Voltage Drain Current I

Drain-Source On-State Resistance R

Forward Transconductance g

Dynamic

Input Capacitance C

Output Capacitance C

Reverse Transfer Capacitance C

Output Capacitance C

Effective Output Capacitance C

Total Gate Charge Q

Gate-Drain Charge Q

Turn-On Delay Time t

Rise Time t

Turn-Off Delay Time t

Fall Time t

Drain-Source Body Diode Characteristics

Continuous Source-Drain Diode Current I

Pulsed Diode Forward Current

a

Body Diode Voltage V

Body Diode Reverse Recovery Time t

Body Diode Reverse Recovery Charge Q

Forward Turn-On Time t

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature.
b. Pulse width ≤ 400 µs; duty cycle ≤ 2 %.

DS

GS(th)

V

GSS

DSS

VGS = 10 V ID = 12 A

DS(on)

fs

iss

- 320 -

oss

-34-

rss

oss

eff. VDS = 0 V to 400 V - 160 -

oss

g

--33

gs

--54

gd

d(on)

r

-45-

d(off)

-33-

f

S

I

SM

SD

rr

rr

on

V

V

GS

V

GS

Rg = 7.5 Ω, VGS = 10 V, see fig. 10

MOSFET symbol
showing the
integral reverse

p - n junction diode

TJ = 25 °C, IF = 20 A, dI/dt = 100 A/µs

-58

0.50 -

°C/WCase-to-Sink, Flat, Greased Surface R

-0.45

VGS = 0 V, ID = 250 µA 500 - - V

VDS = VGS, ID = 250 µA 3.0 - 5.0 V

= ± 30 V - - ± 100 nA

GS

VDS = 500 V, VGS = 0 V - - 50

= 400 V, VGS = 0 V, TJ = 125 °C - - 250

DS

b

- 0.21 0.25 Ω

VDS = 50 V, ID = 12 A 11 - - S

VGS = 0 V,

= 25 V,

V

DS

- 2870 -

f = 1.0 MHz, see fig. 5

V

= 1.0 V, f = 1.0 MHz - 3480 -

DS

= 0 V

= 400 V, f = 1.0 MHz - 85 -

V

DS

- - 110

= 20 A, VDS = 400 V

I

= 10 V

D

see fig. 6 and 13

b

-22-

V

= 250 V, ID = 20 A

DD

G

TJ = 25 °C, IS = 20 A, VGS = 0 V

b

D

S

b

-74-

--20

--80

--1.5V

- 520 780 ns

b

-5.38.0µC

Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)

µA

pF

nC Gate-Source Charge Q

ns

A

www.vishay.com Document Number: 91101
2 S09-2236-Rev. D, 05-Apr-10

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

100

10

rent (A)

VGS
15 V

Top

12 V
10 V

8.0 V

7.0 V

6.0 V

5.5 V

Bottom 5.0 V

IRFB20N50K, SiHFB20N50K

Vishay Siliconix

100.0

TJ= 150 °C

10.0

1

0.1

Drain-to-Source Cur
,

D

I

5.0V

20 µs Pulse Width
TJ = 25 °C

0.01

0.1 1 10 100

VDS, Drain-to-Source Voltage (V)

Fig. 1 - Typical Output Characteristics

100

10

rent (A)

1

VGS
15 V

Top

12 V
10 V

8.0 V

7.0 V

6.0 V

5.5 V

Bottom 5.0 V

5.0V

0.1

Drain-to-Source Cur
,

D

I

20 µs Pulse Width
TJ = 25 °C

0.01

0.1 1 10 100

VDS, Drain-to-Source Voltage (V)

Fig. 2 - Typical Output Characteristics

1.0

Drain-to-Source Current (A)

0.1

,

D

I

TJ= 25 °C

VDS= 50 V

0.0

5.0 6.0 7.0 8.0 9.0 10.0

20 ms Pulse width

V ,GS Gate-to-Source Voltage (V)

Fig. 3 - Typical Transfer Characteristics

3.5

3.0

2.5

2.0

1.5

1.0

, Drain-to-Source On-Resistance

DS(on)

(normalised)

r

0.5

0.0

20 A

I =

D

V

GS

- 60 - 40 - 20 0 20 40 60 80 100 120 140 160

TJ, Junction Temperature (°C)

Fig. 4 - Normalized On-Resistance vs. Temperature

= 10 V

Document Number: 91101 www.vishay.com
S09-2236-Rev. D, 05-Apr-10 3

IRFB20N50K, SiHFB20N50K

Vishay Siliconix

100000

10000

1000

C, Capacitance (pF)

100

10

1 10 100 1000

V

= 0 V, f = 1 MHz

GS

C

= Cgs + Cgd, C

iss

shorted
C

= C

rss

gd

C

= Cds + C

oss

C

iss

C

oss

C

rss

ds

gd

VDS, Drain-to-Source Voltage (V)

Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

20

? ?????

VDS = 400 V

= 250 V

V

16

V

DS
DS

= 100 V

100.0

TJ = 150 °C

10.0

1.0

, Reverse Drain Current (A)

SD

I

0.1

TJ = 25 °C

V

GS

= 0 V

0.2 0.4 0.6 0.8 1.0 1.2

V

, Source-to Drain Voltage (V)

SD

Fig. 7 - Typical Source-Drain Diode Forward Voltage

1000

Operation in this area limited
by r

DS(on)

100

12

8

, Gate-to-Source Voltage (V)

GS

V

4

For test circuit

0

0 20 40 60 80 100 120

QG, Total Gate Charge (nC)

see figure 13

Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage

10

100 µs

1 ms

1

, Drain-to-Source Current (A)

D

TC = 25 °C

I

0.1

TJ = 150 °C
Single Pulse

10 ms

1 10 100 1000 10000

V

, Drain-to-Source Voltage (V)

DS

Fig. 8 - Maximum Safe Operating Area

www.vishay.com Document Number: 91101
4 S09-2236-Rev. D, 05-Apr-10

A

IRFB20N50K, SiHFB20N50K

Vishay Siliconix

R

D.U.T.

D

+

V

DD

-

20

16

V

DS

V

GS

R

g

12

8

, Drain Current (A)

D

I

4

0

25 50 75 100 125 150

Fig. 9 - Maximum Drain Current vs. Case Temperature

1

D = 0.50

)

0.20

0.1

thJC

0.10

0.01

0.02

0.01

0.01

Thermal Response ( Z

0.001

0.00001 0.0001 0.001 0.01 0.1 1

Single Pulse

(Thermal Response)

t1, Rectangular Pulse Duration (s)

10 V

Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %

Fig. 10a - Switching Time Test Circuit

V

DS

90 %

10 %

V

GS

t

d(on)

t

r

t

d(off)

t

f

Fig. 10b - Switching Time Waveforms

P

DM

t

1

t

2

Notes:

1. Duty Factor D = t1/t

2. Peak TJ = PDM x T

2

thJC

+ T

C

Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case

V

DS

15 V

V

DS

R

g

20 V

L

D.U.T.

I

AS

0.01

t

p

Ω

Driver

+

V

A

DD

-

A

I

AS

t

p

Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms

Document Number: 91101 www.vishay.com
S09-2236-Rev. D, 05-Apr-10 5

IRFB20N50K, SiHFB20N50K

Vishay Siliconix

600

500

400

300

200

, Single Pulse Avalanche Energy (mJ)

100

AS

E

0

Fig. 12c - Maximum Avalanche Energy vs. Drain Current

Q

V

GS

Q

GS

V

G

G

Q

GD

Charge

Fig. 13a - Basic Gate Charge Waveform

I

D

Top

Bottom

25 50 75 100 125 150

9.4 A
17 A
20A

Current regulator

Same type as D.U.T.

0.2 µF

12 V

V

GS

Fig. 13b - Gate Charge Test Circuit

50 kΩ

0.3 µF

D.U.T.

3 mA

I

G

Current sampling resistors

I

D

+

V

DS

-

www.vishay.com Document Number: 91101
6 S09-2236-Rev. D, 05-Apr-10

IRFB20N50K, SiHFB20N50K

Peak Diode Recovery dV/dt Test Circuit

Vishay Siliconix

D.U.T.

+

-

R

g

Driver gate drive

P.W.

+

Circuit layout considerations

• Low stray inductance

• Ground plane

• Low leakage inductance

current transformer

-

• dV/dt controlled by R

• Driver same type as D.U.T.

• I

controlled by duty factor "D"

SD

• D.U.T. - device under test

Period

-

D =

g

P. W.

Period

+

+

V

DD

-

= 10 V*

V

GS

waveform

SD

Body diode forward

current

waveform

DS

Body diode forward drop

Ripple ≤ 5 %

= 5 V for logic level devices

GS

Diode recovery

dV/dt

dI/dt

V

DD

I

SD

Reverse
recovery
current

Re-applied
voltage

D.U.T. I

D.U.T. V

Inductor current

* V

Fig. 14 - For N-Channel

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon

Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and

reliability data, see www.vishay.com/ppg?91101

.

Document Number: 91101 www.vishay.com
S09-2236-Rev. D, 05-Apr-10 7

www.vishay.com

M

*

3

2

1

L

L(1)

D

H(1)

Q

Ø P

A

F

J(1)

b(1)

e(1)

e

E

b

C

Package Information

Vishay Siliconix

TO-220-1

DIM.

A 4.24 4.65 0.167 0.183

b 0.69 1.02 0.027 0.040

b(1) 1.14 1.78 0.045 0.070

c 0.36 0.61 0.014 0.024

D 14.33 15.85 0.564 0.624

E 9.96 10.52 0.392 0.414

e 2.41 2.67 0.095 0.105

e(1) 4.88 5.28 0.192 0.208

F 1.14 1.40 0.045 0.055

H(1) 6.10 6.71 0.240 0.264

J(1) 2.41 2.92 0.095 0.115

L 13.36 14.40 0.526 0.567

L(1) 3.33 4.04 0.131 0.159

Ø P 3.53 3.94 0.139 0.155

Q 2.54 3.00 0.100 0.118

ECN: X15-0364-Rev. C, 14-Dec-15
DWG: 6031

Note

• M* = 0.052 inches to 0.064 inches (dimension including
protrusion), heatsink hole for HVM

MILLIMETERS INCHES

MIN. MAX. MIN. MAX.

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Revison: 14-Dec-15

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ASE Xi’an

For technical questions, contact: [e-mail]

Package Picture

1

Document Number: 66542

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Revision: 13-Jun-16

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Document Number: 91000