Datasheet IRF9Z14S, SiHF9Z14S, IRF9Z14L, SiHF9Z14L DataSheet (Vishay)

S

G

D

P-Channel MOSFET

D2PAK (TO-263)

G

D

S

I2PAK (TO-262)

G

D

S

IRF9Z14S, SiHF9Z14S, IRF9Z14L, SiHF9Z14L

Vishay Siliconix

Power MOSFET

PRODUCT SUMMARY

VDS (V) - 60

()V

R

DS(on)

Q

(Max.) (nC) 12

g

Q

(nC) 3.8

gs

Q

(nC) 5.1

gd

Configuration Single

= - 10 V 0.50

GS

FEATURES

• Halogen-free According to IEC 61249-2-21
Definition

• Advanced Process Technology

• Surface Mount (IRF9Z14S, SiHF9Z14S)

•

Low-Profile Through-Hole (IRF9Z14L, SiHF9Z14L)

• 175 °C Operating Temperature

•Fast Switching

• P-Channel

• Fully Avalanche Rated

• Compliant to RoHS Directive 2002/95/EC

DESCRIPTION

Third generation Power MOSFETs from Vishay utilize
advanced processing techniques to achieve extremely low
on-resistance per silicon area. This benefit, combined with
the fast switching speed and ruggedized device design that
Power MOSFETs are well known for, provides the designer
with an extremely efficient and reliable device for use in a
wide variety of applications.

2

The D

PAK is a surface mount power package capable of
accommodating die size up to HEX-4. It provides the
highest power capability and the lowest possible
on-resistance in any existing surface mount package. The

2

D

PAK is suitable for high current applications because of is

low internal connection resistance and can dissipate up to

2.0 W in a typical surface mount application.
The through-hole version (IRF9Z14L, SiHF9Z14L) is
available for low-profile applications.

ORDERING INFORMATION

Package D2PAK (TO-263) D2PAK (TO-263) I2PAK (TO-262)
Lead (Pb)-free and Halogen-free SiHF9Z14S-GE3 SiHF9Z14STRL-GE3

Lead (Pb)-free

Note

a. See device orientation.

IRF9Z14SPbF IRF9Z14STRLPbF
SiHF9Z14S-E3 SiHF9Z14STL-E3

a

SiHF9Z14L-GE3

a

IRF9Z14LPbF

a

SiHF9Z14L-E3

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT

Drain-Source Voltage V
Gate-Source Voltage V

T

= 25 °C

Continuous Drain Current

Pulsed Drain Current

a, e

e

VGS at - 10 V

C

= 100 °C - 4.7

T

C

DS

± 20

GS

I

D

IDM - 27

Linear Derating Factor 0.29 W/°C

c, e

b, e

a

= 25 °C

T

C

= 25 °C 3.7

T

A

Single Pulse Avalanche Energy
Avalanche Current

a

Repetiitive Avalanche Energy

Maximum Power Dissipation

Peak Diode Recovery dV/dt
Operating Junction and Storage Temperature Range T

E

AS

I

AR

E

AR

P

D

dV/dt - 4.5 V/ns

, T

J

stg

Soldering Recommendations (Peak Temperature) for 10 s 300

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. V

= - 25 V, starting TJ = 25 °C, L = 3.6 mH, Rg = 25 , IAS = - 6.7 A (see fig. 12).

DD

c. ISD  - 6.7 A, dI/dt  90 A/μs, VDD  VDS, TJ  175 °C.
d. 1.6 mm from case.
e. Uses IRF9Z14, SiHF9Z14 data and test conditions.

- 60

- 6.7

140 mJ

- 6.7 A

4.3 mJ
43

- 55 to + 175

d

V

A

W

°C

* Pb containing terminations are not RoHS compliant, exemptions may apply

Document Number: 91089
S11-1052-Rev. C, 30-May-11 1

www.vishay.com

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

www.vishay.com/doc?91000

IRF9Z14S, SiHF9Z14S, IRF9Z14L, SiHF9Z14L

Vishay Siliconix

THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL TYP. MAX. UNIT

Maximum Junction-to-Ambient (PCB
Mounted, steady-state)

a

Maximum Junction-to-Case (Drain) R

Note

a. When mounted on 1" square PCB (FR-4 or G-10 material).

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

Static

Drain-Source Breakdown Voltage V

V

Temperature Coefficient VDS/TJ Reference to 25 °C, ID = - 1 mA

DS

Gate-Source Threshold Voltage V

Gate-Source Leakage I

Zero Gate Voltage Drain Current I

Drain-Source On-State Resistance R

Forward Transconductance g

Dynamic

Input Capacitance C

Reverse Transfer Capacitance C

Total Gate Charge Q

Gate-Drain Charge Q

Turn-On Delay Time t

Rise Time t

Turn-Off Delay Time t

Fall Time t

Internal Source Inductance L

Drain-Source Body Diode Characteristics

Continuous Source-Drain Diode Current I

Pulsed Diode Forward Current

Body Diode Voltage V

Drain-Source Body Diode Characteristics

Body Diode Reverse Recovery Time t

Body Diode Reverse Recovery Charge Q

Forward Turn-On Time t

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width  300 μs; duty cycle  2 %.
c. Uses IRF9Z14, SiHF9Z14 data and test conditions.

a

R

thJA

thJC

DS

GS(th)

V

GSS

-40
°C/W

-3.5

VGS = 0, ID = - 250 μA - 60 - - V

c

- - 0.06 - V/°C

VDS = VGS, ID = - 250 μA - 2.0 - - 4.0 V

= ± 20 V - - ± 100 nA

GS

VDS = - 60 V, VGS = 0 V - - - 100

DSS

VGS = - 10 V ID = - 4.0 A

DS(on)

fs

iss

- 170 -

oss

-31-

rss

g

--3.8

gs

--5.1

gd

d(on)

r

-10-

d(off)

-31-

f

S

S

I

SM

SD

rr

rr

on

V

= - 48 V, VGS = 0 V, TJ = 150 °C - - - 500

DS

VDS = - 25 V, ID = - 4.0 A

VGS = 0 V,

V

= - 25 V,

DS

f = 1.0 MHz, see fig. 5

b

c

c

--0.5

1.4 - - S

- 270 -

--12

= - 6.7 A, VDS = - 48 V,

I

V

GS

= - 10 V

D

see fig. 6 and 13

b, c

-11-

= - 30 V, ID = - 6.7 A,

V

DD

R

= 24 , RD = 4.0 , see fig. 10

g

b

-63-

Between lead, and center of die contact - 7.5 - nH

MOSFET symbol
showing the
integral reverse
p - n junction diode

TJ = 25 °C, IS = - 6.7 A, VGS = 0 V

TJ = 25 °C, IF = - 6.7 A, dI/dt = 100 A/μs

D

G

S

b

--- 6.7

--- 27

--- 5.5V

- 80 160 ns

b, c

- 96 190 nC

Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)

μA

pFOutput Capacitance C

nC Gate-Source Charge Q

ns

A

www.vishay.com Document Number: 91089
2 S11-1052-Rev. C, 30-May-11

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

www.vishay.com/doc?91000

91089_01

20 µs Pulse Width
T

C

= 25 °C

- 4.5 V

- VDS, Drain-to-Source Voltage (V)

- I

D

, Drain Current (A)

10

0

10

1

10

1

10

0

10

-1

Bottom

To p

V

GS

- 15 V

- 10 V

- 8.0 V

- 7.0 V

- 6.0 V

- 5.5 V

- 5.0 V

- 4.5 V

10

-1

10

1

10

0

10

-1

10

0

10

1

- V

DS

,

Drain-to-Source Voltage (V)

- I

D

, Drain Current (A)

Bottom

To p

V

GS

- 15 V

- 10 V

- 8.0 V

- 7.0 V

- 6.0 V

- 5.5 V

- 5.0 V

- 4.5 V

20 µs Pulse Width
T

C

= 175 °C

91089_02

- 4.5 V

10

-1

20 µs Pulse Width
V

DS

= - 25 V

10

1

10

0

10

-1

- I

D

, Drain Current (A)

- V

GS

,

Gate-to-Source Voltage (V)

56 78 910

4

25 °C

175 °C

91089_03

I

D

= - 6.7 A

V

GS

= - 10 V

3.0

0.0

0.5

1.0

1.5

2.0

2.5

T

J

,

Junction Temperature (°C)

R

DS(on)

, Drain-to-Source On Resistance

(Normalized)

91089_04

- 60 - 40- 20 0 20 40 6080100 120140 160

180

IRF9Z14S, SiHF9Z14S, IRF9Z14L, SiHF9Z14L

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

Vishay Siliconix

Fig. 1 - Typical Output Characteristics

Fig. 2 - Typical Output Characteristics

Fig. 3 - Typical Transfer Characteristics

Fig. 4 - Normalized On-Resistance vs. Temperature

Document Number: 91089 www.vishay.com
S11-1052-Rev. C, 30-May-11 3

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

This document is subject to change without notice.

www.vishay.com/doc?91000

600

480

360

0

120

240

10

0

10

1

Capacitance (pF)

- V

DS

,

Drain-to-Source Voltage (V)

C

iss

C

rss

C

oss

V

GS

= 0 V, f = 1 MHz

C

iss

= Cgs + Cgd, Cds Shorted

C

rss

= C

gd

C

oss

= Cds + C

gd

91089_05

QG, Total Gate Charge (nC)

- V

GS

, Gate-to-Source Voltage (V)

20

16

12

8

0

4

0

3

15

129

6

V

DS

= - 30 V

For test circuit
see figure 13

V

DS

= - 48 V

91089_06

ID = - 6.7 A

10 µs

100 µs

1 ms

10 ms

Operation in this area limited

by R

DS(on)

- VDS, Drain-to-Source Voltage (V)

- I

D

, Drain Current (A)

TC = 25 °C
T

J

= 175 °C

Single Pulse

10

2

2

5

1

2

5

10

2

1

5

10 10

2

25

91089_08

IRF9Z14S, SiHF9Z14S, IRF9Z14L, SiHF9Z14L

Vishay Siliconix

1

10

Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

175 °C

25 °C

0

10

, Reverse Drain Current (A)

SD

- I

91089_07

-1

10

1.0

4.03.02.0

- VSD, Source-to-Drain Voltage (V)

V

5.0

Fig. 7 - Typical Source-Drain Diode Forward Voltage

= 0 V

GS

6.0

Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage

Fig. 8 - Maximum Safe Operating Area

www.vishay.com Document Number: 91089
4 S11-1052-Rev. C, 30-May-11

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

This document is subject to change without notice.

www.vishay.com/doc?91000

- I

D

, Drain Current (A)

TC, Case Temperature (°C)

0.0

1.5

3.0

4.5

6.0

7.5

91089_09

15025 1251007550

175

V

GS

10 %

90 %

V

DS

t

d(on)

t

r

t

d(off)

t

f

R

g

I

AS

0.01 Ω

t

p

D.U.T.

L

V

DS

+

­V

DD

- 10 V

Var y tp to obtain
required I

AS

I

AS

V

DS

V

DD

V

DS

t

p

IRF9Z14S, SiHF9Z14S, IRF9Z14L, SiHF9Z14L

Vishay Siliconix

R

D.U.T.

D

-

+

V

DD

V

DS

V

GS

R

g

- 10 V

Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %

Fig. 10a - Switching Time Test Circuit

Fig. 9 - Maximum Drain Current vs. Case Temperature

10

)

thJC

0.1

1

D = 0.5

0.2

0.1

0.05

0.02

0.01

Single Pulse
(Thermal Response)

Thermal Response (Z

-2

10

91089_11

-5

10

-4

10

-3

10

t1, Rectangular Pulse Duration (s)

Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig. 10b - Switching Time Waveforms

P

DM

t

1

t

1/t2

thJC

2

+ T

C

Notes:

1. Duty Factor, D = t

2. Peak Tj = PDM x Z

-2

10

0.1 1 10

Document Number: 91089 www.vishay.com
S11-1052-Rev. C, 30-May-11 5

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms

This document is subject to change without notice.

www.vishay.com/doc?91000

Q

GS

Q

GD

Q

G

V

G

Charge

- 10 V

D.U.T.

- 3 mA

V

GS

V

DS

I

G

I

D

0.3 µF

0.2 µF

50 kΩ

12 V

Current regulator

Current sampling resistors

Same type as D.U.T.

+

-

IRF9Z14S, SiHF9Z14S, IRF9Z14L, SiHF9Z14L

Vishay Siliconix

500

400

300

200

, Single Pulse Energy (mJ)

100

AS

E

91089_12c

VDD = - 25 V

0

25 150

50

Starting TJ, Junction Temperature (°C)

To p

Bottom

125

10075

I

D

- 2.7 A

- 4.7 A

- 6.7 A

175

Fig. 12c - Maximum Avalanche Energy vs. Drain Current

Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit

www.vishay.com Document Number: 91089
6 S11-1052-Rev. C, 30-May-11

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

www.vishay.com/doc?91000

IRF9Z14S, SiHF9Z14S, IRF9Z14L, SiHF9Z14L

Vishay Siliconix

Peak Diode Recovery dV/dt Test Circuit

D.U.T.

+

-

R

g

Note

• Compliment N-Channel of D.U.T. for driver

Driver gate drive

P.W.

+

-

Period

Circuit layout considerations

• Low stray inductance

• Ground plane

• Low leakage inductance

• dV/dt controlled by R

• I

controlled by duty factor “D”

SD

• D.U.T. - device under test

current transformer

-

g

D =

Period

P.W.

+

V

GS

+

V

-

= - 10 V

DD

a

D.U.T. lSD waveform

Reverse
recovery
current

Re-applied
voltage

D.U.T. V

Inductor current

Note

a. V

waveform

DS

= - 5 V for logic level and - 3 V drive devices

GS

Body diode forward

current

Body diode forward drop

Ripple ≤ 5 %

dI/dt

Diode recovery

dV/dt

V

DD

I

SD

Fig. 14 - For P-Channel

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91089

.

Document Number: 91089 www.vishay.com
S11-1052-Rev. C, 30-May-11 7

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

www.vishay.com/doc?91000

TO-263AB (HIGH VOLTAGE)

(Datum A)

34

E

L1

4

D

L2

4

C

1

B

B

C

3

2

B

B

Package Information

Vishay Siliconix

A

A

5

H

Detail A

B

A

c2

Gauge
plane

0° to 8°

L

L3

L4

Detail “A”
Rotated 90° CW
scale 8:1

H

B

Seating plane

A1

2 x e

Lead tip

2 x b2

2 x b

0.010 A B

MM

Plating

(c)

Section B - B and C - C

c

± 0.004 B

5

b1, b3

(b, b2)

Scale: none

M

Base
metal

c1

A

E

D1

4

5

E1

View A - A

4

MILLIMETERS INCHES MILLIMETERS INCHES

DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX.

A 4.06 4.83 0.160 0.190 D1 6.86 - 0.270 -

A1 0.00 0.25 0.000 0.010 E 9.65 10.67 0.380 0.420

b 0.51 0.99 0.020 0.039 E1 6.22 - 0.245 -

b1 0.51 0.89 0.020 0.035 e 2.54 BSC 0.100 BSC

b2 1.14 1.78 0.045 0.070 H 14.61 15.88 0.575 0.625

b3 1.14 1.73 0.045 0.068 L 1.78 2.79 0.070 0.110

c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.066

c1 0.38 0.58 0.015 0.023 L2 - 1.78 - 0.070

c2 1.14 1.65 0.045 0.065 L3 0.25 BSC 0.010 BSC

D 8.38 9.65 0.330 0.380 L4 4.78 5.28 0.188 0.208

ECN: S-82110-Rev. A, 15-Sep-08
DWG: 5970

Notes

1. Dimensioning and tolerancing per ASME Y14.5M-1994.

2. Dimensions are shown in millimeters (inches).

3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the
outmost extremes of the plastic body at datum A.

4. Thermal PAD contour optional within dimension E, L1, D1 and E1.

5. Dimension b1 and c1 apply to base metal only.

6. Datum A and B to be determined at datum plane H.

7. Outline conforms to JEDEC outline to TO-263AB.

Document Number: 91364 www.vishay.com
Revision: 15-Sep-08 1

I2PAK (TO-262) (HIGH VOLTAGE)

(Datum A)

E

L1

Package Information

Vishay Siliconix

A

A

B

c2

A

E

D

L2

0.010 A B

Lead tip

B

2 x e

M

Seating

plane

C

C

B

M

3 x b2

3 x b

L

A1

A

E1

Section A - A

Plating

c

b1, b3

(b, b2)

Section B - B and C - C

Scale: None

c

D1

Base
metal

c1

MILLIMETERS INCHES MILLIMETERS INCHES

DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX.

A 4.06 4.83 0.160 0.190 D 8.38 9.65 0.330 0.380

A1 2.03 3.02 0.080 0.119 D1 6.86 - 0.270 -

b 0.51 0.99 0.020 0.039 E 9.65 10.67 0.380 0.420

b1 0.51 0.89 0.020 0.035 E1 6.22 - 0.245 -

b2 1.14 1.78 0.045 0.070 e 2.54 BSC 0.100 BSC

b3 1.14 1.73 0.045 0.068 L 13.46 14.10 0.530 0.555

c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.065

c1 0.38 0.58 0.015 0.023 L2 3.56 3.71 0.140 0.146

c2 1.14 1.65 0.045 0.065

ECN: S-82442-Rev. A, 27-Oct-08
DWG: 5977

Notes

1. Dimensioning and tolerancing per ASME Y14.5M-1994.

2. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm per side. These dimensions are measured at the outmost
extremes of the plastic body.

3. Thermal pad contour optional within dimension E, L1, D1, and E1.

4. Dimension b1 and c1 apply to base metal only.

Document Number: 91367 www.vishay.com
Revision: 27-Oct-08 1

RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead

0.420

(10.668)

0.635
(16.129)

0.355

AN826

Vishay Siliconix

(9.017)

Return to Index

0.135

(3.429)

0.200

(5.080)

Recommended Minimum Pads

Dimensions in Inches/(mm)

0.050

(1.257)

0.145

(3.683)

Document Number: 73397
11-Apr-05

www.vishay.com

1

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

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“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
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Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over
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including but not limited to the warranty expressed therein.

Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
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Revision: 13-Jun-16

1

Document Number: 91000