Datasheet IRF9610S, SiHF9610S DataSheet (Vishay)

www.vishay.com

S

G

D

P-Channel MOSFET

IRF9610S, SiHF9610S

Vishay Siliconix

Power MOSFET

PRODUCT SUMMARY

VDS (V) - 200

R

()V

DS(on)

Q

(Max.) (nC) 11

g

(nC) 7

Q

gs

Q

(nC) 4

gd

Configuration Single

= - 10 V 3

GS

FEATURES

• Surface Mount

• Available in Tape and Reel

• Dynamic dV/dt Rating

•P-Channel

• Fast Switching

• Ease of Paralleling

• Simple Drive Requirements

• Material categorization: For definitions of
compliance please see www.vishay.com/doc?99912

Note

* Lead (Pb)-containing terminations are not RoHS-compliant.

D2PAK (TO-263)

Exemptions may apply.

DESCRIPTION

Third generation Power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.

2

The D

D

G

S

PAK (TO-263) is a surface mount power package
capable of accommodating die sizes up to HEX-4. It
provides the highest power capability and the lowest
possible on-resistance in any existing surface mount
package. The D
applications because of its low internal connection
resistance and can dissipate up to 2 W in a typical surface
mount application.

ORDERING INFORMATION

Package D2PAK (TO-263)

SiHF9610S-GE3

Lead (Pb)-free and Halogen-free

Lead (Pb)-free

SiHF9610STRR-GE3

SiHF9610STRL-GE3

IRF9610SPbF

SiHF9610S-E3

IRF9610STRRPbF

IRF9610STRLPbF

2

PAK (TO-263) is suitable for high current

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT

Drain-Source Voltage V

Gate-Source Voltage V

T

= 25 °C

Continuous Drain Current V

Pulsed Drain Current

Linear Derating Factor 0.16

Linear Derating Factor (PCB Mount)

Maximum Power Dissipation T

Maximum Power Dissipation (PCB Mount)

Peak Diode Recovery dV/dt

Operating Junction and Storage Temperature Range T

Soldering Recommendations (Peak Temperature) for 10 s 300

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 5).
b. I

 - 1.8 A, dI/dt  70 A/μs, VDD  VDS, TJ  150 °C.

SD

c. 1.6 mm from case.
d. When mounted on 1" square PCB (FR-4 or G-10 material).

S12-1558-Rev. D, 02-Jul-12

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

a

d

d

b

For technical questions, contact: [e-mail]

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

at - 10 V

GS

TA = 25 °C 3

C

= 100 °C - 1

C

= 25 °C

C

1

DS

± 20

GS

I

D

IDM - 7

P

D

dV/dt - 5 V/ns

, T

J

stg

- 200

- 1.8

0.025

20

- 55 to + 150

c

Document Number: 91081

V

AT

W/°C

W

°C

D

S

G

S

D

G

IRF9610S, SiHF9610S

www.vishay.com

THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL TYP. MAX. UNIT

Maximum Junction-to-Ambient R

Maximum Junction-to-Ambient
(PCB Mount)

a

Maximum Junction-to-Case (Drain) R

thJA

R

thJA

thJC

-62

-40

-6.4

Note

a. When mounted on 1" square PCB (FR-4 or G-10 material).

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

Static

Drain-Source Breakdown Voltage V

V

Temperature Coefficient VDS/TJ Reference to 25 °C, ID = - 1 mA - - 0.23 - V/°C

DS

Gate-Source Threshold Voltage V

Gate-Source Leakage I

Zero Gate Voltage Drain Current I

Drain-Source On-State Resistance R

Forward Transconductance g

DS

GS(th)

V

GSS

DSS

VGS = - 10 V ID = - 0.90 A

DS(on)

fs

Dynamic

Input Capacitance C

Reverse Transfer Capacitance C

Total Gate Charge Q

Gate-Drain Charge Q

Turn-On Delay Time t

Rise Time t

Turn-Off Delay Time t

Fall Time t

Internal Drain Inductance L

iss

-50-

oss

-15-

rss

g

--7

gs

--4

gd

d(on)

r

d(off)

-8-

f

D

V

-1-

Between lead,
6 mm (0.25") from
package and center of

Internal Source Inductance L

S

die contact

Drain-Source Body Diode Characteristics

Continuous Source-Drain Diode Current I

Pulsed Diode Forward Current

a

Body Diode Voltage V

Body Diode Reverse Recovery Time t

Body Diode Reverse Recovery Charge Q

Forward Turn-On Time t

S

I

SM

SD

rr

rr

on

MOSFET symbol
showing the
integral reverse
p - n junction diode

TJ = 25 °C, IF = - 1.8 A, dI/dt = 100 A/μs

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 5).
b. Pulse width  300 μs; duty cycle  2 %.

VGS = 0, ID = - 250 μA - 200 - - V

VDS = VGS, ID = - 250 μA - 2 - - 4 V

= ± 20 V - - ± 100 nA

GS

VDS = - 200 V, VGS = 0 V - - - 100

V

= - 160 V, VGS = 0 V, TJ = 125 °C - - - 500

DS

b

VDS = - 50 V, ID = - 0.90 A

b

VGS = 0 V,

V

= - 25 V,

DS

f = 1 MHz, see fig. 10

= - 3.5 A, VDS = - 160 V,

I

= - 10 V

GS

V

R

= 50 , RD = 110 , see fig. 17

G

TJ = 25 °C, IS = - 1.8 A, VGS = 0 V

D

see fig. 11 and 18

= - 100 V, ID = - 0.90 A,

DD

b

b

b

b

Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)

Vishay Siliconix

°C/W

--3

0.90 - - S

- 170 -

--11

-8-

-15-

-4.5-

-7.5-

--- 1.8

--- 7

--- 5.8V

- 240 360 ns

-1.72.6μC

μA

pFOutput Capacitance C

nC Gate-Source Charge Q

ns

nH

A

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

For technical questions, contact: [e-mail]

S12-1558-Rev. D, 02-Jul-12

2

Document Number: 91081

91081_01

VDS, Drain-to-Source Voltage (V)

I

D

, Drain Current (A)

- 10

- 2.40

- 4 V

- 6 V

- 5 V

V

GS

= - 10, - 9, - 8, - 7 V

- 1.92

- 1.44

- 0.96

- 0.48

0.00
0

- 20

- 30 - 40

- 50

80 µs Pulse Test

V

GS

,

Gate-to-Source Voltage (V)

I

D

, Drain Current (A)

80 µs Pulse Test
V

DS

> I

D(on)

x R

DS(on)

max.

91081_02

- 2

- 2.40

- 1.92

- 1.44

- 0.96

- 0.48

0.00
0 - 4 - 6 - 8 - 10

T

J

= - 55 °C

T

J

= 25 °C

T

J

= 125 °C

80 µs Pulse Test

I

D

, Drain Current (A)

V

DS

,

Drain-to-Source Voltage (V)

91081_03

- 4 V

- 6 V

- 5 V

V

GS

= - 10, - 9, - 8 V

- 7 V

- 2

- 2.40

- 1.92

- 1.44

- 0.96

- 0.48

0.00
0 - 4 - 6 - 8 - 10

100 µs

1 ms

10 ms

Operation in this area limited

by R

DS(on)

Negative VDS, Drain-to-Source Voltage (V)

Negative I

D

, Drain Current (A)

TC = 25 °C
T

J

= 150 °C

Single Pulse

10

2

2

5

0.1

1

2

5

10

2

5

25

110

25

10

2

10

3

25

91081_04

2.0

1.0

0.1

10

-5

10

-4

10

-3

10

-2

0.1 1.0 10

P

DM

t

1

t

2

t1, Square Wave Pulse Duration (s)

Z

thJC

(t)/R

thJC

, Normalized Effective Transie

Notes:

1. Duty Factor, D = t

1/t2

2. Per Unit Base = R

thJC

= 6.4 °C/W

3. T

JM

- TC = PDM Z

thJC

(t)

0.2

0.05

0.02

0.01

91081_05

0.1

D = 0.5

0.5

0.2

0.05

0.02

0.01

25 25 25 25 25 25

Thermal Impedence (Per Unit)

Single Pulse (Transient
Thermal Impedence)

www.vishay.com

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

IRF9610S, SiHF9610S

Vishay Siliconix

Fig. 1 - Typical Output Characteristics

Fig. 2 - Typical Transfer Characteristics

Fig. 3 - Typical Saturation Characteristics

Fig. 4 - Maximum Safe Operating Area

Fig. 5 - Maximum Effective Transient Thermal Impedance, Junction-to.Case vs. Pulse Duration

S12-1558-Rev. D, 02-Jul-12

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

For technical questions, contact: [e-mail]

3

Document Number: 91081

www.vishay.com

2.0

g

fs

,Transconductance (S)

I

D

,

Drain Current (A)

- 0.48 - 0.96 - 1.44 - 1.92 - 2.40

0

TJ = 25 °C

TJ = - 55 °C

91081_06

TJ = 125 °C

80 µs Pulse Test
V

DS

> I

D(on)

x R

DS(on)

max.

1.6

1.2

0.8

0.4

0.0

TJ = 25 °C

TJ = 150 °C

- 10.0

VSD, Source-to-Drain Voltage (V)

I

D

, Drain Current (A)

- 2.0

- 6.8

- 5.6- 4.4- 3.2

91081_07

- 0.1

- 0.2

- 0.5

- 1.0

- 2.0

- 5.0

- 8.0

91081_08

TJ, Junction Temperature (°C)

BV

DSS

, Drain-to-Source Breakdown

1.25

Voltage (Normalized)

1.15

0.75

0.85

0.95

1.05

- 40

160

120

80400

91081_09

TJ, Junction Temperature (°C)

R

DS(on)

, Drain-to-Source On Resistance

2.5

(Normalized)

2.0

0.0

0.5

1.0

1.5

- 40

160

12080400

I

D

= - 0.6 A

V

GS

= - 10 V

91081_10

VDS, Drain-to-Source Voltage (V)

C, Capacitance (pF)

500

0

100

200

300

400

0 - 50- 40- 30- 20

- 10

C

iss

C

rss

C

oss

V

GS

= 0 V, f = 1 MHz

C

iss

= Cgs + Cgd, Cds Shorted

C

rss

= C

gd

C

oss

= Cds +

C

gs

, C

gd

Cgs + C

gd

≈ Cgs + C

gd

IRF9610S, SiHF9610S

Vishay Siliconix

Fig. 6 - Typical Transconductance vs. Drain Current

Fig. 7 - Typical Source-Drain Diode Forward Voltage

Fig. 9 - Normalized On-Resistance vs. Temperature

Fig. 10 - Typical Capacitance vs. Drain-to-Source Voltage

20

ID = - 1.8 A

V

= - 100 V

16

V

= - 40 V

12

DS

V

DS

DS

= - 60 V

S12-1558-Rev. D, 02-Jul-12

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

Fig. 8 - Breakdown Voltage vs. Temperature

For technical questions, contact: [e-mail]

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

8

, Gate-to-Source Voltage (V)

GS

4

For test circuit
see figure 18

Negative V

91081_11

0

02864

QG, Total Gate Charge (nC)

Fig. 11 - Typical Gate Charge vs. Gate-to-Source Voltage

4

Document Number: 91081

7

150

Negative I

D

, Drain Current (A)

TC, Case Temperature (°C)

0.0

0.4

0.8

1.2

1.6

2.0

25

91081_13

1251007550

TC, Case Temperature (°C)

P

D

, Power Dissipation (W)

20

15

10

0

5

0 20 100806040

91081_14

140

120

0.05 Ω

D.U.T.

L

V

DS

+

-

V

DD

VGS = - 10 V

Var y tp to obtain
required I

L

t

p

VDD = 0.5 V

DS

EC = 0.75 V

DS

E

C

I

L

V

DD

V

DS

t

p

E

C

I

L

6

5

4

3

, Drain-to-Source

2

On Resistance (Ω)

DS(on)

R

1

0

91081_12

www.vishay.com

R

measured with current pulse of

DS(on)

2.0 µs duration. Initial T

(Heating effect of 2.0 µs pulse is minimal.)

- 1

0

- 2 - 3 - 4

ID, Drain Current (A)

= 25 °C.

J

V

GS

= - 10 V

V

- 5

GS

= - 20 V

- 6

IRF9610S, SiHF9610S

Vishay Siliconix

- 7

Fig. 12 - Typical On-Resistance vs. Drain Current

Fig. 13 - Maximum Drain Current vs. Case Temperature

Fig. 14 - Power vs. Temperature Derating Curve

Fig. 15 - Clamped Inductive Test Circuit

Fig. 16 - Clamped Inductive Waveforms

S12-1558-Rev. D, 02-Jul-12

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

5

For technical questions, contact: [e-mail]

Document Number: 91081

www.vishay.com

Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %

R

D

V

GS

R

g

D.U.T.

- 10 V

+

-

V

DS

V

DD

V

GS

10 %

90 %

V

DS

t

d(on)

t

r

t

d(off)

t

f

IRF9610S, SiHF9610S

Vishay Siliconix

Q

- 10 V

G

Fig. 17a - Switching Time Test Circuit

Fig. 17b - Switching Time Waveforms

Q

GS

V

G

Q

GD

Charge

Fig. 18a - Basic Gate Charge Waveform

Current regulator

Same type as D.U.T.

50 kΩ

0.2 µF

12 V

0.3 µF

-

V

+

D.U.T.

V

GS

- 3 mA

I

G

Current sampling resistors

I

DS

D

Fig. 18b - Gate Charge Test Circuit

S12-1558-Rev. D, 02-Jul-12

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

6

Document Number: 91081

For technical questions, contact: [e-mail]

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

www.vishay.com

P.W.

Period

dI/dt

Diode recovery

dV/dt

Body diode forward drop

Body diode forward

current

Driver gate drive

Inductor current

D =

P.W.

Period

+

-

-

-

-

+

+

+

Peak Diode Recovery dV/dt Test Circuit

• dV/dt controlled by R

g

• D.U.T. - device under test

D.U.T.

Circuit layout considerations

• Low stray inductance

• Ground plane

• Low leakage inductance

current transformer

R

g

• Compliment N-Channel of D.U.T. for driver

V

DD

• I

SD

controlled by duty factor “D”

Note

Note

a. V

GS

= - 5 V for logic level and - 3 V drive devices

V

GS

= - 10 V

a

D.U.T. lSD waveform

D.U.T. V

DS

waveform

V

DD

Re-applied
voltage

Ripple ≤ 5 %

I

SD

Reverse
recovery
current

IRF9610S, SiHF9610S

Vishay Siliconix

Fig. 19 - For P-Channel

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91081

S12-1558-Rev. D, 02-Jul-12

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

.

7

For technical questions, contact: [e-mail]

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Document Number: 91081

TO-263AB (HIGH VOLTAGE)

(Datum A)

34

E

L1

4

D

L2

4

C

1

B

B

C

3

2

B

B

Package Information

Vishay Siliconix

A

A

5

H

Detail A

B

A

c2

Gauge
plane

0° to 8°

L

L3

L4

Detail “A”
Rotated 90° CW
scale 8:1

H

B

Seating plane

A1

2 x e

Lead tip

2 x b2

2 x b

0.010 A B

MM

Plating

(c)

Section B - B and C - C

c

± 0.004 B

5

b1, b3

(b, b2)

Scale: none

M

Base
metal

c1

A

E

D1

4

5

E1

View A - A

4

MILLIMETERS INCHES MILLIMETERS INCHES

DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX.

A 4.06 4.83 0.160 0.190 D1 6.86 - 0.270 -

A1 0.00 0.25 0.000 0.010 E 9.65 10.67 0.380 0.420

b 0.51 0.99 0.020 0.039 E1 6.22 - 0.245 -

b1 0.51 0.89 0.020 0.035 e 2.54 BSC 0.100 BSC

b2 1.14 1.78 0.045 0.070 H 14.61 15.88 0.575 0.625

b3 1.14 1.73 0.045 0.068 L 1.78 2.79 0.070 0.110

c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.066

c1 0.38 0.58 0.015 0.023 L2 - 1.78 - 0.070

c2 1.14 1.65 0.045 0.065 L3 0.25 BSC 0.010 BSC

D 8.38 9.65 0.330 0.380 L4 4.78 5.28 0.188 0.208

ECN: S-82110-Rev. A, 15-Sep-08
DWG: 5970

Notes

1. Dimensioning and tolerancing per ASME Y14.5M-1994.

2. Dimensions are shown in millimeters (inches).

3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the
outmost extremes of the plastic body at datum A.

4. Thermal PAD contour optional within dimension E, L1, D1 and E1.

5. Dimension b1 and c1 apply to base metal only.

6. Datum A and B to be determined at datum plane H.

7. Outline conforms to JEDEC outline to TO-263AB.

Document Number: 91364 www.vishay.com
Revision: 15-Sep-08 1

RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead

0.420

(10.668)

0.635
(16.129)

0.355

AN826

Vishay Siliconix

(9.017)

Return to Index

0.135

(3.429)

0.200

(5.080)

Recommended Minimum Pads

Dimensions in Inches/(mm)

0.050

(1.257)

0.145

(3.683)

Document Number: 73397
11-Apr-05

www.vishay.com

1

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Disclaimer

ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.

Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
disclosure relating to any product.

Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all
liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,
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Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical
requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements
about the suitability of products for a particular application. It is the customer’s responsibility to validate that a particular
product with the properties described in the product specification is suitable for use in a particular application. Parameters
provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All
operating parameters, including typical parameters, must be validated for each customer application by the customer’s
technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase,
including but not limited to the warranty expressed therein.

Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
applications or for any other application in which the failure of the Vishay product could result in personal injury or death.
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contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by
any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.

Material Category Policy

Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the
definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment
(EEE) - recast, unless otherwise specified as non-compliant.

Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.

Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free
requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21
conform to JEDEC JS709A standards.

Revision: 02-Oct-12

1

Document Number: 91000