Datasheet IRF840AS, SiHF840AS, IRF840AL, SiHF840AL DataSheet (Vishay)

N-Channel MOSFET

G

D

S

D2PAK (TO-263)

G

D

S

I2PAK (TO-262)

G

D

S

IRF840AS, SiHF840AS, IRF840AL, SiHF840AL

Vishay Siliconix

Power MOSFET

PRODUCT SUMMARY

VDS (V) 500

R

()V

DS(on)

Q

(Max.) (nC) 38

g

Q

(nC) 9.0

gs

Q

(nC) 18

gd

Configuration Single

= 10 V 0.85

GS

FEATURES

• Halogen-free According to IEC 61249-2-21
Definition

• Low Gate Charge Q
Requirement

• Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness

• Fully Characterized Capacitance and
Avalanche Voltage and Current

• Effective C

Specified

oss

Results in Simple Drive

g

• Compliant to RoHS Directive 2002/95/EC

APPLICATIONS

• Switch Mode Power Supply (SMPS)

• Uninterruptible Power Supply

• High Speed Power Switching

TYPICAL SMPS TOPOLOGIES

• Two Transistor Forward

•Half Bridge

• Full Bridge

ORDERING INFORMATION

Package D2PAK (TO-263) D2PAK (TO-263) D2PAK (TO-263) I2PAK (TO-262)

Lead (Pb)-free and Halogen-free SiHF840AS-GE3 SiHF840ASTRL-GE3

Lead (Pb)-free

IRF840ASPbF IRF840ASTRLPbF

SiHF840AS-E3 SiHF840ASTL-E3

a

SiHF840ASTRR-GE3aSiHF840AL-GE3

a

IRF840ASTRRPbF

a

SiHF840ASTR-E3

a

a

IRF840ALPbF

SiHF840AL-E3

Note

a. See device orientation.

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT

Drain-Source Voltage V

Gate-Source Voltage V

= 25 °C

T

Continuous Drain Current V

Pulsed Drain Current

a

at 10 V

GS

C

= 100 °C 5.1

C

DS

± 30

GS

I

D

IDM 32

Linear Derating Factor 1.0 W/°C

c, e

b

a

a

T

= 25 °C

C

T

= 25 °C 3.1

A

E

AS

I

AR

E

AR

P

D

dV/dt 5.0 V/ns

, T

J

stg

Single Pulse Avalanche Energy

Repetitive Avalanche Current

Repetitive Avalanche Energy

Maximum Power Dissipation

Peak Diode Recovery dV/dt

Operating Junction and Storage Temperature Range T

Soldering Temperature for 10 s 300

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Starting T
c. I

SD

d. 1.6 mm from case.
e. Uses IRF840A, SiH840A data and test conditions.

= 25 °C, L = 16 mH, Rg = 25 , IAS = 8.0 A (see fig. 12).

J

 8.0 A, dI/dt  100 A/μs, VDD  VDS, TJ  150 °C.

500

8.0

510 mJ

8.0 A

13 mJ

125

- 55 to + 150

d

a

V

AT

W

°C

* Pb containing terminations are not RoHS compliant, exemptions may apply

Document Number: 91066
S11-1050-Rev. D, 30-May-11 1

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This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

www.vishay.com/doc?91000

S

D

G

IRF840AS, SiHF840AS, IRF840AL, SiHF840AL

Vishay Siliconix

THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

Maximum Junction-to-Ambient
(PCB Mount)

a

Maximum Junction-to-Case (Drain) R

Note

a. When mounted on 1" square PCB (FR-4 or G-10 material).

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

Static

Drain-Source Breakdown Voltage V

V

Temperature Coefficient VDS/TJ Reference to 25 °C, ID = 1 mAd -0.58-V/°C

DS

Gate-Source Threshold Voltage V

Gate-Source Leakage I

Zero Gate Voltage Drain Current I

Drain-Source On-State Resistance R

Forward Transconductance g

Dynamic

Input Capacitance C

Output Capacitance C

Reverse Transfer Capacitance C

Output Capacitance C

Output Capacitance C

Effective Output Capacitance C

Total Gate Charge Q

Gate-Drain Charge Q

Turn-On Delay Time t

Rise Time t

Turn-Off Delay Time t

Fall Time t

Drain-Source Body Diode Characteristics

Continuous Source-Drain Diode Current I

Pulsed Diode Forward Current

Body Diode Voltage V

Body Diode Reverse Recovery Time t

Body Diode Reverse Recovery Charge Q

Forward Turn-On Time t

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width  300 μs; duty cycle  2 %.
c. C

eff. is a fixed capacitance that gives the same charging time as C

oss

d. Uses IRF840A, SiHF840A data and test conditions

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2 S11-1050-Rev. D, 30-May-11

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

a

R

thJA

thJC

DS

GS(th)

V

GSS

--40

--1.0

VGS = 0, ID = 250 μA 500 - - V

VDS = VGS, ID = 250 μA 2.0 - 4.0 V

= ± 30 V - - ± 100 nA

GS

VDS = 500 V, VGS = 0 V - - 25

DSS

VGS = 10 V ID = 4.8 A

DS(on)

fs

iss

- 155 -

oss

-8.0-

rss

oss

V

oss

eff. VDS = 0 V to 480 V

oss

g

--9.0

gs

--18

gd

d(on)

r

-26-

d(off)

-19-

f

S

I

SM

SD

rr

rr

on

V

= 400 V, VGS = 0 V, TJ = 125 °C - - 250

DS

b

- - 0.85 

VDS = 50 V, ID = 4.8 A 3.7 - - S

- 1018 -

56

f = 1.0 MHz, see fig. 5

V

= 0 V

GS

VGS = 0 V,

V

= 25 V,

DS

= 1.0 V, f = 1.0 MHz 1490

V

DS

= 400 V, f = 1.0 MHz 42

DS

c, d

--38

= 8.0 A, VDS = 400 V,

I

V

GS

= 10 V

D

see fig. 6 and 13

b, d

-11-

V

= 250 V, ID = 8.0 A,

DD

R

= 9.1 , RD = 31 , see fig. 10

g

b, d

MOSFET symbol
showing the
integral reverse
p - n junction diode

TJ = 25 °C, IS = 8.0 A, VGS = 0 V

b

TJ = 25 °C, IF = 8.0 A, dI/dt = 100 A/μs

-23-

--8.0

--32

--2.0V

- 422 633 ns

b

-2.03.0μC

Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)

while VDS is rising from 0 %to 80 % VDS.

oss

This document is subject to change without notice.

www.vishay.com/doc?91000

°C/W

μA

pF

nC Gate-Source Charge Q

ns

A

10

2

10

1

91066_01

Bottom

To p

V

GS

15 V
10 V

8.0 V

7.0 V

6.0 V

5.5 V

5.0 V

4.5 V

20 µs Pulse Width
T

J

= 25 °C

4.5 V

VDS, Drain-to-Source Voltage (V)

I

D

, Drain-to-Source Current (A)

10

2

10

1

0.1

0.1

10

2

10

1

0.1

10

2

10

1

0.1

91066_02

Bottom

To p

V

GS

15 V
10 V

8.0 V

7.0 V

6.0 V

5.5 V

5.0 V

4.5 V

20 µs Pulse Width
T

J

= 150 °C

4.5 V

VDS, Drain-to-Source Voltage (V)

I

D

, Drain-to-Source Current (A)

10

2

10

1

0.1

91066_03

TJ = 25 °C

20 µs Pulse Width
V

DS

= 50 V

I

D

, Drain-to-Source Current (A)

V

GS

,

Gate-to-Source Voltage (V)

4.0 5.0

6.0 7.0 8.0 9.0

TJ = 150 °C

IRF840AS, SiHF840AS, IRF840AL, SiHF840AL

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

Vishay Siliconix

Fig. 1 - Typical Output Characteristics

Fig. 2 - Typical Output Characteristics

Fig. 3 - Typical Transfer Characteristics

3.0
I

= 8.0 A

D

= 10 V

V

GS

2.5

2.0

1.5

(Normalized)

1.0

0.5

, Drain-to-Source On Resistance

DS(on)

0.0

R

91066_04

- 60 - 40 - 20 0 20

T

Junction Temperature (°C)

,

J

80 100 120 140 160

40 60

Fig. 4 - Normalized On-Resistance vs. Temperature

Document Number: 91066 www.vishay.com
S11-1050-Rev. D, 30-May-11 3

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

This document is subject to change without notice.

www.vishay.com/doc?91000

1

1

10

2

10

3

10

2

91066_05

C, Capacitance (pF)

V

DS

,

Drain-to-Source Voltage (V)

C

iss

C

rss

C

oss

V

GS

= 0 V, f = 1 MHz

C

iss

= Cgs + Cgd, Cds Shorted

C

rss

= C

gd

C

oss

= Cds + C

gd

10

10

10

5

10

4

10

3

91066_06

QG, Total Gate Charge (nC)

V

GS

, Gate-to-Source Voltage (V)

20

16

12

8

0

4

0

10

40

30

20

ID = 8.0 A

V

DS

= 100 V

V

DS

= 250 V

For test circuit
see figure 13

V

DS

= 400 V

91066_07

V

GS

= 0 V

VSD, Source-to-Drain Voltage (V)

I

SD

, Reverse Drain Current (A)

10

2

10

1

0.1

0.2

0.5 0.8

1.4

1.1

TJ = 25 °C

TJ = 150 °C

10

2

91066_08

10 µs

100 µs

1 ms

10 ms

Operation in this area limited

by R

DS(on)

TC = 25 °C
T

J

= 150 °C

Single Pulse

VDS, Drain-to-Source Voltage (V)

I

D

, Drain Current (A)

10

1

0.1
10

4

10

10

3

10

2

IRF840AS, SiHF840AS, IRF840AL, SiHF840AL

Vishay Siliconix

Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage

Fig. 7 - Typical Source-Drain Diode Forward Voltage

Fig. 8 - Maximum Safe Operating Area

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www.vishay.com/doc?91000

8.0

V

DS

90 %

10 %

V

GS

t

d(on)

t

r

t

d(off)

t

f

0.1 1

91066_11

Thermal Response (Z

thJC

)

t1, Rectangular Pulse Duration (s)

10

1

0.1

10

-2

10

-4

10

-3

10

-2

D = 0.50

0.20

0.10

0.05

0.02

0.01

P

DM

t

1

t

2

Notes:

1. Duty Factor, D = t

1/t2

2. Peak Tj = PDM x Z

thJC

+ T

C

Single Pulse
(Thermal Response)

10

-5

A

R

g

I

AS

0.01 Ω

t

p

D.U.T.

L

V

DS

+

-

V

DD

Driver

15 V

20 V

I

AS

V

DS

t

p

6.0

4.0

IRF840AS, SiHF840AS, IRF840AL, SiHF840AL

Vishay Siliconix

R

D.U.T.

D

+

V

-

DD

V

DS

V

GS

R

g

10 V

Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %

, Drain Current (A)

D

2.0

I

0.0
25 1501251007550

91066_09

TC, Case Temperature (°C)

Fig. 9 - Maximum Drain Current vs. Case Temperature

Fig. 10a - Switching Time Test Circuit

Fig. 10b - Switching Time Waveforms

Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms

Document Number: 91066 www.vishay.com
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91066_12c

1000

0

200

400

600

800

25 150

125

10075

50

Starting T

J

, Junction Temperature (°C)

E

AS

, Single Pulse Avalanche Energy (mJ)

1200

Bottom

To p

I

D

3.6 A

5.1 A

8.0 A

600

570

580

590

0.0 5.04.03.02.01.0

IAV, Avalanche Current (A)

V

DSav

, Avalanche Voltage (V)

610

6.0

91066_12d

540

550

560

Q

GS

Q

GD

Q

G

V

G

Charge

10 V

D.U.T.

3 mA

V

GS

V

DS

I

G

I

D

0.3 µF

0.2 µF

50 kΩ

12 V

Current regulator

Current sampling resistors

Same type as D.U.T.

+

-

IRF840AS, SiHF840AS, IRF840AL, SiHF840AL

Vishay Siliconix

Fig. 13a - Basic Gate Charge Waveform

Fig. 12c - Maximum Avalanche Energy vs. Drain Current

Fig. 12d - Typical Drain-to-Source Voltage vs.

Avalanche Current

Fig. 13b - Gate Charge Test Circuit

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THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

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IRF840AS, SiHF840AS, IRF840AL, SiHF840AL

Vishay Siliconix

Peak Diode Recovery dV/dt Test Circuit

D.U.T.

+

-

R

g

Driver gate drive

P.W.

+

-

Period

Circuit layout considerations

• Low stray inductance

• Ground plane

• Low leakage inductance

current transformer

• dV/dt controlled by R

• Driver same type as D.U.T.

I

controlled by duty factor “D”

•

SD

• D.U.T. - device under test

-

D =

g

Period

P.W.

+

+

V

DD

-

= 10 Va

V

GS

D.U.T. l

Reverse
recovery
current

D.U.T. V

Re-applied
voltage

Inductor current

Note

a. V

waveform

SD

Body diode forward

waveform

DS

Body diode forward drop

Ripple ≤ 5 %

= 5 V for logic level devices

GS

current

dI/dt

Diode recovery

dV/dt

V

DD

I

SD

Fig. 14 - For N-Channel

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91066

.

Document Number: 91066 www.vishay.com
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TO-263AB (HIGH VOLTAGE)

(Datum A)

34

E

L1

4

D

L2

4

C

1

B

B

C

3

2

B

B

Package Information

Vishay Siliconix

A

A

5

H

Detail A

B

A

c2

Gauge
plane

0° to 8°

L

L3

L4

Detail “A”
Rotated 90° CW
scale 8:1

H

B

Seating plane

A1

2 x e

Lead tip

2 x b2

2 x b

0.010 A B

MM

Plating

(c)

Section B - B and C - C

c

± 0.004 B

5

b1, b3

(b, b2)

Scale: none

M

Base
metal

c1

A

E

D1

4

5

E1

View A - A

4

MILLIMETERS INCHES MILLIMETERS INCHES

DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX.

A 4.06 4.83 0.160 0.190 D1 6.86 - 0.270 -

A1 0.00 0.25 0.000 0.010 E 9.65 10.67 0.380 0.420

b 0.51 0.99 0.020 0.039 E1 6.22 - 0.245 -

b1 0.51 0.89 0.020 0.035 e 2.54 BSC 0.100 BSC

b2 1.14 1.78 0.045 0.070 H 14.61 15.88 0.575 0.625

b3 1.14 1.73 0.045 0.068 L 1.78 2.79 0.070 0.110

c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.066

c1 0.38 0.58 0.015 0.023 L2 - 1.78 - 0.070

c2 1.14 1.65 0.045 0.065 L3 0.25 BSC 0.010 BSC

D 8.38 9.65 0.330 0.380 L4 4.78 5.28 0.188 0.208

ECN: S-82110-Rev. A, 15-Sep-08
DWG: 5970

Notes

1. Dimensioning and tolerancing per ASME Y14.5M-1994.

2. Dimensions are shown in millimeters (inches).

3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the
outmost extremes of the plastic body at datum A.

4. Thermal PAD contour optional within dimension E, L1, D1 and E1.

5. Dimension b1 and c1 apply to base metal only.

6. Datum A and B to be determined at datum plane H.

7. Outline conforms to JEDEC outline to TO-263AB.

Document Number: 91364 www.vishay.com
Revision: 15-Sep-08 1

I2PAK (TO-262) (HIGH VOLTAGE)

(Datum A)

E

L1

Package Information

Vishay Siliconix

A

A

B

c2

A

E

D

L2

0.010 A B

Lead tip

B

2 x e

M

Seating

plane

C

C

B

M

3 x b2

3 x b

L

A1

A

E1

Section A - A

Plating

c

b1, b3

(b, b2)

Section B - B and C - C

Scale: None

c

D1

Base
metal

c1

MILLIMETERS INCHES MILLIMETERS INCHES

DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX.

A 4.06 4.83 0.160 0.190 D 8.38 9.65 0.330 0.380

A1 2.03 3.02 0.080 0.119 D1 6.86 - 0.270 -

b 0.51 0.99 0.020 0.039 E 9.65 10.67 0.380 0.420

b1 0.51 0.89 0.020 0.035 E1 6.22 - 0.245 -

b2 1.14 1.78 0.045 0.070 e 2.54 BSC 0.100 BSC

b3 1.14 1.73 0.045 0.068 L 13.46 14.10 0.530 0.555

c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.065

c1 0.38 0.58 0.015 0.023 L2 3.56 3.71 0.140 0.146

c2 1.14 1.65 0.045 0.065

ECN: S-82442-Rev. A, 27-Oct-08
DWG: 5977

Notes

1. Dimensioning and tolerancing per ASME Y14.5M-1994.

2. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm per side. These dimensions are measured at the outmost
extremes of the plastic body.

3. Thermal pad contour optional within dimension E, L1, D1, and E1.

4. Dimension b1 and c1 apply to base metal only.

Document Number: 91367 www.vishay.com
Revision: 27-Oct-08 1

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

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Revision: 13-Jun-16

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Document Number: 91000