Datasheet IRF510S, SiHF510S DataSheet (Vishay)

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IRF510S, SiHF510S

Vishay Siliconix

Power MOSFET

PRODUCT SUMMARY

VDS (V) 100

R

()V

DS(on)

Q

max. (nC) 8.3

g

Q

(nC) 2.3

gs

Q

(nC) 3.8

gd

Configuration Single

D2PAK (TO-263)

D

G

S

= 10 V 0.54

GS

G

N-Channel MOSFET

FEATURES

• Surface mount

• Available in tape and reel

• Dynamic dV/dt rating

Available

• Repetitive avalanche rated

• 175 °C operating temperature

Available

• Fast switching

• Ease of paralleling

D

• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912

Note

*

Thi s datasheet pro vi des information about parts that are
RoHS-compliant and / or parts that are non-RoHS-compliant. For
example, parts with lead (Pb) terminations are not RoHS-compliant.
Please see the information / tables in this datasheet for details.





DESCRIPTION

Third generation power MOSFETs from Vishay provide the

S

designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
The D2PAK (TO-263) is a surface mount power package
capable of accommodating die sizes up to HEX-4. It
provides the highest power capability and the lowest
possible on-resistance in any existing surface mount
package. The D2PAK (TO-263) is suitable for high current
applications because of its low internal connection
resistance and can dissipate up to 2.0 W in a typical surface
mount application.

ORDERING INFORMATION

Package D2PAK (TO-263) D2PAK (TO-263) D2PAK (TO-263)
Lead (Pb)-free and Halogen-free SiHF510S-GE3 SiHF510STRL-GE3

Lead (Pb)-free

Note

a. See device orientation.

IRF510SPbF IRF510STRLPbF
SiHF510S-E3 SiHF510STL-E3

a

a

a

SiHF510STRR-GE3
IRF510STRRPbF
SiHF510STR-E3

a

a

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT

Drain-Source Voltage V
Gate-Source Voltage V

= 25 °C

T

Continuous Drain Current V

Pulsed Drain Current

a

at 10 V

GS

C

= 100 °C 4.0

C

DS

± 20

GS

I

D

IDM 20
Linear Derating Factor 0.29
Linear Derating Factor (PCB mount)
Single Pulse Avalanche Energy
Avalanche Current

a

Repetitive Avalanche Energy
Maximum Power Dissipation T
Maximum Power Dissipation (PCB mount)
Peak Diode Recovery dV/dt
Operating Junction and Storage Temperature Range T
Soldering Recommendations (Peak temperature)

e

b

a

= 25 °C

e

c

d

C

TA = 25 °C 3.7

for 10 s 300

E

AS

I

AR

E

AR

P

D

dV/dt 5.5 V/ns

, T

J

stg

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. V

= 25 V, starting TJ = 25 °C, L = 4.8 mH, Rg = 25 , IAS = 5.6 A (see fig. 12).

DD

 5.6 A, dI/dt  75 A/μs, VDD  VDS, TJ  175 °C.

c. I

SD

d. 1.6 mm from case.
e. When mounted on 1" square PCB (FR-4 or G-10 material).

S15-2693-Rev. D, 16-Nov-15

1

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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

100

5.6

0.025
75 mJ

5.6 A

4.3 mJ
43

-55 to +175

Document Number: 91016

a

V

AT

W/°C

W

°C

IRF510S, SiHF510S

D

S

G

S

D

G

www.vishay.com

THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL TYP. MAX. UNIT

Maximum Junction-to-Ambient R

Maximum Junction-to-Ambient 
(PCB mount)

a

Maximum Junction-to-Case (Drain) R

thJA

R

thJA

thJC

-62

-40

-3.5

Note

a. When mounted on 1" square PCB (FR-4 or G-10 material).

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

Static

Drain-Source Breakdown Voltage V

V

Temperature Coefficient VDS/TJ Reference to 25 °C, ID = 1 mA - 0.12 - V/°C

DS

Gate-Source Threshold Voltage V

Gate-Source Leakage I

Zero Gate Voltage Drain Current I

Drain-Source On-State Resistance R

Forward Transconductance g

DS

GS(th)

V

GSS

DSS

VGS = 10 V ID = 3.4 A

DS(on)

fs

Dynamic

Input Capacitance C

Reverse Transfer Capacitance C

Total Gate Charge Q

Gate-Drain Charge Q

Turn-On Delay Time t

Rise Time t

Turn-Off Delay Time t

Fall Time t

Internal Drain Inductance L

iss

-81-

oss

-15-

rss

g

--2.3

gs

--3.8

gd

d(on)

r

-15-

d(off)

-9.4-

f

D

V

Between lead,
6 mm (0.25") from
package and center of

Internal Source Inductance L

S

die contact

Drain-Source Body Diode Characteristics

Continuous Source-Drain Diode Current I

Pulsed Diode Forward Current

a

Body Diode Voltage V

Body Diode Reverse Recovery Time t

Body Diode Reverse Recovery Charge Q

Forward Turn-On Time t

S

I

SM

SD

rr

rr

on

MOSFET symbol
showing the 
integral reverse
p - n junction diode

TJ = 25 °C, IF = 5.6 A, dI/dt = 100 A/μs

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width  300 μs; duty cycle  2 %.

VGS = 0, ID = 250 μA 100 - - V

VDS = VGS, ID = 250 μA 2.0 - 4.0 V

= ± 20 V - - ± 100 nA

GS

VDS = 100 V, VGS = 0 V - - 25

= 80 V, VGS = 0 V, TJ = 150 °C - - 250

V

DS

VDS = 50 V, ID = 3.4 A

b

b

VGS = 0 V,

V

= 25 V,

DS

f = 1.0 MHz, see fig. 5

= 5.6 A, VDS = 80 V,

I

= 10 V

GS

V

R

= 24 , RD = 8.4 , see fig. 10

g

TJ = 25 °C, IS = 5.6 A, VGS = 0 V

D

see fig. 6 and fig. 13

= 50 V, ID = 5.6 A,

DD

b

b

b

b

Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)

Vishay Siliconix

°C/W

- - 0.54 

1.3 - - S

- 180 -

--8.3

-6.9-

-16-

-4.5-

-7.5-

--5.6

--20

--2.5V

- 100 200 ns

-0.440.88μC

μA

pFOutput Capacitance C

nC Gate-Source Charge Q

ns

nH

A

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

For technical questions, contact: [e-mail]

S15-2693-Rev. D, 16-Nov-15

2

Document Number: 91016

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10

1

10

0

10

-1

10

0

10

1

V

DS

,

Drain-to-Source Voltage (V)

I

D

, Drain Current (A)

4.5 V

Bottom

To p

V

GS

15 V
10 V

8.0 V

7.0 V

6.0 V

5.5 V

5.0 V

4.5 V

20 μs pulse width
T

C

= 175 °C

91016_02

20 μs pulse width
V

DS

= 50 V

10

1

10

0

10

-1

I

D

, Drain Current (A)

V

GS

,

Gate-to-Source Voltage (V)

56789104

25 °C

175 °C

91016_03

400

320

240

160

0

80

10

0

10

1

V

GS

= 0 V, f = 1 MHz

C

iss

= Cgs + Cgd, Cds shorted

C

rss

= C

gd

C

oss

= Cds + C

gd

C

iss

C

rss

C

oss

Capacitance (pF)

V

DS

,

Drain-to-Source Voltage (V)

91016_05

20

16

12

8

0

4

02 864

ID = 5.6 A

V

DS

= 20 V

For test circuit
see figure 13

10

V

DS

= 50 V

V

DS

= 80 V

QG, Total Gate Charge (nC)

V

GS

, Gate-to-Source Voltage (V)

91016_06

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

IRF510S, SiHF510S

Vishay Siliconix

V

GS

15 V
10 V

8.0 V

7.0 V

6.0 V

5.5 V

5.0 V

4.5 V

, Drain Current (A)

D

I

To p

1

10

Bottom

0

10

20 μs pulse width

= 25 °C

T

C

91016_01

-1

10

VDS, Drain-to-Source Voltage (V)

0

10

1

10

Fig. 1 - Typical Output Characteristics, TC = 25 °C

4.5 V

3.0
I

= 5.6 A

D

= 10 V

V

GS

2.5

2.0

1.5

(Normalized)

1.0

0.5

, Drain-to-Source On Resistance

DS(on)

0.0

R

-60 -40 -20 0 20 40 60 80 100 120 140 160

,

T

91016_04

Junction Temperature (°C)

J

Fig. 4 - Normalized On-Resistance vs. Temperature

180

Fig. 2 - Typical Output Characteristics, T

S15-2693-Rev. D, 16-Nov-15

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

Fig. 3 - Typical Transfer Characteristics

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

= 175 °C

C

Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage

3

For technical questions, contact: [e-mail]

Document Number: 91016

0

100 µs

1 ms

10 ms

Operation in this area limited

by R

DS(on)

VDS, Drain-to-Source Voltage (V)

I

D

, Drain Current (A)

TC = 25 °C
T

J

= 175 °C

single pulse

0.1

10

2

2

5

1

2

5

10

2

5

25

1

10

25

10

2

25

10

3

91016_08

I

D

, Drain Current (A)

TC, Case Temperature (°C)

1.0

2.0

3.0

4.0

5.0

6.0

25 1501251007550

0.0
175

91016_09

Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %

R

D

V

GS

R

g

D.U.T.

10 V

+

-

V

DS

V

DD

V

DS

90 %

10 %

V

GS

t

d(on)

t

r

t

d(off)

t

f

10

1

0.1

10

-2

10

-5

10

-4

10

-3

10

-2

0.1 1 10

P

DM

t

1

t

2

t1, Rectangular Pulse Duration (s)

Thermal Response (Z

thJC

)

Notes:

1. Duty factor, D = t

1/t2

2. Peak Tj = PDM x Z

thJC

+ T

C

Single pulse
(thermal response)

0 - 0.5

0.2

0.1

0.05

0.02

0.01

91016_11

10

, Reverse Drain Current (A)

-1

10

SD

I

0.5 0.90.80.70.6 1.0 1.21.1

91016_07

www.vishay.com

175 °C

25 °C

VSD, Source-to-Drain Voltage (V)

IRF510S, SiHF510S

Vishay Siliconix

V

= 0 V

GS

Fig. 7 - Typical Source-Drain Diode Forward Voltage

Fig. 8 - Maximum Safe Operating Area

Fig. 9 - Maximum Drain Current vs. Case Temperature

Fig. 10a - Switching Time Test Circuit

Fig. 10b - Switching Time Waveforms

S15-2693-Rev. D, 16-Nov-15

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case

For technical questions, contact: [e-mail]

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Document Number: 91016

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R

g

I

AS

0.01 Ω

t

p

D.U.T

L

V

DS

+

-

V

DD

10 V

Var y t

p

to obtain

required I

AS

300

0

50

100

150

200

250

25 1501251007550

Starting TJ, Junction Temperature (°C)

E

AS

, Single Pulse Energy (mJ)

Bottom

To p

I

D

2.3 A

4.0 A

5.6 A

VDD = 25 V

175

91016_12c

Q

GS

Q

GD

Q

G

V

G

Charge

V

GS

IRF510S, SiHF510S

Vishay Siliconix

Fig. 12a - Unclamped Inductive Test Circuit

V

DS

t

p

V

DS

I

AS

V

DD

Fig. 12b - Unclamped Inductive Waveforms

Fig. 13a - Basic Gate Charge Waveform

Current regulator

Same type as D.U.T.

50 kΩ

0.2 µF

12 V

V

GS

0.3 µF

D.U.T.

3 mA

I

G

Current sampling resistors

I

D

+

V

DS

-

Fig. 13b - Gate Charge Test Circuit

Fig. 12c - Maximum Avalanche Energy vs. Drain Current

S15-2693-Rev. D, 16-Nov-15

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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

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Document Number: 91016

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P.W.

Period

dI/dt

Diode recovery

dV/dt

Ripple ≤ 5 %

Body diode forward drop

Re-applied
voltage

Reverse
recovery
current

Body diode forward

current

V

GS

= 10 Va

I

SD

Driver gate drive

D.U.T. l

SD

waveform

D.U.T. V

DS

waveform

Inductor current

D =

P.W.

Period

+

-

+

+

+

-

-

-

Peak Diode Recovery dV/dt Test Circuit

V

DD

• dV/dt controlled by R

g

• Driver same type as D.U.T.

•

I

SD

controlled by duty factor “D”

• D.U.T. - device under test

D.U.T.

Circuit layout considerations

• Low stray inductance

• Ground plane

• Low leakage inductance

current transformer

R

g

Note

a. V

GS

= 5 V for logic level devices

V

DD

IRF510S, SiHF510S

Vishay Siliconix

Fig. 14 - For N-Channel

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91016

S15-2693-Rev. D, 16-Nov-15

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

.

6

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Document Number: 91016

TO-263AB (HIGH VOLTAGE)

(Datum A)

34

E

L1

4

D

L2

4

C

1

B

B

C

3

2

B

B

Package Information

Vishay Siliconix

A

A

5

H

Detail A

B

A

c2

Gauge
plane

0° to 8°

L

L3

L4

Detail “A”
Rotated 90° CW
scale 8:1

H

B

Seating plane

A1

2 x e

Lead tip

2 x b2

2 x b

0.010 A B

MM

Plating

(c)

Section B - B and C - C

c

± 0.004 B

5

b1, b3

(b, b2)

Scale: none

M

Base
metal

c1

A

E

D1

4

5

E1

View A - A

4

MILLIMETERS INCHES MILLIMETERS INCHES

DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX.

A 4.06 4.83 0.160 0.190 D1 6.86 - 0.270 -

A1 0.00 0.25 0.000 0.010 E 9.65 10.67 0.380 0.420

b 0.51 0.99 0.020 0.039 E1 6.22 - 0.245 -

b1 0.51 0.89 0.020 0.035 e 2.54 BSC 0.100 BSC

b2 1.14 1.78 0.045 0.070 H 14.61 15.88 0.575 0.625

b3 1.14 1.73 0.045 0.068 L 1.78 2.79 0.070 0.110

c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.066

c1 0.38 0.58 0.015 0.023 L2 - 1.78 - 0.070

c2 1.14 1.65 0.045 0.065 L3 0.25 BSC 0.010 BSC

D 8.38 9.65 0.330 0.380 L4 4.78 5.28 0.188 0.208

ECN: S-82110-Rev. A, 15-Sep-08
DWG: 5970

Notes

1. Dimensioning and tolerancing per ASME Y14.5M-1994.

2. Dimensions are shown in millimeters (inches).

3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the
outmost extremes of the plastic body at datum A.

4. Thermal PAD contour optional within dimension E, L1, D1 and E1.

5. Dimension b1 and c1 apply to base metal only.

6. Datum A and B to be determined at datum plane H.

7. Outline conforms to JEDEC outline to TO-263AB.

Document Number: 91364 www.vishay.com
Revision: 15-Sep-08 1

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

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RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.

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“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
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particular product with the properties described in the product specification is suitable for use in a particular application.
Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over
time. All operating parameters, including typical parameters, must be validated for each customer application by the customer’s
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including but not limited to the warranty expressed therein.

Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
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Revision: 13-Jun-16

1

Document Number: 91000