Datasheet si9410bdy Datasheet

Page 1
N-Channel 30-V (D-S) MOSFET
Si9410BDY
Vishay Siliconix
PRODUCT SUMMARY
VDS (V) R
30
DS(on)
0.024 at V
0.033 at V
GS
GS
(Ω)I
= 10 V
= 4.5 V
D
(A)
8.1
6.9
FEATURES
• TrenchFET
• Compliant to RoHS Directive 2002/95/EC
®
Power MOSFETs
D
SO-8
SD
1
SD
2
SD
3
GD
4
Top View
Ordering Information: Si9410BDY-T1-E3 (Lead (Pb)-free)
Si9410BDY-T1-GE3 (Lead (Pb)-free and Halogen-free)
8
7
6
5
G
S
N-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Parameter Symbol 10 s Steady State Unit
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current (T
= 150 °C)
J
a
Pulsed Drain Current (10 µs Pulse Width)
Continuous Source Current (Diode Conduction)
Maximum Power Dissipation
a
a
Operating Junction and Storage Temperature Range
TA = 25 °C
= 70 °C
T
A
TA = 25 °C
= 70 °C
T
A
V
DS
V
GS
I
D
I
DM
I
S
P
D
T
, T
J
stg
8.1 6.2
6.5 5.0
2.1 1.2
2.5 1.5
1.6 0.9
30
± 20
30
W
- 55 to 150 °C
V
A
THERMAL RESISTANCE RATINGS
Parameter Symbol Typical Maximum Unit
Maximum Junction-to-Ambient
a
t ≤ 10 s
Steady State 70 85
Maximum Junction-to-Foot Steady State
Notes: a. Surface Mounted on 1" x 1" FR4 board.
Document Number: 72269 S09-0870-Rev. C, 18-May-09
R
thJA
R
thJF
40 50
°C/W
20 24
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Page 2
Si9410BDY
Vishay Siliconix
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
Parameter Symbol Test Conditions Min. Typ. Max. Unit
Static
V
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Current
a
Drain-Source On-State Resistance
Forward Transconductance
Diode Forward Voltage
Dynamic
b
a
a
Total Gate Charge
Gate-Drain Charge
Tur n - O n D e l ay Time
Rise Time
Turn-Off Delay Time
Fall Ti me
Source-Drain Reverse Recovery Time
V
GS(th)
I
GSS
I
DSS
I
D(on)
a
R
DS(on)
g
fs
V
SD
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
t
rr
V
V
VDS = 15 V, V
I
Notes: a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %. b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
= VGS, ID = 250 µA
DS
VDS = 0 V, VGS = ± 20 V
V
= 30 V, V
DS
= 30 V, V
DS
GS
≥ 5 V, V
DS
V
= 10 V, ID = 8.1 A
GS
V
= 4.5 V, ID = 6.9 A
GS
= 0 V
GS
= 0 V, TJ = 55 °C
= 10 V
GS
VDS = 15 V, ID = 8.1 A
IS = 2.1 A, V
V
= 15 V, RL = 15 Ω
DD
≅ 1 A, V
D
GEN
= 0 V
GS
= 10 V, ID = 8.1 A
GS
= 10 V, Rg = 6 Ω
IF = 2.1 A, dI/dt = 100 A/µs
1.0 3.0 V
± 100 nA
1
5
30 A
0.019 0.024
0.026 0.033
20 S
0.8 1.2 V
15 23
3.2
2.5
10 15
15 25
30 45
11 20
25 50
µA
Ω
nCGate-Source Charge
ns
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
30
24
18
12
- Drain Current (A)I
D
6
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
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VGS = 10 V thru 5 V
- Drain-to-Source Voltage (V)
V
DS
Output Characteristics
4 V
3 V
30
24
18
12
- Drain Current (A)I
D
6
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
V
GS
TC = 125 °C
25 °C
- Gate-to-Source Voltage (V)
Transfer Characteristics
Document Number: 72269
S09-0870-Rev. C, 18-May-09
- 55 °C
Page 3
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
0.040
Si9410BDY
Vishay Siliconix
1200
0.035
)
0.030
0.025
0.020
- On-Resistance (R
0.015
DS(on)
0.010
0.005
0.000
- Gate-to-Source Voltage (V)
GS
V
VGS = 4.5 V
VGS = 10 V
0 5 10 15 20 25 30
ID - Drain Current (A)
On-Resistance vs. Drain Current
10
VDS = 15 V I
= 8.1 A
D
8
6
4
2
1000
800
600
400
C - Capacitance (pF)
200
C
rss
0
0 5 10 15 20 25 30
1.6
1.4
1.2
- On-Resistance
1.0
(Normalized)
DS(on)
R
0.8
C
oss
VDS - Drain-to-Source Voltage (V)
Capacitance
VGS = 10 V I
= 8.1 A
D
C
iss
0
0 3 6 9 12 15
30
10
- Source Current (A)I
S
1
0.0 0.2 0.4 0.6 0.8 1.0 1.2
VSD- Source-to-Drain Voltage (V)
Source-Drain Diode Forward Voltage
Document Number: 72269 S09-0870-Rev. C, 18-May-09
Qg- Total Gate Charge (nC)
Gate Charge
TJ = 150 °C
TJ = 25 °C
0.6
- 50 - 25 0 25 50 75 100 125 150
T
- Junction Temperature (°C)
J
On-Resistance vs. Junction Temperature
0.10
0.08
0.06
ID = 8.1 A
- On-Resistance (Ω)R
0.04
DS(on)
0.02
0.00 0246810
VGS - Gate-to-Source Voltage (V)
On-Resistance vs. Gate-to-Source Voltage
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Page 4
Si9410BDY
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
0.4
0.2
ID = 250 µA
0.0
- 0.2
Variance (V)V
GS(th)
- 0.4
- 0.6
- 0.8
- 50 - 25 0 25 50 75 100 125 150
TJ - Temperature (°C)
Threshold Voltage
100
- Drain Current (A)
D
I
0.1
0.01
50
40
30
Power (W)
20
10
0
-
3
I
Limited
DM
P(t) = 0.0001 s
10
10
Limited by R
DS(on)
10
*
P(t) = 0.001 s
I
D(on)
1
Limited
P(t) = 0.01 s
P(t) = 0.1 s
TA = 25 °C
Single Pulse
P(t) = 1 s
P(t) = 10 s
DC
BVDSS Limited
0.1 1 10 100
- Drain-to-Source Voltage (V)
V
DS
* V
> minimum VGS at which R
DS
DS(on)
is specified
Safe Operating Area
-
-
2
1
Time (s)
Single Pulse Power
1 100 6001010
0.1
Thermal Impedance
Normalized Effective Transient
0.01
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2
1
Duty Cycle = 0.5
0.2
0.1
0.05
0.02
-
4
10
Single Pulse
-
3
10
Notes:
P
DM
1. Duty Cycle, D =
2. Per Unit Base = R
3. T
- TA = PDMZ
JM
4. Surface Mounted
-
2
10
-
1
1 10 60010
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
t
1
t
2
t
1
t
2
= 70 °C/W
thJA
(t)
thJA
100
Document Number: 72269
S09-0870-Rev. C, 18-May-09
Page 5
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
2
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.01
10
0.05
0.02
-
4
Single Pulse
-
3
10
-
2
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Foot
Thermal Impedance
Normalized Effective Transient
Si9410BDY
Vishay Siliconix
-
1
11010
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?72269
Document Number: 72269
.
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S09-0870-Rev. C, 18-May-09
5
Page 6
SOIC (NARROW): 8-LEAD
JEDEC Part Number: MS-012
Package Information
Vishay Siliconix
D
e
BA
1
DIM
A 1.35 1.75 0.053 0.069
A
1
B 0.35 0.51 0.014 0.020
C 0.19 0.25 0.0075 0.010
D 4.80 5.00 0.189 0.196
E 3.80 4.00 0.150 0.157
e 1.27 BSC 0.050 BSC
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.50 0.93 0.020 0.037
q0°8°0°8°
S 0.44 0.64 0.018 0.026
ECN: C-06527-Rev. I, 11-Sep-06 DWG: 5498
8
1
0.25 mm (Gage Plane)
A
6
7
2
5
HE
3
4
S
h x 45
C
L
MILLIMETERS INCHES
Min Max Min Max
0.10 0.20 0.004 0.008
All Leads
q
0.101 mm
0.004"
Document Number: 71192 11-Sep-06
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1
Page 7
VISHAY SILICONIX
Trench FET® Power MOSFETs
Application Note 808
Mounting LITTLE FOOT®, SO-8 Power MOSFETs
Wharton McDaniel Surface-mounted LITTLE FOOT power MOSFETs use
integrated circuit and small-signal packages which have been been modified to provide the heat transfer capabilities required by power devices. Leadframe materials and
0.050
1.27
design, molding compounds, and die attach materials have been changed, while the footprint of the packages remains the same.
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs, (http://www.vishay.com/ppg?72286), for the
0.027
0.69
0.07
1.98
Figure 2. Dual MOSFET SO-8 Pad Pattern
basis of the pad design for a LITTLE FOOT SO-8 power MOSFET. In converting this recommended minimum pad to the pad set for a power MOSFET, designers must make two connections: an electrical connection and a thermal connection, to draw heat away from the package.
In the case of the SO-8 package, the thermal connections are very simple. Pins 5, 6, 7, and 8 are the drain of the MOSFET for a single MOSFET package and are connected together. In a dual package, pins 5 and 6 are one drain, and pins 7 and 8 are the other drain. For a small-signal device or integrated circuit, typical connections would be made with traces that are 0.020 inches wide. Since the drain pins serve the additional function of providing the thermal connection to the package, this level of connection is inadequate. The
The minimum recommended pad patterns for the single-MOSFET SO-8 with copper spreading (Figure 1) and dual-MOSFET SO-8 with copper spreading (Figure 2) show the starting point for utilizing the board area available for the heat-spreading copper. To create this pattern, a plane of copper overlies the drain pins. The copper plane connects the drain pins electrically, but more importantly provides planar copper to draw heat from the drain leads and start the process of spreading the heat so it can be dissipated into the ambient air. These patterns use all the available area underneath the body for this purpose.
total cross section of the copper may be adequate to carry the current required for the application, but it presents a large thermal impedance. Also, heat spreads in a circular fashion from the heat source. In this case the drain pins are the heat sources when looking at heat spread on the PC board.
Since surface-mounted packages are small, and reflow soldering is the most common way in which these are affixed to the PC board, “thermal” connections from the planar copper to the pads have not been used. Even if additional planar copper area is used, there should be no problems in the soldering process. The actual solder
0.288
7.3
connections are defined by the solder mask openings. By combining the basic footprint with the copper plane on the
0.050
1.27
0.027
0.69
0.078
1.98
0.2
5.07
0.196
5.0
Figure 1. Single MOSFET SO-8 Pad
Pattern With Copper Spreading
Document Number: 70740 www.vishay.com Revision: 18-Jun-07 1
drain pins, the solder mask generation occurs automatically.
A final item to keep in mind is the width of the power traces. The absolute minimum power trace width must be determined by the amount of current it has to carry. For thermal reasons, this minimum width should be at least
0.020 inches. The use of wide traces connected to the drain plane provides a low impedance path for heat to move away from the device.
0.288
7.3
8
0.2
5.07
With Copper Spreading
0.088
2.25
0.088
2.25
APPLICATION NOTE
Page 8
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR SO-8
0.172
(4.369)
0.028
(0.711)
Return to Index
Return to Index
0.022
(0.559)
0.246 (6.248)
Recommended Minimum Pads
Dimensions in Inches/(mm)
0.050
(1.270)
0.152
0.047
(3.861)
(1.194)
APPLICATION NOTE
www.vishay.com Document Number: 72606 22 Revision: 21-Jan-08
Page 9
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Vishay

Disclaimer

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