Datasheet SI7489DP-GE3 Datasheet (VISHAY)

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Page 1

P-Channel 100-V (D-S) MOSFET

Si7489DP

Vishay Siliconix

PRODUCT SUMMARY

VDS (V) R

- 100

0.041 at V

0.047 at V

DS(on)

(Ω)

= - 10 V

= - 4.5 V

- 28

(A)

Qg (Typ.)

54 nC

FEATURES

• Halogen-free According to IEC 61249-2-21 Available

• TrenchFET

Power MOSFET

PowerPAK SO-8

6.15 mm

Bottom View

Ordering Information: Si7489DP-T1-E3 (Lead (Pb)-free)

Si7489DP-T1-GE3 (Lead (Pb)-free and Halogen-free)

5.15 mm

P-Channel MOSFET

ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted

Parameter Symbol Limit Unit

Drain-Source Voltage V Gate-Source Voltage V

= 25 °C

= 70 °C

Continuous Drain Current (T

= 150 °C)

TA = 25 °C TA = 70 °C

Pulsed Drain Current I

= 25 °C

Continuous Source-Drain Diode Current

Avalanche Current Single-Pulse Avalanche Energy E

Maximum Power Dissipation

TA = 25 °C

L = 0.1 mH

= 25 °C

= 70 °C 53

= 25 °C

TA = 70 °C

Operating Junction and Storage Temperature Range TJ, T

Soldering Recommendations (Peak Temperature)

d, e

stg

- 100 ± 20

- 28

- 24.9

b, c

- 7.8

b, c

- 6.2

- 40

- 28

b, c

- 4.3

- 35 61 mJ 83

b, c

5.2

b, c

3.3

- 55 to 150 260

°C

THERMAL RESISTANCE RATINGS

Parameter Symbol Typical Maximum Unit

Maximum Junction-to-Ambient Maximum Junction-to-Case (Drain) Steady State R

Notes: a. Package Limited. b. Surface Mounted on 1" x 1" FR4 board. c. t = 10 s. d. See Solder Profile (www.vishay.com/ppg?73257

(not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not

required to ensure adequate bottom side solder interconnection. e. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components. f. Maximum under Steady State conditions is 65 °C/W.

Document Number: 73436 S09-0271-Rev. C, 16-Feb-09

b, f

t ≤ 10 s R

thJA

thJC

19 24

1.2 1.5

°C/W

). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed copper

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Page 2

Si7489DP

Vishay Siliconix

SPECIFICATIONS TJ = 25 °C, unless otherwise noted

Parameter Symbol Test Conditions Min. Typ. Max. Unit

Static

Drain-Source Breakdown Voltage

Temperature Coefficient ΔVDS/T

Temperature Coefficient ΔV

GS(th)

Gate-Source Threshold Voltage

Gate-Source Leakage

Zero Gate Voltage Drain Current

On-State Drain Current

Drain-Source On-State Resistance

Forward Transconductance

Dynamic

Input Capacitance

Reverse Transfer Capacitance

Total Gate Charge

Gate-Source Charge

Gate-Drain Charge

Gate Resistance

Tur n -O n De l a y T i m e

Rise Time

Turn-Off Delay Time

Fall Time

Tur n -O n De l a y T i m e

Rise Time

Turn-Off Delay Time

Fall Time

GS(th)/TJ

GS(th)

GSS

DSS

D(on)

DS(on)

iss

oss

rss

d(on)

d(off)

d(on)

d(off)

Drain-Source Body Diode Characteristics

Continuous Source-Drain Diode Current

Pulse Diode Forward Current

Body Diode Voltage

Body Diode Reverse Recovery Time

Body Diode Reverse Recovery Charge

Reverse Recovery Fall Time

Reverse Recovery Rise Time

Notes: a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %. b. Guaranteed by design, not subject to production testing.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the de vice. These are stress rating s only, and functiona l operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

VGS = 0 V, ID = - 250 µA

ID = - 250 µA

= VGS, ID = - 250 µA

VDS = 0 V, VGS = ± 20 V

= - 100 V, V

≥ 5 V, V

= - 10 V, ID = - 7.8 A

= - 4.5 V, ID = - 7.3 A

= 0 V

= 0 V, TJ = 55 °C

= - 10 V

VDS = - 15 V, ID = - 7.8 A

VDS = - 50 V, V

= - 50 V, V

= 0 V, f = 1 MHz

= - 10 V, ID = - 7.8 A

= - 4.5 V, ID = - 7.8 A

f = 1 MHz 4 Ω

= - 50 V, RL = 8.1 Ω

≅ - 6.2 A, V

= - 10 V, Rg = 1 Ω

GEN

= - 50 V, RL = 8.1 Ω

= - 4.5 V, Rg = 1 Ω

GEN

TC = 25 °C

IS = - 6.2 A

IF = - 6.2 A, dI/dt = 100 A/µs, TJ = 25 °C

- 100 V

- 113

5.5

mV/°C

- 1 - 3 V

± 100 nA

- 1

- 10

- 40 A

0.033 0.041

0.038 0.047

38 S

4600

230

175

106 160

54 81

15 25

20 30

110 165

100 150

42 65

160 240

100 150

- 28

- 40

- 0.8 - 1.2 V

60 90 ns

150 225 nC

µA

pFOutput Capacitance

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Document Number: 73436

S09-0271-Rev. C, 16-Feb-09

Page 3

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

Si7489DP

Vishay Siliconix

- Drain Current (A)I

0.0 0.5 1.0 1.5 2.0 2.5 3.0

- Drain-to-Source Voltage (V)

VGS = 10 thru 4 V

Output Characteristics

0.042

0.040

0.038

VGS = 4.5 V

3 V

2 V

- Drain Current (A)I

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

- Gate-to-Source Voltage (V)

TA = 125 °C

25 °C

Transfer Characteristics

7000

6000

5000

4000

iss

- 55 °C

- On-Resistance (Ω)

0.036

DS(on)

0.034

0.032 0 5 10 15 20 25 30 35 40

- Drain Current (A)

VGS = 10 V

On-Resistance vs. Drain Current and Gate Voltage

ID = 7.8 A

VDS = 50 V

VDS = 80 V

- Gate-to-Source Voltage (V)

0 20406080100120

Qg - Total Gate Charge (nC)

Gate Charge

3000

C - Capacitance (pF)

2000

oss

1000

0 1020304050607080

rss

VDS - Drain-to-Source Voltage (V)

Capacitance

2.3

ID = 7.8 A

2.0

1.7

1.4

- On-Resistance (Normalized)

1.1

DS(on)

0.8

0.5

- 50 - 25 0 25 50 75 100 125 150

VGS = 10 V, 4.5 V

- Junction Temperature (°C)

On-Resistance vs. Junction Temperature

Document Number: 73436 S09-0271-Rev. C, 16-Feb-09

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Page 4

Si7489DP

Vishay Siliconix

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

TJ = 150 °C

- Source Current (A)I

0.00 0.2 0.4 0.6 0.8

- Source-to-Drain Voltage (V)

Source-Drain Diode Forward Voltage

2.4

2.2

2.0

1.8

(V)

1.6

GS(th)

1.4

1.2

1.0

TJ = 25 °C

ID = 250 µA

1.0 1.2

- Drain-to-Source On-Resistance (Ω)

DS(on)

Power (W)

0.08

ID = 7.8 A

0.07

TA = 125 °C

0.06

0.05

0.04

0.03

0.02 2345678910

VGS - Gate-to-Source Voltage (V)

= 25 °C

On-Resistance vs. Gate-to-Source Voltage

0.8

- 50 - 25 0 25 50 75 100 125 150 175

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- Temperature (°C)

Threshold Voltage

- Drain Current (A)I

0.01 0.1 1 10 100 1000

100

Limited by R

DS(on)*

0.1

0.01

0.001

0.1 1 10 1000

* V

> minimum VGS at which R

TA = 25 °C

Single Pulse

- Drain-to-Source Voltage (V)

DS(on)

100 µs

1 ms

10 ms

100 ms

1 s

10 s

100

is specified

Safe Operating Area, Junction-to-Ambient

Time (s)

Single Pulse Power, Junction-to-Ambient

Document Number: 73436

S09-0271-Rev. C, 16-Feb-09

Page 5

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

Si7489DP

Vishay Siliconix

Package Limited

- Drain Current (A)

0 25 50 75 100 125 150

TC - Case Temperature (°C)

Current Derating*

100

Power (W)

100

25 50 75 100 125 150

TC - Case Temperature (°C)

Power Derating

- Peak Avalanche Current (A)

0.000001 0.0001 0.01

TA=

L·I

BV - V

0.00001

- Time In Avalanche (s)

0.001

Single Pulse Avalanche Capability

* The power dissipation PD is based on T dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package

= 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper

J(max)

limit.

Document Number: 73436 S09-0271-Rev. C, 16-Feb-09

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Page 6

Si7489DP

Vishay Siliconix

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

Duty Cycle = 0.5

0.2

0.1

0.01

0.05

0.02

Single Pulse

-2

-1

1 10 100010

Square Wave Pulse Duration (s)

Normalized Thermal Transient Impedance, Junction-to-Ambient

Thermal Impedance

Normalized Effective Transient

Notes:

- TA = PDMZ

1. Duty Cycle, D =

2. Per Unit Base = R

3. T

4. Surface Mounted

100

thJA

t t

= 65 °C/W

(t)

0.1

Thermal Impedance

Normalized Effective Transient

0.01

Duty Cycle = 0.5

0.2

0.1

0.05

0.02

-4

Single Pulse

-3

-2

Square Wave Pulse Duration (s)

Normalized Thermal Transient Impedance, Junction-to-Case

-1

110

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silic on Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?73436

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Document Number: 73436

S09-0271-Rev. C, 16-Feb-09

Page 7

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PowerPAK® SO-8, (Single/Dual)

Package Information

Vishay Siliconix

Notes

Inch will govern.

Dimensions exclusive of mold gate burrs.

Dimensions exclusive of mold flash and cutting burrs.

DIM.

A 0.97 1.04 1.12 0.038 0.041 0.044

A1 - 0.05 0 - 0.002

b 0.33 0.41 0.51 0.013 0.016 0.020

c 0.23 0.28 0.33 0.009 0.011 0.013

D 5.05 5.15 5.26 0.199 0.203 0.207 D1 4.80 4.90 5.00 0.189 0.193 0.197 D2 3.56 3.76 3.91 0.140 0.148 0.154 D3 1.32 1.50 1.68 0.052 0.059 0.066 D4 0.57 typ. 0.0225 typ. D5 3.98 typ. 0.157 typ.

E 6.05 6.15 6.25 0.238 0.242 0.246

E1 5.79 5.89 5.99 0.228 0.232 0.236 E2 3.48 3.66 3.84 0.137 0.144 0.151 E3 3.68 3.78 3.91 0.145 0.149 0.154

E4 0.75 typ. 0.030 typ.

e 1.27 BSC 0.050 BSC

K 1.27 typ. 0.050 typ. K1 0.56 - - 0.022 - -

H 0.51 0.61 0.71 0.020 0.024 0.028

L 0.51 0.61 0.71 0.020 0.024 0.028

L1 0.06 0.13 0.20 0.002 0.005 0.008

 0° - 12° 0° - 12°

W 0.15 0.25 0.36 0.006 0.010 0.014

M 0.125 typ. 0.005 typ.

ECN: S17-0173-Rev. L, 13-Feb-17 DWG: 5881

Detail Z

Backside View of Single Pad

D3 (2x)

Backside View of Dual Pad

MILLIMETERS INCHES

MIN. NOM. MAX. MIN. NOM. MAX.

Revison: 13-Feb-17

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Document Number: 71655

Page 8

VISHAY SILICONIX

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Power MOSFETs

Application Note AN821

PowerPAK® SO-8 Mounting and Thermal Considerations

by Wharton McDaniel

MOSFETs for switching applications are now available with die on resistances around 1 m and with the capability to handle 85 A. While these die capabilities represent a major advance over what was available just a few years ago, it is important for power MOSFET packaging technology to keep pace. It should be obvious that degradation of a high performance die by the package is undesirable. PowerPAK is a new package technology that addresses these issues. In this application note, PowerPAK’s construction is described. Following this mounting information is presented including land patterns and soldering profiles for maximum reliability. Finally, thermal and electrical performance is discussed.

THE PowerPAK PACKAGE

The PowerPAK package was developed around the SO-8 package (figure 1). The PowerPAK SO-8 utilizes the same footprint and the same pin-outs as the standard SO-8. This allows PowerPAK to be substituted directly for a standard SO-8 package. Being a leadless package, PowerPAK SO-8 utilizes the entire SO-8 footprint, freeing space normally occupied by the leads, and thus allowing it to hold a larger die than a standard SO-8. In fact, this larger die is slightly larger than a full sized DPAK die. The bottom of the die attach pad is exposed for the purpose of providing a direct, low resistance thermal path to the substrate the device is mounted on. Finally, the package height is lower than the standard SO-8, making it an excellent choice for applications with space constraints.

PowerPAK SO-8 SINGLE MOUNTING

The PowerPAK single is simple to use. The pin arrangement (drain, source, gate pins) and the pin dimensions are the same as standard SO-8 devices (see figure 2). Therefore, the PowerPAK connection pads match directly to those of the SO-8. The only difference is the extended drain connection area. To take immediate advantage of the PowerPAK SO-8 single devices, they can be mounted to existing SO-8 land patterns.

Standard SO-8 PowerPAK SO-8

Fig. 2

The minimum land pattern recommended to take full advantage of the PowerPAK thermal performance see Application Note 826, Recommended Minimum Pad

Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs. Click on the PowerPAK SO-8 single in the index

of this document.

In this figure, the drain land pattern is given to make full contact to the drain pad on the PowerPAK package.

This land pattern can be extended to the left, right, and top of the drawn pattern. This extension will serve to increase the heat dissipation by decreasing the thermal resistance from the foot of the PowerPAK to the PC board and therefore to the ambient. Note that increasing the drain land area beyond a certain point will yield little decrease in foot-to-board and foot-to-ambient thermal resistance. Under specific conditions of board configuration, copper weight and layer stack, experiments have found that more than about 0.25 in (in addition to the drain land) will yield little improvement in thermal performance.

to 0.5 in2 of additional copper

APPLICATION NOTE

Fig. 1 PowerPAK 1212 Devices

Revision: 16-Mai-13

For technical questions, contact: [email protected]

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Document Number: 71622

Page 9

Application Note AN821

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Vishay Siliconix

PowerPAK® SO-8 Mounting and Thermal Considerations

PowerPAK SO-8 DUAL

The pin arrangement (drain, source, gate pins) and the pin dimensions of the PowerPAK SO-8 dual are the same as standard SO-8 dual devices. Therefore, the PowerPAK device connection pads match directly to those of the SO-8. As in the single-channel package, the only exception is the extended drain connection area. Manufacturers can likewise take immediate advantage of the PowerPAK SO-8 dual devices by mounting them to existing SO-8 dual land patterns.

To take the advantage of the dual PowerPAK SO-8’s thermal performance, the minimum recommended land pattern can be found in Application Note 826,

Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs. Click on the

PowerPAK 1212-8 dual in the index of this document.

The gap between the two drain pads is 24 mils. This matches the spacing of the two drain pads on the PowerPAK SO-8 dual package.

REFLOW SOLDERING

Vishay Siliconix surface-mount packages meet solder reflow reliability requirements. Devices are subjected to solder reflow as a test preconditioning and are then reliability-tested using temperature cycle, bias humidity, HAST, or pressure pot. The solder reflow temperature profile used, and the temperatures and time duration, are shown in figures 3 and 4.

For the lead (Pb)-free solder profile, see

www.vishay.com/doc?73257.

Fig. 3 Solder Reflow Temperature Profile

Ramp-Up Rate + 3 °C /s max.

Temperature at 150 - 200 °C 120 s max.

Temperature Above 217 °C 60 - 150 s

Maximum Temperature 255 + 5/- 0 °C

Time at Maximum Temperature

Ramp-Down Rate + 6 °C/s max.

30 s

260 °C

3 °C(max) 6 ° C/s (max.)

150 - 200 °C

Maximum peak temperature at 240 °C is allowed.

Fig. 4 Solder Reflow Temperatures and Time Durations

Revision: 16-Mai-13

APPLICATION NOTE

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

For technical questions, contact: [email protected]

60 s (min.)

Pre-Heating Zone

217 °C

150 s (max.)

Reflow Zone

Document Number: 71622

Page 10

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Si4874DY vs. Si7446DP PPAK on a 4-Layer Board

SO-8 Pattern, Trough Under Drain

Pulse Duration (sec)

) s

ttaw/

C ( e

cn adep

0.0001

100000.01

Si4874DY

Si7446DP

100

Rth vs. Spreading Copper

(0 %, 50 %, 100 % Back Copper)

Spreading Copper (sq in)

)sttaw/C(

ecn

adep

0.00

0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00

0 %

50 %

100 %

PowerPAK® SO-8 Mounting and Thermal Considerations

THERMAL PERFORMANCE

Introduction

A basic measure of a device’s thermal performance is the junction-to-case thermal resistance, R junction-to-foot thermal resistance, R

This parameter is

thJF

measured for the device mounted to an infinite heat sink and is therefore a characterization of the device only, in other words, independent of the properties of the object to which the device is mounted. Table 1 shows a comparison of the DPAK, PowerPAK SO-8, and standard SO-8. The PowerPAK has thermal performance equivalent to the DPAK, while having an order of magnitude better thermal performance over the SO-8.

TABLE 1 - DPAK AND POWERPAK SO-8 EQUIVALENT STEADY STATE PERFORMANCE

DPAK

Thermal

Resistance R

1.2 °C/W 1 °C/W 16 °C/W

thJC

Thermal Performance on Standard SO-8 Pad Pattern

Because of the common footprint, a PowerPAK SO-8 can be mounted on an existing standard SO-8 pad pattern. The question then arises as to the thermal performance of the PowerPAK device under these conditions. A characterization was made comparing a standard SO-8 and a PowerPAK device on a board with a trough cut out underneath the PowerPAK drain pad. This configuration restricted the heat flow to the SO-8 land pads. The results are shown in figure 5.

PowerPAK

SO-8

, or the

thJC

Standard

SO-8

Application Note AN821

Vishay Siliconix

Because of the presence of the trough, this result suggests a minimum performance improvement of 10 °C/W by using a PowerPAK SO-8 in a standard SO-8 PC board mount.

The only concern when mounting a PowerPAK on a standard SO-8 pad pattern is that there should be no traces running between the body of the MOSFET. Where the standard SO-8 body is spaced away from the pc board, allowing traces to run underneath, the PowerPAK sits directly on the pc board.

Thermal Performance - Spreading Copper

Designers may add additional copper, spreading copper, to the drain pad to aid in conducting heat from a device. It is helpful to have some information about the thermal performance for a given area of spreading copper.

Figure 6 shows the thermal resistance of a PowerPAK SO-8 device mounted on a 2-in. 2-in., four-layer FR-4 PC board. The two internal layers and the backside layer are solid copper. The internal layers were chosen as solid copper to model the large power and ground planes common in many applications. The top layer was cut back to a smaller area and at each step junction-to-ambient thermal resistance measurements were taken. The results indicate that an area above 0.3 to 0.4 square inches of spreading copper gives no additional thermal performance improvement. A subsequent experiment was run where the copper on the back-side was reduced, first to 50 % in stripes to mimic circuit traces, and then totally removed. No significant effect was observed.

Fig. 5 PowerPAK SO-8 and Standard SO-0 Land Pad Thermal

Revision: 16-Mai-13

APPLICATION NOTE

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

Path

For technical questions, contact: [email protected]

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Fig. 6 Spreading Copper Junction-to-Ambient Performance

Document Number: 71622

Page 11

Application Note AN821

0.6

0.8

1.0

1.2

1.4

1.6

1.8

-50 - 25 0 25 50 75 100 125 150

= 10 V

= 23 A

On-Resistance vs. Junction Temperature

- Junction Temperature (°C)

)dezilamroN(( ecnatsiseR-nO -R

)no(SD

)

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PowerPAK® SO-8 Mounting and Thermal Considerations

SYSTEM AND ELECTRICAL IMPACT OF PowerPAK SO-8

In any design, one must take into account the change in MOSFET R

A MOSFET generates internal heat due to the current passing through the channel. This self-heating raises the junction temperature of the device above that of the PC board to which it is mounted, causing increased power dissipation in the device. A major source of this problem lies in the large values of the junction-to-foot thermal resistance of the SO-8 package.

PowerPAK SO-8 minimizes the junction-to-board thermal resistance to where the MOSFET die temperature is very close to the temperature of the PC board. Consider two devices mounted on a PC board heated to 105 °C by other components on the board (figure 8).

with temperature (figure 7).

DS(on)

Fig. 7 MOSFET R

DS(on)

vs. Temperature

Suppose each device is dissipating 2.7 W. Using the junction-to-foot thermal resistance characteristics of the PowerPAK SO-8 and the standard SO-8, the die temperature is determined to be 107 °C for the PowerPAK (and for DPAK) and 148 °C for the standard SO-8. This is a 2 °C rise above the board temperature for the PowerPAK and a 43 °C rise for the standard SO-8. Referring to figure 7, a 2 °C difference has minimal effect on R 43 °C difference has a significant effect on R

DS(on)

whereas a

Minimizing the thermal rise above the board temperature by using PowerPAK has not only eased the thermal design but it has allowed the device to run cooler, keep r

DS(on)

low, and permits the device to handle more current than the same MOSFET die in the standard SO-8 package.

CONCLUSIONS

PowerPAK SO-8 has been shown to have the same thermal performance as the DPAK package while having the same footprint as the standard SO-8 package. The PowerPAK SO-8 can hold larger die approximately equal in size to the maximum that the DPAK can accommodate implying no sacrifice in performance because of package limitations.

Recommended PowerPAK SO-8 land patterns are provided to aid in PC board layout for designs using this new package.

Thermal considerations have indicated that significant advantages can be gained by using PowerPAK SO-8 devices in designs where the PC board was laid out for the standard SO-8. Applications experimental data gave thermal performance data showing minimum and typical thermal performance in a SO-8 environment, plus information on the optimum thermal performance obtainable including spreading copper. This further emphasized the DPAK equivalency.

PowerPAK SO-8 therefore has the desired small size characteristics of the SO-8 combined with the attractive thermal characteristics of the DPAK package.

PowerPAK SO-8

107 °C

0.8 °C/W

Fig. 8 Temperature of Devices on a PC Board

Revision: 16-Mai-13

PC Board at 105 °C

APPLICATION NOTE

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Standard SO-8

148 °C

16 C/W

For technical questions, contact: [email protected]

Document Number: 71622

Page 12

RECOMMENDED MINIMUM PADS FOR PowerPAK® SO-8 Single

0.260

(6.61)

0.150

(3.81)

0.024 (0.61)

Application Note 826

Vishay Siliconix

Return to Index

0.026 (0.66)

0.050

(1.27)

0.050

(1.27)

0.032

(0.82)

Recommended Minimum Pads

Dimensions in Inches/(mm)

0.154

(3.91)

0.040

(1.02)

0.174

(4.42)

APPLICATION NOTE

Document Number: 72599 www.vishay.com Revision: 21-Jan-08 15

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Legal Disclaimer Notice

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Vishay

Disclaimer



ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.

Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product.

Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special, consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular purpose, non-infringement and merchantability.

Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements about the suitability of products for a particular application. It is the customer’s responsibility to validate that a particular product with the properties described in the product specification is suitable for use in a particular application. Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over time. All operating parameters, including typical parameters, must be validated for each customer application by the customer’s technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein.

Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the Vishay product could result in personal injury or death. Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.

Revision: 08-Feb-17

Document Number: 91000