Datasheet si6413dq Datasheet

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Page 1

P-Channel 1.8-V (G-S) MOSFET

Si6413DQ

Vishay Siliconix

PRODUCT SUMMARY

VDS (V) R

0.010 at V

- 20

0.013 at V

0.016 at V

Ordering Information: Si6413DQ-T1-GE3 (Lead (Pb)-free and Halogen-free)

(Ω)I

DS(on)

= - 4.5 V

= - 2.5 V

= - 1.8 V

- 8.8

- 7.6

- 6.8

TSSOP-8

Si6413DQ

Top View

(A)

FEATURES

• Halogen-free

• TrenchFET

Power MOSFET

APPLICATIONS

• Load Switch

• PA Switch

• Charger Switch

P-Channel MOSFET

* Source Pins 2, 3, 6 and 7

must be tied common.

RoHS

COMPLIANT

ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted

Parameter Symbol 10 s Steady State Unit

Drain-Source Voltage

Gate-Source Voltage

Continuous Drain Current (T

= 150 °C)

Pulsed Drain Current (10 µs Pulse Width)

Continuous Source Current (Diode Conduction)

Maximum Power Dissipation

Operating Junction and Storage Temperature Range

TA = 25 °C

= 70 °C

TA = 25 °C

= 70 °C

, T

stg

- 8.8 - 7.2

- 7.0 - 5.7

- 1.35 - 0.95

- 20

± 8

- 30

1.5 1.05

1.0 0.67

- 55 to 150 °C

THERMAL RESISTANCE RATINGS

Parameter Symbol Typical Maximum Unit

Maximum Junction-to-Ambient

t ≤ 10 s

Steady State 100 120

Maximum Junction-to-Foot Steady State

Notes: a. Surface Mounted on 1" x 1" FR4 board.

Document Number: 72084 S-80682-Rev. B, 31-Mar-08

thJA

thJF

60 83

°C/W

35 45

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Page 2

Si6413DQ

Vishay Siliconix

SPECIFICATIONS TJ = 25 °C, unless otherwise noted

Parameter Symbol Test Conditions Min. Typ. Max. Unit

Static

Gate Threshold Voltage

Gate-Body Leakage

Zero Gate Voltage Drain Current

On-State Drain Current

Drain-Source On-State Resistance

Forward Transconductance

Diode Forward Voltage

Dynamic

Total Gate Charge

Gate-Drain Charge

Tur n -O n D el a y T im e

Rise Time

Turn-Off Delay Time

Fall Time

Source-Drain Reverse Recovery Time

GS(th)

GSS

DSS

D(on)

DS(on)

d(on)

d(off)

Notes: a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %. b. Guaranteed by design, not subject to production testing.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

= VGS, ID = - 400 µA

VDS = 0 V, VGS = ± 8 V

= - 16 V, V

= - 5 V, V

= - 4.5 V, ID = - 8.8 A

= - 2.5 V, ID = - 7.6 A

= - 1.8 V, ID = - 6.8 A

= 0 V

= 0 V, TJ = 70 °C

= - 4.5 V

VDS = - 15 V, ID = - 8.8 A

IS = - 1.3 A, V

= - 10 V, V

= - 10 V, RL = 10 Ω

≅ - 1 A, V

GEN

= 0 V

= - 5 V, ID = - 8.8 A

= - 4.5 V, RG = 6 Ω

IF = - 1.3 A, di/dt = 100 A/µs

- 0.40 - 0.8 V

± 100 nA

- 1

- 10

- 20 A

0.008 0.010

0.010 0.013

0.013 0.016

45 S

- 0.58 - 1.1 V

69 105

9.5

15.5

55 85

120 200

305 470

160 250

90 150

µA

nCGate-Source Charge

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

- Drain Current (A)I

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VGS = 5 thru 2 V

1.5 V

1.0 V

012345

- Drain-to-Source Voltage (V)

Output Characteristics

- Drain Current (A)I

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

TC = 125 °C

25 °C

- Gate-to-Source Voltage (V)

- 55 °C

Transfer Characteristics

Document Number: 72084

S-80682-Rev. B, 31-Mar-08

Page 3

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

0.030

Si6413DQ

Vishay Siliconix

8000

- On-Resistance (Ω)R

DS(on)

- Gate-to-Source Voltage (V)

0.024

0.018

0.012

0.006

0.000 0 6 12 18 24 30

- Drain Current (A)

VGS = 1.8 V

VGS = 2.5 V

VGS = 4.5 V

On-Resistance vs. Drain Current

VDS = 10 V I

= 8.8 A

6400

4800

3200

C - Capacitance (pF)

1600

048121620

1.6

VGS = 4.5 V I

1.4

1.2

(Normalized)

1.0

DS(on)

R - On-Resistance

0.8

iss

oss

rss

VDS - Drain-to-Source Voltage (V)

Capacitance

= 8.8 A

0 1428425670

- Source Current (A)I

0.1

0.0 0.2 0.4 0.6 0.8 1.0 1.2

Source-Drain Diode Forward Voltage

Document Number: 72084 S-80682-Rev. B, 31-Mar-08

Qg - Total Gate Charge (nC)

Gate Charge

TJ = 150 °C

- Source-to-Drain Voltage (V)

TJ = 25 °C

0.6

- 50 - 25 0 25 50 75 100 125 150

- Junction Temperature (°C)

On-Resistance vs. Junction Temperature

0.06

0.05

- On-Resistance (Ω)R

DS(on)

0.04

0.03

0.02

0.01

0.00 0123456

VGS - Gate-to-Source Voltage (V)

ID = 8.8 A

On-Resistance vs. Gate-to-Source Voltage

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Si6413DQ

Vishay Siliconix

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

0.4

0.2

ID = 400 µA

0.0

Variance (V)V

GS(th)

- 0.2

- 0.4

- 50 - 25 0 25 50 75 100 125 150

TJ - Temperature (°C)

Threshold Voltage

100

- Drain Current (A)I

0.1

0.01

Power (W)

-2

Single Pulse Power, Junction-to-Ambient

Limited

by R *

DS(on)

1 ms

10 ms

100 ms

1 s

TC = 25 °C

Single Pulse

10 s

0.1 1 10 100

VDS- Drain-to-Source Voltage (V)

> minimum VGSat which R

DS(on)

is specified

Safe Operating Area, Junction-to-Case

-1

1 1001010

Time (s)

Thermal Impedance

Normalized Effective Transient

0.01

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0.1

-4

Duty Cycle = 0.5

0.2

0.1

0.05

0.02

Single Pulse

Notes:

thJA

100

(t)

= 100 °C/W

1. Duty Cycle, D =

2. Per Unit Base = R

- TA = PDMZ

3. T

4. Surface Mounted

-3

-2

-1

1 10 60010

Square Wave Pulse Duration (s)

Normalized Thermal Transient Impedance, Junction-to-Ambient

Document Number: 72084

S-80682-Rev. B, 31-Mar-08

Page 5

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

Duty Cycle = 0.5

0.2

0.1

Thermal Impedance

0.05

Si6413DQ

Vishay Siliconix

Normalized Effective Transient

0.01

0.02

Single Pulse

-4

-3

-2

Square Wave Pulse Duration (s)

-1

11010

Normalized Thermal Transient Impedance, Junction-to-Foot

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?72084.

Document Number: 72084

www.vishay.com

S-80682-Rev. B, 31-Mar-08

Page 6

TSSOP: 8ĆLEAD

JEDEC Part Number: MO-153

R 0.10

Corners)

(4 Corners)

R 0.10

Package Information

Vishay Siliconix

MILLIMETERS

Dim Min Nom Max

B C D E

0.25 (Gage Plane)

oK1

ECN: S-03946—Rev. G, 09-Jul-01 DWG: 5844

– – 1.20

0.05 0.10 0.15

0.80 1.00 1.05

0.19 0.28 0.30 – 0.127 –

2.90 3.00 3.10

6.20 6.40 6.60

4.30 4.40 4.50 – 0.65 –

0.45 0.60 0.75

0.90 1.00 1.10 – – 0.10

0_ 3_ 6_

Document Number: 71201 06-Jul-01

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Page 7

The Next Step in Surface-Mount Power MOSFETs

Wharton McDaniel and David Oldham

AN1001

Vishay Siliconix

LITTLE FOOTR TSSOP-8

When Vishay Siliconix introduced its LITTLE FOOT MOSFETs, it was the first time that power MOSFETs had been offered in a true surface-mount package, the SOIC. LITTLE FOOT immediately found a home in new small form factor disk drives, computers, and cellular phones.

The new LITTLE FOOT TSSOP-8 power MOSFETs are the natural evolutionary response to the continuing demands of many markets for smaller and smaller packages. LITTLE FOOT TSSOP-8 MOSFETs have a smaller footprint and a lower profile than LITTLE FOOT SOICs, while maintaining low r

and high thermal performance. Vishay Siliconix has

DS(on)

accomplished this by putting one or two high-density MOSFET die in a standard 8-pin TSSOP package mounted on a custom leadframe.

THE TSSOP-8 PACKAGE

LITTLE FOOT TSSOP-8 power MOSFETs require approximately half the PC board area of an equivalent LITTLE FOOT device (Figure 1). In addition to the reduction in board area, the package height has been reduced to 1.1 mm.

This is the low profile demanded by applications such as PCMCIA cards.

It reduces the power package to the same height as many resistors and capacitors in 0805 and 0605 sizes. It also allows placement on the “passive” side of the PC board.

The standard pinouts of the LITTLE FOOT TSSOP-8 packages have been changed from the standard established by LITTLE FOOT. This change minimizes the contribution of interconnection resistance to r

and maximizes the

DS(on)

transfer of heat out of the package.

Figure 2 shows the pinouts for a single-die TSSOP. Notice that both sides of the package have Source and Drain connections, whereas LITTLE FOOT has the Source and Gate connections on one side of the package, and the Drain connections are on the opposite side.

Drain

Source

Gate

Drain

Source

Drain

Top View

Side View

Figure 1. An TSSOP-8 Package Next to a SOIC-8 Package

with Views from Both Top and Side

Document Number: 70571 12-Dec-03

Figure 2. Pinouts for Single Die TSSOP

Figure 3 shows the standard pinouts for a dual-die TSSOP-8. In this case, the connections for each individual MOSFET occupy one side.

Drain 1

Source 1

Gate 1

Figure 3. Pinouts for Dual-Die TSSOP

Drain 2

Source 2

Gate 2

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Page 8

AN1001

Vishay Siliconix

Because the TSSOP has a fine pitch foot print, the pad layout is somewhat more demanding than the layout of the SOIC. Careful attention must be paid to silkscreen-to-pad and soldermask-to-pad clearances. Also, fiduciary marks may be required. The design and spacing of the pads must be dealt with carefully. The pads must be sized to hold enough solder paste to form a good joint, but should not be so large or so placed as to extend under the body, increasing the potential for solder bridging. The pad pattern should allow for typical pick and place errors of 0.25 mm. See Application Note 826,

Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs,

(http://www.vishay.com/doc?72286), for the recommended pad pattern for PC board layout.

THERMAL ISSUES

Figure 5.

The actual test is based on dissipating a known amount of power in the device for a known period of time so the junction temperature is raised to 150_C. The starting and ending junction temperatures are determined by measuring the forward drop of the body diode. The thermal resistance for that pulse width is defined by the temperature rise of the junction above ambient and the power of the pulse, DTja/P.

LITTLE FOOT TSSOP MOSFETs have been given thermal ratings using the same methods used for LITTLE FOOT. The maximum thermal resistance junction-to-ambient is 83_C/W for the single die and 125_C/W for dual-die parts. TSSOP relies on a leadframe similar to LITTLE FOOT to remove heat from the package. The single- and dual-die leadframes are shown in Figure 4.

a) 8-Pin Single-Pad TSSOP

b) 8-Pin Dual-Pad TSSOP

Figure 4. Leadframe

Figure 6 shows the single pulse power curve of the Si6436DQ laid over the curve of the Si9936DY to give a comparison of the thermal performance. The die in the two devices have equivalent die areas, making this a comparison of the packaging. This comparison shows that the TSSOP package performs as well as the SOIC out to 150 ms, with long-term performance being 0.5 W less. Although the thermal performance is less, LITTLE FOOT TSSOP will operate in a large percentage of applications that are currently being served by LITTLE FOOT.

14.0

12.0

10.0

8.0

6.0

Power (W)

4.0

2.0

0.0

0.1 1 10 100

Figure 6. Comparison of Thermal Performance

Si6436

Si9936

Time (Sec.)

The MOSFETs are characterized using a single pulse power test. For this test the device mounted on a one-square-inch piece of copper clad FR-4 PC board, such as those shown in Figure 5. The single pulse power test determines the maximum amount of power the part can handle for a given pulse width and defines the thermal resistance junction-to-ambient. The test is run for pulse widths ranging from approximately 10 ms to 100 seconds. The thermal resistance at 30 seconds is the rated thermal resistance for the part. This rating was chosen to allow comparison of packages and leadframes. At longer pulse widths, the PC board thermal charateristics become dominant, making all parts look the same.

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CONCLUSION

TSSOP power MOSFETs provide a significant reduction in PC board footprint and package height, allowing reduction in board size and application where SOICs will not fit. This is accomplished using a standard IC package and a custom leadframe, combining small size with good power handling capability.

For the TSSOP-8 package outline visit:

http://www.vishay.com/doc?71201

For the SOIC-8 package outline visit:

http://www.vishay.com/doc?71192

Document Number: 70571

12-Dec-03

Page 9

Mounting LITTLE FOOTR TSSOP-8 Power MOSFETs

Wharton McDaniel

AN806

Vishay Siliconix

Surface-mounted LITTLE FOOT power MOSFETs use integrated circuit and small-signal packages which have been been modified to provide the heat transfer capabilities required by power devices. Leadframe materials and design, molding compounds, and die attach materials have been changed, while the footprint of the packages remains the same.

See Application Note 826, Recommended Minimum Pad

Patterns With Outline Drawing Access for Vishay Siliconix MOSFET, (http://www.vishay.com/doc?72286), for the basis

of the pad design for a LITTLE FOOT TSSOP-8 power MOSFET package footprint. In converting the footprint to the pad set for a power device, designers must make two connections: an electrical connection and a thermal connection, to draw heat away from the package.

In the case of the TSSOP-8 package, the thermal connections are very simple. Pins 1, 5, and 8 are the drain of the MOSFET for a single MOSFET package and are connected together. In the dual package, pins 1 and 8 are the two drains. For a small-signal device or integrated circuit, typical connections would be made with traces that are 0.020 inches wide. Since the drain pins also provide the thermal connection to the package, this level of connection is inadequate. The total

cross section of the

copper may be adequate to carry the

current required for the application, but it presents a large thermal impedance. Also, heat spreads in a circular fashion

from the heat source. In this case the drain pins are the heat sources when looking at heat spread on the PC board.

The pad patterns with copper spreading for the single-MOSFET TSSOP-8 (Figure 1) and dual-MOSFET TSSOP-8 (Figure 2) show the starting point for utilizing the board area available for the heat-spreading copper. To create this pattern, a plane of copper overlies the drain pins. The copper plane connects the drain pins electrically, but more importantly provides planar copper to draw heat from the drain leads and start the process of spreading the heat so it can be dissipated into the ambient air. These patterns use all the available area underneath the body for this purpose.

0.284

7.6

0.032

0.8

0.018

0.45

0.091

0.073

1.65

1.78

FIGURE 2. Dual MOSFET TSSOP-8 Pad Pattern with

Copper Spreading

0.026

0.66

0.122

3.1

Since surface-mounted packages are small, and reflow soldering is the most common way in which these are affixed to the PC board, “thermal” connections from the planar copper to the pads have not been used. Even if additional planar copper area is used, there should be no problems in the soldering process. The actual solder connections are defined by the solder mask openings. By combining the basic footprint with the copper plane on the drain pins, the solder mask generation occurs automatically.

0.284

7.6

0.032

0.8

0.018

0.45

0.073

1.78

FIGURE 1. Single MOSFET TSSOP-8 Pad

Document Number: 70738 17-Dec-03

0.118

3.54

Pattern with Copper Spreading

0.026

0.66

0.122

3.1

A final item to keep in mind is the width of the power traces. The absolute minimum power trace width must be determined by the amount of current it has to carry. For thermal reasons, this minimum width should be at least 0.020 inches. The use of wide traces connected to the drain plane provides a low impedance path for heat to move away from the device.

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Page 10

RECOMMENDED MINIMUM PADS FOR TSSOP-8

0.092

(2.337)

Application Note 826

Vishay Siliconix

0.026

(0.660)

Return to Index

0.262 (6.655)

0.014

(0.356)

Recommended Minimum Pads

Dimensions in Inches/(mm)

0.182 (4.623)

0.040 (1.016)

0.012

(0.305)

APPLICATION NOTE

Document Number: 72611 www.vishay.com Revision: 21-Jan-08 27

Page 11

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Vishay

Disclaimer

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Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special, consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular purpose, non-infringement and merchantability.

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Document Number: 91000 www.vishay.com Revision: 11-Mar-11 1