Page 1
Si5018
SiPHY™ OC-48/STM-16 C
LOCK AND DATA RECOVERY
Features
Complete high speed, low power, CDR solution includes the following:
!
Supports OC-48 /STM-16 & FEC
!
Low Power—270 mW
(TYP OC-48)
!
Small Footprint: 4 mm x 4 mm
!
DSPLL™ Eliminates External
Loop Filter Components
!
3.3 V Tolerant Control Inputs
!
Exceeds All SONET/SDH Jitter
Specifications
!
Jitter Generation
3.0 mUI
!
Device Power Down
!
Loss-of-Lock Indicator
!
Single 2.5 V Supply
RMS
(TYP)
Applications
!
SONET/SDH/ATM Routers
!
Add/Drop Multiplexers
!
Digital Cross Connects
!
SONET/SDH Test Equipment
!
Optical Transceiver Modules
!
SONET/SDH Regenerators
!
Board Level Serial Links
Description
The Si5018 is a fully integrated low-p ower clock and d ata recovery (CDR)
IC designed for high-speed serial communication systems. It extracts
timing information and data from a serial input at OC-48/STM-16 data
rates. In addition, suppor t for 2.7 Gbps data streams is also provided for
applications that employ forward error correction (FEC). DSPLL™
technology eliminates sensitive noise entry points thus making the PLL
less susceptible to board-level interaction and helpi ng to ensure optimal
jitter performance.
The Si5018 repres ents a new stan dard in low ji tter, low power, and small
size for high spe ed CDRs. It o perates fr om a singl e 2.5 V supply over the
industrial temperature range (–40°C to 85°C).
Ordering Information:
See page 14.
Pin Assignments
Si5018
GND
REXT
1
VDD
2
GND
3
REFCLK+
REFCLK–
4
5
6 7 8 9
LOL
Top View
VDD
IC W
Si5018
GND
GND
CLKOUT+
17181920
GND
Pad
GND
DIN+
16
10
CLKOUT–
15
14
13
12
11
DIN–
ITH
PWRDN/CAL
VDD
DOUT+
DOUT–
VDD
FEC
Functional Block Diagram
LOL
DIN+
DIN–
BUF
2
Bias
REXT
Preliminary Rev. 0.8 12/00 Copyright © 2000 by Silicon Laboratories Si5018-DS08
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
DSPLL™
Phase-Locked
Loop
2
REFCLK+
REFCLK–
Retimer
BUF
BUF
2
2
DOUT+
DOUT–
PWRDN/CAL
CLKOUT+
CLKOUT–
Page 2
Si5018
2 Preliminary Rev. 0.8
Page 3
Si5018
T
ABLE OF
C
ONTENTS
Section Page
Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
DSPLL™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Reference Clock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Forward Error Correction (FEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Lock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Pin Descriptions: Si5018 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Preliminary Rev. 0.8 3
Page 4
Si5018
Detailed Block Diagram
DIN+
DIN+
DIN–
REFCLK+
REFCLK+
REFCLK–
REXT
Detector
Detector
Detector
Bias
Bias
Bias
Generation
Generation
Generation
Phase
Phase
Phase
A/D
DSP
n
Lock
Detector
Figure 1. Detailed Block Diagram
VCO
Ca libra t io n
CLK
Divider
Retime
RetimeRetime
c
DOUT+
DOUT–
c
CLKOUT+
CLKOUT–
LOL
PWRDN/CAL
4 Preliminary Rev. 0.8
Page 5
Electrical Specifications
Table 1. Recommended Operating Conditions
Si5018
Parameter
Symbol Test Condition
Ambient Temperature T
Si5018 Supply Voltage
2
V
A
DD
1
Min
Typ
–40 25 85 °C
2.375 2.5 2.625 V
Max
1
Notes:
1. All minimum and maximum specifications are guaranteed and apply across the recommended operating
conditions. Typical values apply at nominal supply voltages and an operating temperature of 25°C unless
otherwise stated.
2. The Si5018 specifications are guaranteed when using the recommended application circuit (including
component tolerance) of Figure 5 on page 8.
V
SIGNAL+
Differential
I/Os
V
ICM,VOCM
SIGNAL–
V
IS
Single-Ended Voltage
(SIGNAL+) – (SIGNAL–)
Differential
Voltage Swing
VID,VOD (V
= 2VIS)
ID
Differential Peak-to-Peak Voltage
t
Unit
DOUT
CLKOUT
DOUT,
CLKOUT
Figure 2. Differential Voltage Measurement (DI N, REFCLK, DOUT, CLKOUT)
t
Cf-D
t
Cr-D
Figure 3. Clock to Data Timing
80%
20%
t
F
t
R
Figure 4. DOUT and CLKOUT Rise/Fall Times
Preliminary Rev. 0.8 5
Page 6
Si5018
Table 2. DC Characteristics
(VDD = 2.5 V ± 5%, TA = –40°C to 85°C)
Parameter Symbol Test Condition Min Typ Max Unit
Supply Current I
Power Dissipation P
Common Mode Input Voltage (DIN, REFCLK) V
Single Ended Input Voltage (DIN, REFCLK) V
Differential Input Voltage Swing (DIN, REFCLK) V
Input Impedance (DIN, REFCLK) R
Differen tial Output Voltage Swing
V
(DOUT)
Differen tial Output Voltage Swing
V
(CLKOUT)
Output Common Mode Voltage
V
(DOUT,CLKOUT)
Output Impedance (DOUT,CLKOUT) R
Output Short to GND (DOUT,CLKOUT) I
Output Short to V
(DOUT,CLKOUT) I
DD
SC(–)
SC(+)
Input Voltage Low (LVTTL Inputs) V
Input Voltage High (LVTTL Inputs) V
Input Low Current (LVTTL Inputs) I
Input High Current (LVTTL Inputs) I
Output Voltage Low (L VTTL Outputs) V
Output Voltage High (LVTTL Outputs) V
Input Impedance (LVTTL Inputs) R
PWRDN/CAL Leakage Current I
PWRDNVPWRDN
DD
D
ICM
IS
ID
IN
OD
OD
OCM
OUT
IL
IH
IL
IH
OL
OH
IN
varies with V
DD
See Figure 2 100 — 750 mV
See Figure 2 200 — 1500 mV
Line-to-Line 84 100 116 Ω
100 Ω Load
Line-to-Line
100 Ω Load
Line-to-Line
100 Ω Load
Line-to-Line
Single-ended 84 100 116 Ω
IO = 2 mA — — 0.4 V
IO = 2 mA 2.4 — — V
≥ 0.8 V TBD 25 TBD µA
— 108 118 mA
— 270 310 mW
—.80*VDD—V
(pk-pk)
TBD 940 TBD mV
(pk-pk)
TBD 900 TBD mV
(pk-pk)
—VDD –
—V
0.20
—25TBDmA
TBD –15 — mA
——.8 V
2.0 — — V
——10µA
——10µA
10 — — kΩ
Table 3. AC Characteristics (Clock & Data)
(VA 2.5 V ± 5%, TA = –40°C to 85°C)
Parameter Symbol Test Condition Min Typ Max Unit
Output Clock Rate f
Output Rise Time t
Output Fall Time t
Clock to Data Delay
CLK
t
Cr-D
R
F
Figure 4 — 100 TBD ps
Figure 4 — 100 TBD ps
Figure 3
FEC (2.7 GHz)
OC-48
Clock to Data Delay
t
Cf-D
Figure 3
FEC (2.7 GHz)
OC-48
Input Return Loss 100 kHz – 2.5 GHz
2.5 GHz – 4.0 GHz
6 Preliminary Rev. 0.8
2.4 — 2.7 GHz
TBD
TBD
TBD
TBD
18.7
TBD
250
255
51
50
—
—
TBD
TBD
TBD
TBD
—
—
ps
ps
dB
dB
Page 7
Si5018
Table 4. AC Characteristics (PLL Characteristics)
(VA 2.5 V ± 5%, TA = –40°C to 85°C)
Parameter Symbol Test Condition Min Typ Max Unit
Jitter Tolerance* J
TOL(P–P)
f = 600 Hz 40 TBD — UIp-p
f = 6000 Hz 4 TBD — UIp-p
f = 100 kHz 4 TBD — UIp-p
f = 1 MHz .4 TBD — UIp-p
RMS Jitter Generation
Peak-to-Peak Jitter Generation
Jitter Transfer Bandwidth
Jitter Transfer Peaking
Acquisition Time T
*
*
*
*
J
GEN(rms)
J
GEN(rms)
J
BW
J
P
AQ
with no jitter on serial data — 3.0 5.0 mUI
with no jitter on serial data — 25 55 mUI
——2.0MHz
— 0.03 0.1 dB
After falling edge of
1.45 1.5 1.7 ms
PWRDN/CAL
From the return of valid data 40 60 150 µs
Input Reference Clock Duty
C
DUTY
40 50 60 %
Cycle
Input Reference Clock Frequency
C
TOL
–100 — 100 ppm
Tolerance
Reference Clock Range 19.44 — 168.75 MHz
Frequency Difference at which
LOL TBD 600 TBD ppm
Receive PLL goes out of Lock
(REFCLK compared to the
divided down VCO clock)
Frequency Difference at which
LOCK TBD 300 TBD ppm
Receive PLL goes into Lock
(REFCLK compared to the
divided down VCO clock)
*Note: Bellcore specifications: GR-253-CORE, Issue 2, December 1995. Using PRBS 223– 1 data pattern.
Preliminary Rev. 0.8 7
Page 8
Si5018
Table 5. Absolute Maximum Ratings
Parameter Symbol Value Unit
DC Supply Voltage V
LVTTL Input Voltage V
Differential Input Voltages V
DD
DIG
DIF
–0.5 to 2.8 V
–0.3 to 3.6 V
–0.3 to (VDD+ 0.3) V
Maximum Current any output PIN ±50 mA
Operating Junction Temperature T
Storage Temperature Range T
JCT
STG
–55 to 150 °C
–55 to 150 °C
Lead Temperature (soldering 10 seconds) 300 °C
ESD HBM Tolerance (100pf, 1.5 kΩ)1kV
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Table 6. Thermal Characteristics
Parameter Symbol Test Condition Value Unit
Thermal Resistance Junction to Ambient ϕ
Power Down
JA
Still Air 38 °C/W
Loss-of-Lock
Indicator
High Speed
Serial Input
System
Reference
Clock
LOL
DIN+
DIN–
PWRDN/CAL
DOUT+
DOUT–
Si5018
REFCLK+
REFCLK–
ΩΩΩΩ
10 k
(1%)
(1%)
(1%)(1%)
REXT
VDD
CLKOUT+
CLKOUT–
VDD
µµµµ
0.1
2200pF
20pF
GND
F
Figure 5. Si5018 Typical Application Circuit
Recovered
Data
Recovered
Clock
8 Preliminary Rev. 0.8
Page 9
Functional Description
Si5018
The Si5018 utilizes a phase-locked loop (PLL) to
recover a clock s ynchronous to the input data stream .
This clock is used to retime the data, and both the
recovered clock and data are output syn chronously via
current mode logic (CML) drivers. Optimal jitter
performance is obtained by using Silicon Laboratories'
DSPLL™ technology to eliminate the no ise entry poi nts
caused by external PLL loop filter components.
DSPLL
The phase-locked loop structure (shown in Figure 1 o n
page 4) utilizes Silicon Laboratories' DSPLL™
technology to elimin ate the need for external l oop filter
components found in traditional PLL implementations.
This is achieved by using a digital signal processing
(DSP) algorithm to replace the loop filter commonly
found in analog PLL designs . This algorithm pro cesses
the phase detector error term and generates a digital
control value to adjust the frequency of the voltage
controlled oscilla tor (VCO). Bec ause external loo p filter
components are not required, sensitive noise entry
points are eliminated thus making the DSPLL less
susceptible to board-level noise sources that make
SONET/SDH jitter compliance difficult to attain.
™
PLL Self-Calibration
The Si5018 achieves optimal jitter performance by
using self-calibration circuitry to set the loop gain
parameters within the DSPLL. For the self-calibration
circuitry to operate correctly, the power supply voltage
must exceed 2.25 V when calibration occurs. For best
performance, the user should force a self-calibration
once the supply has stabilized on power-up.
A self-calibration can be initiat ed by forcing a high-tolow transition on the power-down control input,
PWRDN/CAL, while a vali d reference clock is supplie d
to the REFCLK input. The PWRDN/CAL input should be
held high at least 1 µS before transitioning low to
guarantee a self-cal ibration. Sev eral applica tion circu its
that could be used to initiate a power- on self-cal ibration
are provided in Silico n Laboratories’ “ AN42: Controlling
the Si5018/20 Self-Calibration.”
Reference Clock Detect
The Si5018 uses the referen ce clock to ce nter the VCO
output frequency at the OC-48/S TM-16 data rate. The
device will self con figure for o peration wi th one of thr ee
reference clock frequencies. This eliminates the need to
externally configure the device to operate with a
particular reference clock.
The reference clock centers the VCO for a nominal
output between 2.488 GHz & 2.7 GHz. The VCO
frequency is centered at 16, 32, or 128 times the
reference clock frequency. Detection circuitry
continuously monitors the reference clock input to
determine whether the dev ice should be configured for
a reference clock that is 1/16, 1/32, or 1/128 the
nominal VCO output. Approximate reference clock
frequencies are given in Table 7.
Table 7. Typical REFCLK Frequencies
OC-48/
STM-16
(2.488 GHz)
19.44 MHz 20.83 MHz 128
77.76 MHz 83.31 MHz 32
155.52 MHz 166.63 MHz 16
OC-48/
STM-16 w/
15/14 FEC
(2.666 GHz)
Ratio of
VCO to
REFCLK
Forward Error Correction (FEC)
The Si5018 supports FEC in SONET OC-48 (SDH
STM-16) application s for data rates up to 2.7 Gbps. In
FEC applications, the appropriate reference clock
frequency is determined by dividing the input data rate
by 16, 32, or 128. For example, if an FEC cod e is used
that produces a 2.7 Gbps data rate, the required
reference clock would be 168.75 MHz, 84.375 MHz, or
21.09 MHz.
Lock Detect
The Si5018 provides lock-detect circuitry th at indicates
whether the PLL has ac hieved frequency lock with th e
incoming data. The ci rcuit compare s the frequency of a
divided down version of the recovered clock with the
frequency of the supplied referen ce clock (REFCLK). If
the recovered clo ck freque ncy devia tes fro m that of the
reference clock by the amount specified in Table 4 on
page 7, the PLL is decla red ou t of lock, a nd the lo ss-oflock (LOL) pin is asserted “high.” In this state, the
DSPLL will periodically try to reacquire lock with the
incoming data stream. During reacquisition, the
recovered clock, CLKOUT, will drift over a ±600 ppm
range relative to the su pplied reference c lock. Th e LOL
output will remain asserted until the recovered clock
frequency is within the REFCLK frequency by the
amount specified in Table 4.
Note: LOL is not asserted during PWRDN/CAL.
Preliminary Rev. 0.8 9
Page 10
Si5018
PLL Performance
The PLL implementation used in the Si5018 is fully
compliant with the jitter specifications proposed for
SONET/SDH equipment by Bellcore GR-253-CORE,
Issue 2, December 1995 and ITU-T G.958.
Jitter Tolerance
The Si5018’s tolerance to input jitter exceeds that of the
Bellcore/ITU mask shown in Figure 6. This mask
defines the level of peak-to-peak sinusoid jitter that
must be tolerated when applied to the differential data
input of the device.
Jitter Transfer
The Si5018 is ful ly co mplian t with the r elevant Be llcore /
ITU specifications related to SONET/SD H jitter transfer.
Jitter transfer is defined as the ratio of output signal jitter
to input signal jitter as a functi on of ji tter freq uency (see
Figure 7). These m easur em ents are ma de wi th an i npu t
test signal that is degraded wi th sinusoidal jitter whose
magnitude is defined by the mask in Figure 6.
Jitter Generation
The Si5018 exceeds al l relevant specifications for jitter
generation proposed for SONET/SDH equipment. The
jitter generation specification defines the amount of jitter
that may be presen t on the recovered clock and data
outputs when a jitter free input signal is provide d. The
Si5018 generates less than 3.0 mUI
presented with jitter free input data.
Sinusoidal
Input
Jitter (UI p-p)
20dB/Decade Slope
15
1.5
0.15
of jitter when
RMS
Jitter
Transfer
0.1 dB
Acceptable
Range
Fc
Frequency
20dB / Decade
Slope
SONET
Data RateFc(kHz)
OC-48 2000
Figure 7. Jitter Transfer Specification
Power Down
The Si5018 provides a power d own pin, PWRDN/CAL,
that disables the output drivers (DOUT, CLKOUT).
When the PWRDN/CAL pin is driven “high”, the pos itiv e
and negative terminals of CLKOUT and DOUT are each
tied to VDD through 100 Ω on-chip resistors. This
feature is useful in reducing power consumption in
applications that employ redundant serial channels.
When PWRDN/CAL is released (set to “low”) the digital
logic resets to a kn own initia l conditi on, reca librate s the
DSPLL, and will begin to lock to the data stream.
Device Grounding
The Si5018 uses the GND pad on the bottom of the 20pin micro leaded package (MLP) for device ground. This
pad should be connected di rectly to the analog supply
ground. See Figures 10 and 11 for the ground (GND)
pad location.
f0 f1 f2 f3 ft
Frequency
Bias Generation Circuitry
The Si5018 makes use of an external resistor to set
internal bias currents. The external resistor allows
SONET
Data RateF0(Hz)F1(Hz)F2(Hz)F3(kHz)Ft(kHz)
OC-48 10 600 6000 100 1000
precise generation of bias currents which significantly
reduces power consumption versus traditional
implementations tha t use an internal resistor. The bias
generation circuitry requires a 10 kΩ (1%) resistor
Figure 6. Jitter Tolerance Specification
10 Preliminary Rev. 0.8
connected between REXT and GND.
Page 11
Si5018
Differential Input Circui try
The Si5018 provides differential inputs for both the high speed data (DIN) and the reference clock (REFCLK)
inputs. An example te rmination for thes e inputs is show n in Figure 8. In applications wh ere direct DC cou pling is
possible, the 0.1 µF capacitors may be omitted. T he DIN an d REFC L K in put am pl ifier s requ ir e an inpu t si gna l wit h
a minimum differential peak-to-peak voltage listed in Table 2 on page 6.
DIN+,
DIN–,
Si5018
2.5 kΩΩΩΩ
VDD
2.5 kΩΩΩΩ10 kΩΩΩΩ
10 kΩΩΩΩ
GND
102 ΩΩΩΩ
Differential Driver
0.1µµµµF
0.1µµµµF
Zo = 50 ΩΩΩΩ
Zo = 50 ΩΩΩΩ
REFCLK+
REFCLK–
Figure 8. Input Termination for DIN and REFCLK (AC Coupled)
Differential Output Circuitry
The Si5018 utilizes a current mode logic (CML) architecture to output both the recovered clock (CLKOUT) and data
(DOUT). An example of output termination with AC coupling is shown in Figure 9. In applications in which direct DC
coupling is possible, the 0.1 µF capacitors may be omitted. The differential peak-to-peak voltage swing of the CML
architecture is listed in Table 2 on page 6.
Si5018
100 ΩΩΩΩ
100 ΩΩΩΩ
VDD
VDD
DOUT+,
CLKOUT+
DOUT–,
CLKOUT–
0.1 µµµµF
0.1 µµµµF
Zo = 50 ΩΩΩΩ
Zo = 50 ΩΩΩΩ
VDD
50 ΩΩΩΩ
50 ΩΩΩΩ
VDD
Figure 9. Output Termination for DOUT and CLKOUT (AC Coupled)
Preliminary Rev. 0.8 11
Page 12
Si5018
Pin Descriptions: Si5018
GND
GND
GND
CLKOUT+
CLKOUT–
17181920
16
10
15
14
13
12
11
DIN–
PWRDN/CAL
VDD
DOUT+
DOUT–
VDD
REXT
1
VDD
GND
REFCLK+
REFCLK–
2
3
4
5
GND
Pad
6 7 8 9
LOL
VDD
GND
DIN+
Top View
Figure 10. Si5018 Pin Configuration
Table 8. Si5018 Pin Descriptions
Pin # Pin Name I/O Signal Level Description
1REXT External Bias Resistor.
This resistor is used by onboard circuitry to establish bias currents within the device. This pin must
be connected to GND through a 10 kΩ (1%) resis-
tor.
4, 5 REFCLK+,
REFCLK–
I See Table2 Differential Reference Clock.
The reference clock sets the initial operating frequency used by the onboard PLL for clock and data
recovery. Additionally , the reference clock is used to
derive the clock output when no data is present.
6LOLOLVTTLLoss of Lock.
This output is driven high when the recovered clock
frequency deviates from the reference clock by the
amount specified in Table 4 on page 7.
9, 10 DIN+, DIN– I See Table 2 Differential Data Input.
Clock and data are recovered from the differential
signal present on these pins.
12, 13 DOUT–,
DOUT+
OCMLDifferential Data Output.
The data output signal is a retimed version of the
data recovered from the signal present on DIN. It is
phase aligned with CLKOUT and is updated on the
rising edge of CLKOUT.
12 Preliminary Rev. 0.8
Page 13
Table 8. Si5018 Pin Descriptions (Continued)
Pin # Pin Name I/O Signal Level Description
Si5018
15 PWRDN/CAL I LVTTL
16, 17 CLKOUT–,
CLKOUT+
2, 7, 11, 14 VDD 2.5 V Supply Voltage.
3, 8, 18, 19,
20, and
GND Pad
GND GND Supply Ground.
OCMLDifferential Clock Output.
Power Down.
To shut down the high-speed outputs and reduce
power consumption, hold this pin high. For normal
operation, hold this pin low.
Calibration.
To initiate an internal self-calibration, force a highto-low transition on this pin. (See "PLL Self-Calibration‚" on page 9.)
Note: This input has a weak internal pulldown.
The output clock is recovered from the data signal
present on DIN. In the absence of data, the output
clock is derived from REFCLK.
Nominally 2.5 V.
Nominally 0.0 V . The GND pad found on the bottom
of the 20-pin micro leaded package (see Figure 11)
must be connected directly to supply ground.
Preliminary Rev. 0.8 13
Page 14
Si5018
Ordering Guide
Table 9. Ordering Guide
Part Number Package Temperature
Si5018-BM 20 -pin MLP –40°C to 85°C
14 Preliminary Rev. 0.8
Page 15
Si5018
Package Outline
Figure 11 illustrates the packag e details f or the Si5018 . Table 10 lists th e values for the dimens ions shown in the
illustration.
56
0.50 DIA.
TOP VIEW
A
1
2
3
D
D1
N
D1/2
2X
D/2
A
C0.25
E1/2 E/2
E1 E
0.252XB
C
BOTTOM VIEW
10
0.05
A
A2
C
A1
A3
4X P
R
4X P
4X Q
4
0.10 BAMC
b
D2
D2/2
8.
N
1
2
(Ne-1)X e
3
E2
REF.
0.20
C
2X
FOR ODD TERMINAL/SIDE FOR EVEN TERMINAL/SIDE
B
2X
e
AC0.20
C
L
TERMINAL TIP
CC
C
L
4
e
Figure 11. 20-pin Micro Leaded Package (MLP)
Table 10. Package Diagram Dimensions
B
b
SECTION "C-C"
SCALE: NONE
L
0
C
SEATING
11
A1
NOTES:
1.
DIE THICKNESS ALLOW ABLE IS 0.305mm MAXIMUM(.012 INCHES MAXIMUM)
DIMENSIONING & TOLERANCES C ON FOR M T O ASME Y14.5M. - 1994.
2.
N IS THE NUMBER OF TERMINALS.
3.
Nd IS THE NUMBER OF TERMINALS IN X-DIRECTION &
Ne IS THE NUMBER OF TERMINALS IN Y-DIRECTION.
4.
DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED
PLANE
BETWEEN 0.20 AND 0.25mm FROM T ERM INAL TIP.
5.
THE PIN #1 IDENTIFIER MUST BE EXISTED ON THE TOP SURF ACE O F TH E
PACKAGE BY USING INDENTATION MARK O R OT HER FEAT URE O F PAC KAG E BOD Y.
EXACT SHAPE AND SIZE OF THIS FEATURE IS OPTIONAL.
6.
7. ALL DIMENSIONS ARE IN MILLIMETERS.
THE SHAPE SHOWN ON FOU R CO RN ERS AR E NO T AC TUAL I/O.
8.
PACKAGE W AR PAG E MAX 0.05mm.9.
APPLIED FOR EXPOSED PAD AND T ERMINALS.
10.
EXCLUDE EMBEDDING PART O F EXPO SED
PAD FROM MEASURING.
APPLIED ONLY FOR TERM INALS.
11.
e
(Nd-1)Xe
REF.
E2/2
Symbol Millimeters Symbol Millimeters
Min Nom Max Min Nom Max
A — 0.85 1.00 E1 3.75 BSC
A1 0.00 0.01 0.05 E2 1.95 2.10 2.25
A2 — 0.65 0.80 N 20
A3 0.20 REF Nd 5
b 0.23 0.28 0.35 Ne 5
D 4.00 BSC L 0.50 0. 60 0.75
D1 3.75 BSC P 0.24 0.42 0.60
D2 1.95 2.10 2.25 Q 0.30 0.40 0.65
e 0.50 BSC R 0.13 0. 17 0.23
E 4.00 BSC θ ——12°
Preliminary Rev. 0.8 15
Page 16
Si5018
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16 Preliminary Rev. 0.8
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