Datasheet si4812bdy Datasheet

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Si4812BDY

Vishay Siliconix

N-Channel 30-V (D-S) MOSFET with Schottky Diode

MOSFET PRODUCT SUMMARY

VDS (V) R

0.016 at V

0.021 at V

(Ω)I

DS(on)

= 10 V

= 4.5 V

(A)

9.5

7.7

FEATURES

• Halogen-free According to IEC 61249-2-21 Available

• LITTLE FOOT

• 100 % R

Plus Power MOSFET

Tested

SCHOTTKY PRODUCT SUMMARY

(V)

VDS (V)

Diode Forward Voltage

(A)

30 0.50 V at 1.0 A 1.4

Ordering Information:

SO-8

T op V i e w

Si4812BDY-T1-E3 (Lead (Pb)-free) Si4812BDY-T1-GE3 (Lead (Pb)-free and Halogen-free)

N-channel MOSFET

Schottky Diode

ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted

Limit

Parameter Symbol

Drain-Source Voltage (MOSFET) Reverse Voltage (Schottky) 30 Gate-Source Voltage (MOSFET)

TA = 25 °C

Continuous Drain Current (T

= 150 °C) (MOSFET)

a, b

= 70 °C 7.7 5.9

Pulsed Drain Current (MOSFET)

Continuous Source Current (MOSFET Diode Conduction)

a, b

Average Forward Current (Schottky) Pulsed Forward Current (Schottky) Single Pulse Avalanche Current Avalanche Energy

Maximum Power Dissipation (MOSFET)

Maximum Power Dissipation (Schottky)

a, b

L = 0.1 mH

TA = 25 °C T

= 70 °C 1.6 0.9

TA = 25 °C 2.0 1.2 T

= 70 °C 1.3 0.8

Operating Junction and Storage Temperature Range

, T

stg

10 s Steady State

± 20

9.5 7.3

2.1 1.2

1.4 0.8 30

1.25 mJ

2.5 1.4

- 55 to 150 °C

Unit

THERMAL RESISTANCE RATINGS

Parameter Device Symbol Typical Maximum Unit

Maximum Junction-to-Ambient (t ≤ 10 s)

Maximum Junction-to-Ambient (t = Steady State)

Maximum Junction-to-Foot (t = Steady State)

Notes: a. Surface Mounted on FR4 board. b. t ≤ 10 s.

Document Number: 73038 S-83039-Rev. D, 29-Dec-08

MOSFET

Schottky 50 60

MOSFET 72 90

thJA

Schottky 85 100

MOSFET

Schottky 24 30

thJF

40 50

°C/W

18 23

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Page 2

Si4812BDY

Vishay Siliconix

MOSFET AND SCHOTTKY SPECIFICATIONS TJ = 25 °C, unless otherwise noted

Parameter Symbol Test Conditions Min. Typ. Max. Unit

Static

Gate Threshold Voltage

Gate-Body Leakage

Zero Gate Voltage Drain Current (MOSFET and Schottky)

On-State Drain Current

Drain-Source On-State Resistance

Forward Transconductance

Schottky Diode Forward Voltage

Dynamic

Total Gate Charge

Gate-Drain Charge

Gate Resistance

Tur n -O n De l ay Ti m e

Rise Time

Turn-Off Delay Time

Fall Time

Source-Drain Reverse Recovery Time

GS(th)

GSS

DSS

D(on)

DS(on)

d(on)

d(off)

Notes: a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %. b. Guaranteed by design, not subject to production testing.

= VGS, ID = 250 µA

VDS = 0 V, VGS = ± 20 V

= 30 V, V

≥ 5 V, V

= 10 V, ID = 9.5 A

= 4.5 V, ID = 7.7 A

= 0 V

= 0 V, TJ = 100 °C

= 0 V, TJ = 125 °C

= 10 V

VDS = 15 V, ID = 9.5 A

IS = 1.0 A, V

= 1.0 A, V

= 15 V, V

= 15 V, RL = 15 Ω

≅ 1 A, V

GEN

= 0 V

= 0 V, TJ = 125 °C

= 5 V, ID = 9.5 A

= 10 V, Rg = 6 Ω

IF = 1.0 A, dI/dt = 100 A/µs

13V

± 100 nA

0.004 0.100

0.7 10

3.0 20

20 A

0.013 0.016

0.0165 0.021

45 S

0.45 0.50

0.33 0.42

8.5 13

nCGate-Source Charge

2.6

0.3 0.7 1.1 Ω

15 25

13 20

20 30

815

22 35

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

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Document Number: 73038

S-83039-Rev. D, 29-Dec-08

Page 3

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

Si4812BDY

Vishay Siliconix

- Drain Current (A)I

- On-Resistance (Ω)R

DS(on)

012345

VGS = 10 thru 4 V

3 V

VDS - Drain-to-Source Voltage (V)

Output Characteristics

0.030

0.025

0.020

0.015

0.010

0.005

VGS = 4.5 V

VGS = 10 V

- Drain Current (A)I

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

VGS - Gate-to-Source Voltage (V)

TC = 125 °C

25 °C

Transfer Characteristics

1300

1040

780

520

C - Capacitance (pF)

260

oss

rss

iss

- 55 °C

0.000 0 102030405060

On-Resistance vs. Drain Current

- Gate-to-Source Voltage (V)

VDS = 15 V

= 9.5 A

0246810

Document Number: 73038 S-83039-Rev. D, 29-Dec-08

ID - Drain Current (A)

Qg - Total Gate Charge (nC)

Gate Charge

0 5 10 15 20 25 30

1.6

1.4

1.2

- On-Resistance

1.0

(Normalized)

DS(on)

0.8

0.6

- 50 - 25 0 25 50 75 100 125 150

VDS - Drain-to-Source Voltage (V)

Capacitance

VGS = 10 V

= 9.5 A

- Junction Temperature (°C)

On-Resistance vs. Junction Temperature

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Page 4

Si4812BDY

Vishay Siliconix

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

0.05

- Source Current (A)I

- Reverse Current (mA)I

0.0001

0.1

0.0 0.2 0.4 0.6 0.8 1.0 1.2

TJ = 150 °C

TJ = 25 °C

- Source-to-Drain Voltage (V)

Source-Drain Diode Forward Voltage

0.1

0.01

0.001

30 V

20 V

10 V

- On-Resistance (Ω)R

DS(on)

Power (W)

0.04

0.03

0.02

0.01

0.00 0246810

VGS - Gate-to-Source Voltage (V)

ID = 9.5 A

On-Resistance vs. Gate-to-Source Voltage

0.00001

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0 255075100

TJ - Junction Temperature (°C)

Reverse Current (Schottky)

100

- Drain Current (A)

0.1

0.01

0.1 1 10 100

DS(on)

is specified

125 150

Limited by R

DS(on)*

TC = 25 °C

Single Pulse

VDS- Drain-to-Source Voltage (V)

> minimum VGSat which R

Safe Operating Area, Junction-to-Case

6001001010.10.01

Time (s)

Single Pulse Power (MOSFET)

1 ms

10 ms

100 ms

1 s 10 s

Document Number: 73038

S-83039-Rev. D, 29-Dec-08

Page 5

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

Duty Cycle = 0.5

0.2

0.1

0.01

-4

0.05

0.02

Single Pulse

-3

-2

-1

Square Wave Pulse Duration (s)

Normalized Thermal Transient Impedance, Junction-to-Ambient (MOSFET)

Thermal Impedance

Normalized Effective Transient

Si4812BDY

Vishay Siliconix

Notes:

thJA

= 72 °C/W

(t)

1. Duty Cycle, D =

2. Per Unit Base = R

3. T

- TA = PDMZ

4. Surface Mounted

10 100 600

0.1

Thermal Impedance

Normalized Effective Transient

0.01

-4

Duty Cycle = 0.5

0.2

0.1

0.05

0.02

Single Pulse

Notes:

1. Duty Cycle, D =

2. Per Unit Base = R

- TA = PDMZ

3. T

4. Surface Mounted

-3

-2

-1

11030

Square Wave Pulse Duration (s)

Normalized Thermal Transient Impedance, Junction-to-Ambient (Schottky)

= 85 °C/W

thJA

(t)

thJA

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?73038

Document Number: 73038

www.vishay.com

S-83039-Rev. D, 29-Dec-08

Page 6

SOIC (NARROW): 8-LEAD

JEDEC Part Number: MS-012

Package Information

Vishay Siliconix

DIM

A 1.35 1.75 0.053 0.069

B 0.35 0.51 0.014 0.020

C 0.19 0.25 0.0075 0.010

D 4.80 5.00 0.189 0.196

E 3.80 4.00 0.150 0.157

e 1.27 BSC 0.050 BSC

H 5.80 6.20 0.228 0.244

h 0.25 0.50 0.010 0.020

L 0.50 0.93 0.020 0.037

q0°8°0°8°

S 0.44 0.64 0.018 0.026

ECN: C-06527-Rev. I, 11-Sep-06 DWG: 5498

0.25 mm (Gage Plane)

h x 45

MILLIMETERS INCHES

Min Max Min Max

0.10 0.20 0.004 0.008

All Leads

0.101 mm

0.004"

Document Number: 71192 11-Sep-06

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Page 7

VISHAY SILICONIX

TrenchFET® Power MOSFETs

Application Note 808

Mounting LITTLE FOOT®, SO-8 Power MOSFETs

Wharton McDaniel Surface-mounted LITTLE FOOT power MOSFETs use

integrated circuit and small-signal packages which have been been modified to provide the heat transfer capabilities required by power devices. Leadframe materials and

0.050

1.27

design, molding compounds, and die attach materials have been changed, while the footprint of the packages remains the same.

See Application Note 826, Recommended Minimum Pad

Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs, (http://www.vishay.com/ppg?72286), for the

0.027

0.69

0.07

1.98

Figure 2. Dual MOSFET SO-8 Pad Pattern

basis of the pad design for a LITTLE FOOT SO-8 power MOSFET. In converting this recommended minimum pad to the pad set for a power MOSFET, designers must make two connections: an electrical connection and a thermal connection, to draw heat away from the package.

In the case of the SO-8 package, the thermal connections are very simple. Pins 5, 6, 7, and 8 are the drain of the MOSFET for a single MOSFET package and are connected together. In a dual package, pins 5 and 6 are one drain, and pins 7 and 8 are the other drain. For a small-signal device or integrated circuit, typical connections would be made with traces that are 0.020 inches wide. Since the drain pins serve the additional function of providing the thermal connection to the package, this level of connection is inadequate. The

The minimum recommended pad patterns for the single-MOSFET SO-8 with copper spreading (Figure 1) and dual-MOSFET SO-8 with copper spreading (Figure 2) show the starting point for utilizing the board area available for the heat-spreading copper. To create this pattern, a plane of copper overlies the drain pins. The copper plane connects the drain pins electrically, but more importantly provides planar copper to draw heat from the drain leads and start the process of spreading the heat so it can be dissipated into the ambient air. These patterns use all the available area underneath the body for this purpose.

total cross section of the copper may be adequate to carry the current required for the application, but it presents a large thermal impedance. Also, heat spreads in a circular fashion from the heat source. In this case the drain pins are the heat sources when looking at heat spread on the PC board.

Since surface-mounted packages are small, and reflow soldering is the most common way in which these are affixed to the PC board, “thermal” connections from the planar copper to the pads have not been used. Even if additional planar copper area is used, there should be no problems in the soldering process. The actual solder

0.288

7.3

connections are defined by the solder mask openings. By combining the basic footprint with the copper plane on the

0.050

1.27

0.027

0.69

0.078

1.98

0.2

5.07

0.196

5.0

Figure 1. Single MOSFET SO-8 Pad

Pattern With Copper Spreading

Document Number: 70740 www.vishay.com Revision: 18-Jun-07 1

drain pins, the solder mask generation occurs automatically.

A final item to keep in mind is the width of the power traces. The absolute minimum power trace width must be determined by the amount of current it has to carry. For thermal reasons, this minimum width should be at least

0.020 inches. The use of wide traces connected to the drain plane provides a low impedance path for heat to move away from the device.

0.288

7.3

0.2

5.07

With Copper Spreading

0.088

2.25

0.088

2.25

APPLICATION NOTE

Page 8

Application Note 826

Vishay Siliconix

RECOMMENDED MINIMUM PADS FOR SO-8

0.172

(4.369)

0.028

(0.711)

Return to Index

0.022

(0.559)

0.246 (6.248)

Recommended Minimum Pads

Dimensions in Inches/(mm)

0.050

(1.270)

0.152

0.047

(3.861)

(1.194)

APPLICATION NOTE

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Page 9

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Vishay

Disclaimer

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Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special, consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular purpose, non-infringement and merchantability.

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Document Number: 91000 www.vishay.com Revision: 11-Mar-11 1