Datasheet si4544dy Datasheet

Page 1
N- and P-Channel 30-V (D-S) MOSFET
Si4544DY
Vishay Siliconix
PRODUCT SUMMARY
VDS (V) R
N-Channel 30
P-Channel - 30
0.035 at V
0.050 at V
0.045 at V
0.090 at V
SO-8
S
1
1
G
2
1
S
3
2
G
4
2
Top View
Ordering Information: Si4544DY-T1-E3 (Lead (Pb)-free)
Si4544DY-T1-GE3 (Lead (Pb)-free and Halogen-free)
8
7
6
5
(Ω)I
DS(on)
= 10 V
GS
= 4.5 V
GS
= - 10 V
GS
= - 4.5 V
GS
D
D
D
D
(A)
D
± 6.5
± 5.4
± 5.7
± 4.0
FEATURES
• TrenchFET
• Compliant to RoHS Directive 2002/95/EC
®
Power MOSFETs
G
2
G
1
S
2
D
S
1
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Parameter Symbol N-Channel P-Channel Unit
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current (T
= 150 °C)
J
a
TA = 25 °C
= 70 °C
T
A
Pulsed Drain Current
Continuous Source Current (Diode Conduction)
Maximum Power Dissipation
a
a
TA = 25 °C
= 70 °C
T
A
Operating Junction and Storage Temperature Range
V
DS
V
GS
I
D
I
DM
I
S
P
D
T
, T
J
stg
30 - 30
± 20 ± 20
± 6.5 ± 5.7
± 5.4 ± 4.0
± 20 ± 20
1.7 - 1.7
2.4
1.5
- 55 to 150 °C
V
A
W
THERMAL RESISTANCE RATINGS
Parameter Symbol N- or P-Channel Unit
Maximum Junction-to-Ambient
a
Notes: a. Surface Mounted on FR4 board, t ≤ 10 s.
Document Number: 70768 S09-0868-Rev. D, 18-May-09
R
thJA
52 °C/W
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1
Page 2
Si4544DY
Vishay Siliconix
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
Parameter Symbol Test Conditions Min. Typ. Max. Unit
Static
V
= VGS, ID = 250 µA
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Current
a
Drain-Source On-State Resistance
Forward Transconductance
Diode Forward Voltage
Dynamic
b
a
a
Total Gate Charge
Gate-Source Charge
V
GS(th)
I
GSS
I
DSS
I
D(on)
a
R
DS(on)
g
fs
V
SD
Q
g
Q
gs
DS
V
= VGS, ID = - 250 µA
DS
VDS = 0 V, VGS = ± 20 V
V
= 30 V, V
DS
= - 30 V, V
V
DS
V
= 30 V, V
DS
V
DS
= - 30 V, V
V
V
V
V
GS
GS
≥ 5 V, V
V
DS
≥ - 5 V, V
DS
V
≥ 5 V, V
DS
≥ - 5 V, V
DS
V
= 10 V, ID = 6.5 A
GS
= - 10 V, ID = - 5.7 A
GS
V
= 4.5 V, ID = 5.4 A
GS
= - 4.5 V, ID = - 4.0 A
GS
VDS = 15 V, ID = 6.5 A
V
= - 15 V, ID = - 5.7 A
DS
IS = 1.7 A, V
I
= - 1.7 A, V
S
N-Channel
V
= 15 V, V
DS
= 10 V, ID = 6.5 A
GS
= 0 V
GS
= 0 V
GS
= 0 V, TJ = 55 °C
= 0 V, TJ = 55 °C
= 10 V
GS
= - 10 V
GS
= 4.5 V
GS
= - 4.5 V
GS
= 0 V
GS
= 0 V
GS
P-Channel
Gate-Drain Charge
Tur n - O n D e l ay Time
Rise Time
Turn-Off Delay Time
Fall Ti me
Source-Drain Reverse Recovery Time
Q
t
d(on)
t
d(off)
= - 15 V, V
DS
gd
V
t
r
≅ 1 A, V
I
D
DD
V
DD
≅ - 1 A, V
I
t
f
t
rr
D
IF = 1.7 A, dI/dt = 100 A/µs
I
= - 1.7 A, dI/dt = 100 A/µs
F
= - 10 V, ID = - 5.7 A
GS
N-Channel
= 15 V, RL = 15 Ω
= 10 V, Rg = 6 Ω
GEN
P-Channel
= - 15 V, RL = 15 Ω
= - 10 V, Rg = 6 Ω
GEN
V
Notes: a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %. b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
N-Ch 1.0
P-Ch - 1.0
N-Ch ± 100
P-Ch ± 100
N-Ch 1
P-Ch - 1
N-Ch 5
P-Ch - 5
N-Ch 20
P-Ch - 20
N-Ch 5
P-Ch - 5
N-Ch 0.027 0.035
P-Ch 0.036 0.045
N-Ch 0.038 0.050
P-Ch 0.060 0.090
N-Ch 15
P-Ch 9
N-Ch 0.75 1.2
P-Ch - 0.75 - 1.2
N-Ch 18 35
P-Ch 19 40
N-Ch 4.2
P-Ch 4.5
N-Ch 3.5
P-Ch 3.6
N-Ch 13 30
P-Ch 13 30
N-Ch 12 30
P-Ch 15 30
N-Ch 31 60
P-Ch 37 70
N-Ch 10 30
P-Ch 14 30
N-Ch 30 70
P-Ch 35 70
V
nA
µA
A
Ω
S
V
nC
ns
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Document Number: 70768
S09-0868-Rev. D, 18-May-09
Page 3
N-CHANNEL TYPICAL CHARACTERISTICS 25 °C unless otherwise noted
Si4544DY
Vishay Siliconix
20
VGS = 10 V thru 5 V
16
12
8
- Drain Current (A)I
D
4
0
0246810
VDS - Drain-to-Source Voltage (V)
4 V
3 V
Output Characteristics
0.06
0.05
0.04
0.03
- On-Resistance (Ω)R
0.02
DS(on)
0.01
VGS = 4.5 V
VGS = 10 V
20
16
12
8
- Drain Current (A)I
D
4
0
012345
VGS - Gate-to-Source Voltage (V)
TC = 125 °C
25 °C
- 55 °C
Transfer Characteristics
1500
C
1200
900
600
C - Capacitance (pF)
300
C
C
oss
rss
iss
0.00 048121620
On-Resistance vs. Drain Current
10
VDS = 15 V
= 6.5 A
I
D
8
6
4
- Gate-to-Source Voltage (V)
GS
2
V
0
048121620
Document Number: 70768 S09-0868-Rev. D, 18-May-09
ID - Drain Current (A)
Qg - Total Gate Charge (nC)
Gate Charge
- On-ResistanceR
DS(on)
0
0 6 12 18 24 30
VDS - Drain-to-Source Voltage (V)
Capacitance
1.8
(Normalized)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
VGS = 10 V
= 6.5 A
I
D
- 50 - 25 0 25 50 75 100 125 150
- Junction Temperature (°C)
T
J
On-Resistance vs. Junction Temperature
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Page 4
Si4544DY
Vishay Siliconix
N-CHANNEL TYPICAL CHARACTERISTICS 25 °C unless otherwise noted
20
10
TJ = 150 °C
- Source Current (A)I
S
1
0 0.2 0.4 0.6 0.8 1.0 1.2
VSD - Source-to-Drain Voltage (V)
Source-Drain Diode Forward Voltage
0.6
0.3
0.0
Variance (V)V
- 0.3
GS(th)
ID = 250 µA
TJ = 25 °C
0.12
0.09
ID = 6.5 A
0.06
- On-Resistance (Ω)R
DS(on)
0.03
0.00 13579
VGS - Gate-to-Source Voltage (V)
On-Resistance vs. Gate-to-Source Voltage
40
32
24
Power (W)
16
- 0.6
- 0.9
- 50 - 25 0 25 50 75 100 125 150
TJ - Temperature (°C)
Threshold Voltage
2
1
Duty Cycle = 0.5
0.2
0.1
0.1
Thermal Impedance
Normalized Effective Transient
0.05
0.02
Single Pulse
0.01
-4
10
-3
10
Normalized Thermal Transient Impedance, Junction-to-Ambient
-2
10
Square Wave Pulse Duration (s)
8
0
0.01 0.1 1 10 30
Time (s)
Single Pulse Power
Notes:
P
DM
t
1
t
2
t
thJA
t
thJA
1
2
= 52 °C/W
(t)
1. Duty Cycle, D =
2. Per Unit Base = R
3. T
- TA = PDMZ
JM
4. Surface Mounted
-1
10
11030
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Document Number: 70768
S09-0868-Rev. D, 18-May-09
Page 5
P-CHANNEL TYPICAL CHARACTERISTICS 25 °C unless otherwise noted
20
VGS = 10 V thru 5 V
16
20
16
Si4544DY
Vishay Siliconix
12
8
- Drain Current (A)I
D
4
0
0246810
- Drain-to-Source Voltage (V)
V
DS
4 V
Output Characteristics
0.16
0.12
- On-Resistance (Ω)R
DS(on)
0.08
0.04
0.00
VGS = 4.5 V
VGS = 10 V
048121620
ID - Drain Current (A)
On-Resistance vs. Drain Current
3 V
12
8
- Drain Current (A)I
D
4
0
012345
VGS - Gate-to-Source Voltage (V)
TC = 125 °C
25 °C
- 55 °C
Transfer Characteristics
1500
C
1200
900
600
C - Capacitance (pF)
300
C
rss
0
0 6 12 18 24 30
iss
C
oss
VDS - Drain-to-Source Voltage (V)
Capacitance
10
VDS = 10 V
= 5.7 A
I
D
048121620
- Gate-to-Source Voltage (V)
V
GS
8
6
4
2
0
Document Number: 70768 S09-0868-Rev. D, 18-May-09
Qg - Total Gate Charge (nC)
Gate Charge
- On-Resistance R
DS(on)
1.8
VGS = 10 V
= 5.7 A
I
D
- 50 - 25 0 25 50 75 100 125 150
- Junction Temperature (°C)
T
J
(Normalized)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
On-Resistance vs. Junction Temperature
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5
Page 6
Si4544DY
Vishay Siliconix
P-CHANNEL TYPICAL CHARACTERISTICS 25 °C unless otherwise noted
20
0.20
- Source Current (A)I
S
Variance (V)V
GS(th)
10
TJ = 150 °C
1
0 0.25 0.50 0.75 1.00
VSD - Source-to-Drain Voltage (V)
Source-Drain Diode Forward Voltage
0.8
0.6
0.4
0.2
0.0
- 0.2
- 0.4
ID = 250 µA
TJ = 25 °C
1.25 1.50
- On-Resistance (Ω)R
DS(on)
Power (W)
0.16
0.12
0.08
ID = 5.7 A
0.04
0.00 0246810
VGS - Gate-to-Source Voltage (V)
On-Resistance vs. Junction Temperature
40
30
20
10
- 0.6
- 50 - 25 0 25 50 75 100 125 150
- Temperature (°C)
T
J
Threshold Voltage
0
0.01
0.1
1
Time (s)
Single Pulse Power
10 30
2
1
Duty Cycle = 0.5
Notes:
P
DM
t
1
t
- TA = PDMZ
JM
2
1. Duty Cycle, D =
2. Per Unit Base = R
3. T
4. Surface Mounted
thJA
thJA
t
1
t
2
= 52 °C/W
(t)
0.1
Thermal Impedance
Normalized Effective Transient
0.2
0.1
0.05
0.02
Single Pulse
0.01
-4
10
-3
10
-2
10
-1
10
11030
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?70768
.
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Document Number: 70768
S09-0868-Rev. D, 18-May-09
Page 7
SOIC (NARROW): 8-LEAD
JEDEC Part Number: MS-012
Package Information
Vishay Siliconix
D
e
BA
1
DIM
A 1.35 1.75 0.053 0.069
A
1
B 0.35 0.51 0.014 0.020
C 0.19 0.25 0.0075 0.010
D 4.80 5.00 0.189 0.196
E 3.80 4.00 0.150 0.157
e 1.27 BSC 0.050 BSC
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.50 0.93 0.020 0.037
q0°8°0°8°
S 0.44 0.64 0.018 0.026
ECN: C-06527-Rev. I, 11-Sep-06 DWG: 5498
8
1
0.25 mm (Gage Plane)
A
6
7
2
5
HE
3
4
S
h x 45
C
L
MILLIMETERS INCHES
Min Max Min Max
0.10 0.20 0.004 0.008
All Leads
q
0.101 mm
0.004"
Document Number: 71192 11-Sep-06
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1
Page 8
VISHAY SILICONIX
Trench FET® Power MOSFETs
Application Note 808
Mounting LITTLE FOOT®, SO-8 Power MOSFETs
Wharton McDaniel Surface-mounted LITTLE FOOT power MOSFETs use
integrated circuit and small-signal packages which have been been modified to provide the heat transfer capabilities required by power devices. Leadframe materials and
0.050
1.27
design, molding compounds, and die attach materials have been changed, while the footprint of the packages remains the same.
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs, (http://www.vishay.com/ppg?72286), for the
0.027
0.69
0.07
1.98
Figure 2. Dual MOSFET SO-8 Pad Pattern
basis of the pad design for a LITTLE FOOT SO-8 power MOSFET. In converting this recommended minimum pad to the pad set for a power MOSFET, designers must make two connections: an electrical connection and a thermal connection, to draw heat away from the package.
In the case of the SO-8 package, the thermal connections are very simple. Pins 5, 6, 7, and 8 are the drain of the MOSFET for a single MOSFET package and are connected together. In a dual package, pins 5 and 6 are one drain, and pins 7 and 8 are the other drain. For a small-signal device or integrated circuit, typical connections would be made with traces that are 0.020 inches wide. Since the drain pins serve the additional function of providing the thermal connection to the package, this level of connection is inadequate. The
The minimum recommended pad patterns for the single-MOSFET SO-8 with copper spreading (Figure 1) and dual-MOSFET SO-8 with copper spreading (Figure 2) show the starting point for utilizing the board area available for the heat-spreading copper. To create this pattern, a plane of copper overlies the drain pins. The copper plane connects the drain pins electrically, but more importantly provides planar copper to draw heat from the drain leads and start the process of spreading the heat so it can be dissipated into the ambient air. These patterns use all the available area underneath the body for this purpose.
total cross section of the copper may be adequate to carry the current required for the application, but it presents a large thermal impedance. Also, heat spreads in a circular fashion from the heat source. In this case the drain pins are the heat sources when looking at heat spread on the PC board.
Since surface-mounted packages are small, and reflow soldering is the most common way in which these are affixed to the PC board, “thermal” connections from the planar copper to the pads have not been used. Even if additional planar copper area is used, there should be no problems in the soldering process. The actual solder
0.288
7.3
connections are defined by the solder mask openings. By combining the basic footprint with the copper plane on the
0.050
1.27
0.027
0.69
0.078
1.98
0.2
5.07
0.196
5.0
Figure 1. Single MOSFET SO-8 Pad
Pattern With Copper Spreading
Document Number: 70740 www.vishay.com Revision: 18-Jun-07 1
drain pins, the solder mask generation occurs automatically.
A final item to keep in mind is the width of the power traces. The absolute minimum power trace width must be determined by the amount of current it has to carry. For thermal reasons, this minimum width should be at least
0.020 inches. The use of wide traces connected to the drain plane provides a low impedance path for heat to move away from the device.
0.288
7.3
8
0.2
5.07
With Copper Spreading
0.088
2.25
0.088
2.25
APPLICATION NOTE
Page 9
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR SO-8
0.172
(4.369)
0.028
(0.711)
Return to Index
Return to Index
0.022
(0.559)
0.246 (6.248)
Recommended Minimum Pads
Dimensions in Inches/(mm)
0.050
(1.270)
0.152
0.047
(3.861)
(1.194)
APPLICATION NOTE
www.vishay.com Document Number: 72606 22 Revision: 21-Jan-08
Page 10
Legal Disclaimer Notice
Vishay

Disclaimer

ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
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Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special, consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular purpose, non-infringement and merchantability.
Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements about the suitability of products for a particular application. It is the customer’s responsibility to validate that a particular product with the properties described in the product specification is suitable for use in a particular application. Parameters provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All operating parameters, including typical parameters, must be validated for each customer application by the customer’s technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein.
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Document Number: 91000 www.vishay.com Revision: 11-Mar-11 1
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