Datasheet si4532cd Datasheet

N- and P-Channel 30 V (D-S) MOSFET

S

1

D

1

G

1

D

1

S

2

D

2

G

2

D

2

SO-8

5

6

7

8

Top View

2

3

4

1

Ordering Information: Si4532CDY-T1-GE3 (Lead (Pb)-free and Halogen-free)

N-Channel MOSFET

D

1

G

1

S

1

S

2

G

2

D

2

P-Channel MOSFET

Si4532CDY

Vishay Siliconix

PRODUCT SUMMARY

VDS (V) R

N-Channel 30

P-Channel - 30

DS(on)

0.047 at V

0.065 at V

0.089 at V

0.140 at V

()I

= 10 V 6.0

GS

= 4.5 V 5.2

GS

= - 10 V - 4.3

GS

= - 4.5 V - 3.4

GS

(A)aQg (Typ.)

D

2.75

4.1

FEATURES

• Halogen-free According to IEC 61249-2-21
Definition

• TrenchFET® Power MOSFET

• 100 % R

• 100 % UIS Tested

• Compliant to RoHS Directive 2002/95/EC

Tested

g

APPLICATIONS

• DC/DC Converter

• Load Switch

ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)

Parameter Symbol N-Channel P-Channel Unit

Drain-Source Voltage

Gate-Source Voltage

Continuous Drain Current (T

= 150 °C)

J

Pulsed Drain Current (10 µs Pulse Width)

Source-Drain Current Diode Current

Pulsed Source-Drain Current

Single Pulse Avalanche Current

Single Pulse Avalanche Energy

Maximum Power Dissipation

Operating Junction and Storage Temperature Range

= 25 °C

T

C

= 70 °C

T

C

T

= 25 °C

A

TA = 70 °C

= 25 °C

T

C

= 25 °C

T

A

L = 0.1 mH

= 25 °C

T

C

= 70 °C

T

C

T

= 25 °C

A

TA = 70 °C

V

DS

V

GS

I

D

I

DM

I

S

I

SM

I

AS

E

AS

P

D

, T

T

J

stg

30 - 30

± 20

6.0 - 4.3

4.9 - 3.4

4.9

3.9

b, c

b, c

- 3.4

- 2.7

b, c

b, c

24 - 15

2.3 - 2.3

1.5

b, c

- 1.5

b, c

24 - 12

78

2.5 3.2 mJ

2.78 2.78

1.78 1.78

1.78

1.14

b, c

b, c

1.78

1.14

b, c

b, c

- 55 to 150 °C

V

A

W

THERMAL RESISTANCE RATINGS

Parameter Symbol

Maximum Junction-to-Ambient

Maximum Junction-to-Foot (Drain) Steady State

Notes:

a. Based on T
b. Surface mounted on 1" x 1" FR4 board.
c. t = 10 s.
d. Maximum under steady state conditions is 120 °C/W (N-Channel) and 110 °C/W (P-Channel).

Document Number: 64805
S11-0652-Rev. B, 11-Apr-11

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

= 25 °C.

C

b, d

This document is subject to change without notice.

t  10 s

N-Channel P-Channel

Typ. Max. Typ. Max.

R

thJA

R

thJF

57 70 57 70

37 45 37 45

Unit

°C/W

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Si4532CDY

Vishay Siliconix

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

Parameter Symbol Test Conditions Min. Typ.aMax. Unit

Static

Drain-Source Breakdown Voltage

V

Temperature Coefficient VDS/T

DS

V

Temperature Coefficient V

GS(th)

Gate-Source Threshold Voltage

Gate-Body Leakage

Zero Gate Voltage Drain Current

On-State Drain Current

Drain-Source On-State Resistance

Forward Transconductance

Dynamic

a

b

b

b

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

Total Gate Charge

Gate-Source Charge

Gate-Drain Charge

Gate Resistance

V

DS

GS(th)/TJ

V

GS(th)

I

GSS

I

DSS

I

D(on)

R

DS(on)

g

fs

C

iss

C

oss

C

rss

Q

g

Q

gs

Q

gd

R

g

J

VGS = 0 V, ID = 250 µA

V

= 0 V, ID = - 250 µA

GS

ID = 250 µA

I

= - 250 µA

D

ID = 250 µA

II

= - 250 µA

D

V

= VGS, ID = 250 µA

DS

V

= VGS, ID = - 250 µA

DS

VDS = 0 V, VGS = ± 20 V

V

= 30 V, V

DS

V

= - 30 V, V

DS

V

= 30 V, V

DS

V

= - 30 V, V

DS

=5 V, V

V

DS

V

= -5 V, V

DS

V

= 10 V, ID = 3.5 A

GS

V

= - 10 V, ID = - 3.5 A

GS

V

= 4.5 V, ID = 2.8 A

GS

V

= - 4.5 V, ID = - 2.5 A

GS

VDS = 15 V, ID = 2.5 A

V

= - 15 V, ID = - 3.5 A

DS

N-Channel

V

= 15 V, V

DS

P-Channel

V

= - 15 V, V

DS

VDS = 15 V, V

V

= - 15 V, V

DS

GS

N-Channel

V

= 15 V, V

DS

GS

P-Channel

V

= - 15 V, V

DS

GS

f = 1 MHz

= 0 V

GS

= 0 V

GS

= 0 V, TJ = 55 °C

GS

= 0 V, TJ = 55 °C

GS

= 10 V

GS

= - 10 V

GS

= 0 V, f = 1 MHz

GS

= 0 V, f = 1 MHz

GS

= 10 V, ID = 2.5 A

GS

= - 10 V, ID = - 2.5 A

= 4.5 V ID = 2.5 A

= - 4.5 V, ID = - 2.5 A

N-Ch 30

P-Ch - 30

N-Ch 33

P-Ch - 33

N-Ch - 5.8

P-Ch 4.5

N-Ch 1.0 3.0

P-Ch - 1.0 - 3.0

N-Ch 100

P-Ch - 100

N-Ch 1

P-Ch - 1

N-Ch 5

P-Ch - 5

N-Ch 20

P-Ch - 12

N-Ch 0.038 0.047

P-Ch 0.073 0.089

N-Ch 0.052 0.065

P-Ch 0.113 0.140

N-Ch 7

P-Ch 7

N-Ch 305

P-Ch 340

N-Ch 65

P-Ch 67

N-Ch 29

P-Ch 51

N-Ch 6 9

P-Ch 7.8 12

N-Ch 2.75 4.5

P-Ch 4.1 6.2

N-Ch 1.3

P-Ch 1.3

N-Ch 0.9

P-Ch 1.8

N-Ch 0.6 3.1 6.2

P-Ch 2.0 10 20

V

mV/°C

V

nA

µA

A



S

pF

nC



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This document is subject to change without notice.

Document Number: 64805

S11-0652-Rev. B, 11-Apr-11

Si4532CDY

Vishay Siliconix

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

Parameter Symbol Test Conditions Min. Typ.aMax. Unit

Dynamic

Tu r n - O n D e la y Ti m e

Rise Time

Turn-Off Delay Time

Fall Time

Tu r n - O n D e la y Ti m e

Rise Time

Turn-Off Delay Time

Fall Time

Drain-Source Body Diode Characteristics

Continuous Source-Drain Diode
Current

Pulse Diode Forward Current

Body Diode Voltage

Body Diode Reverse Recovery Time

Body Diode Reverse Recovery Charge

Reverse Recovery Fall Time

Reverse Recovery Rise Time

Notes:

a. Guaranteed by design, not subject to production testing.
b. Pulse test; pulse width  300 µs, duty cycle  2 %.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

a

t

d(on)

t

r

t

d(off)

t

f

t

d(on)

t

r

t

d(off)

t

f

I

S

a

I

SM

V

SD

t

rr

I

D

 - 1 A, V

I

D

I

 1 A, V

D

 - 1 A, V

I

D

N-Channel

V

= 15 V, RL = 15 

DD

 1 A, V

GEN

P-Channel

V

= - 15 V, RL = 15 

DD

GEN

N-Channel

V

= 15 V, RL = 15 

DD

GEN

P-Channel

V

= - 15 V, RL = 15 

DD

GEN

TC = 25 °C

IS = 1.25 A

I

= - 0.75 A

S

= 10 V, Rg = 1 

= - 10 V, Rg = 1 

= 4.5 V, Rg = 1 

= - 4.5 V, Rg = 1 

N-Channel

Q

I

= 1.25 A, dI/dt = 100 A/µs, TJ = 25 °C

rr

F

t

a

I

= - 2.5 A, dI/dt = - 100 A/µs, TJ = 25 °C

F

t

b

P-Channel

N-Ch 7 11

P-Ch 5.5 10

N-Ch 12 18

P-Ch 13 25

N-Ch 14 25

P-Ch 17 30

N-Ch 6 10

P-Ch 7.7 15

N-Ch 16 30

P-Ch 40 60

N-Ch 16 30

P-Ch 40 60

N-Ch 9 18

P-Ch 20 40

N-Ch 9 18

P-Ch 17 30

N-Ch 2.3

P-Ch - 2.3

N-Ch 24

P-Ch - 12

N-Ch 0.8 1.2

P-Ch - 0.8 - 1.2

N-Ch 14 21

P-Ch 17 30

N-Ch 6 10

P-Ch 11 20

N-Ch 9

P-Ch 12

N-Ch 5

P-Ch 5

ns

A

V

ns

nC

ns

Document Number: 64805
S11-0652-Rev. B, 11-Apr-11

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This document is subject to change without notice.

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3

Si4532CDY

0

6

12

18

24

02468 10

VGS=10V thru 6 V

VGS=4V

VGS=5V

V

DS

- Drain-to-Source Voltage (V)

- Drain Current (A)I

D

- On-Resistance ()R

DS(on)

0.00

0.02

0.04

0.06

0.08

0.10

0 2 4 6 8 10 12 14 16

ID - Drain Current (A)

VGS = 4.5 V

VGS = 10 V

0.0

0.2

0.4

0.6

0.8

1.0

1.2

012345

TC= 25 °C

TC= 125 °C

TC= - 55 °C

V

GS

- Gate-to-Source Voltage (V)

- Drain Current (A)I

D

0.7

0.9

1.1

1.3

1.5

1.7

- 50 - 25 0 25 50 75 100 125 150

ID=6A

VGS=4.5V

VGS=10V

T

J

-Junction Temperature (°C)

(Normalized)

- On-ResistanceR

DS(on)

Vishay Siliconix

N-CHANNEL TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

Output Characteristics

On-Resistance vs. Drain Current and Gate Voltage

10

=2.5A

I

D

8

6

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4

- Gate-to-Source Voltage (V)

GS

2

V

0

0246

Qg- Total Gate Charge (nC)

VDS=7.5V

VDS=15V

Gate Charge

400

350

300

250

200

150

C - Capacitance (pF)

100

VDS=22.5V

This document is subject to change without notice.

Transfer Characteristics

C

iss

C

C

rss

50

0

0 5 10 15 20 25 30

VDS - Drain-to-Source Voltage (V)

oss

Capacitance

On-Resistance vs. Junction Temperature

Document Number: 64805

S11-0652-Rev. B, 11-Apr-11

N-CHANNEL TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

0.0 0.2 0.4 0.6 0.8 1.0 1.2

TJ = 150 °C

TJ = 25 °C

10

0.1

V

SD

- Source-to-Drain Voltage (V)

- Source Current (A)I

S

1

0.25

0.20

0.15

0.10

- On-Resistance (Ω)

DS(on)

R

0.05

0.00
012345678 910

Source-Drain Diode Forward Voltage

VGS- Gate-to-Source Voltage (V)

On-Resistance vs. Gate-to-Source Voltage

Si4532CDY

Vishay Siliconix

TJ= 125 °C

TJ=25 °C

0.4

0.2

ID = 250 µA

0.0

- 0.2

Variance (V)V

GS(th)

- 0.4

- 0.6

- 0.8

- 50 - 25 0 25 50 75 100 125 150

TJ - Temperature (°C)

Threshold Voltage

100

Limited byR

10

1

I

- Drain Current (A)

D

TA= 25 °C

Single Pulse

0.1

0.01

0.1 1 10 100

V

* V

> minimum VGSat which R

GS

Safe Operating Area, Junction-to-Ambient

*

DS(on)

BVDSS Limited

- Drain-to-Source Voltage (V)

DS

50

40

30

Power (W)

20

10

0

0.1

Time (s )

011100.00.01

Single Pulse Power, Junction-to-Ambient

10 µs
100 µs

1ms

10 ms

100 ms

1s
10 s
100 s, DC

is specified

DS(on)

Document Number: 64805
S11-0652-Rev. B, 11-Apr-11

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This document is subject to change without notice.

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Si4532CDY

0.0

0.7

1.4

2.1

2.8

3.5

0 25 50 75 100 125 150

T

C

- Case Temperature (°C)

Power (W)

Vishay Siliconix

N-CHANNEL TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

8

6

Package Limited

4

- Drain Current (A)

D

I

2

0

0 25 50 75 100 125 150

- Case Temperature (°C)

T

C

Current Derating*

1.5

1.2

0.9

Power (W)

0.6

0.3

0.0
0 25 50 75 100 125 150

T

-Ambient Temperature (°C)

A

Power Derating, Junction-to-Foot

* The power dissipation PD is based on T

= 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper

J(max)

Power Derating, Junction-to-Ambient

dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.

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Document Number: 64805

S11-0652-Rev. B, 11-Apr-11

N-CHANNEL TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

10

-3

10

-2

1

10

100010

-1

10

-4

100

0.2

0.1

Square WavePulse Duration (s)

Normalized Effective Transient

Thermal Impedance

1

0.1

0.01

t

1

t

2

Notes:

P

DM

1. Duty Cycle, D =

2. Per Unit Base = R

thJA

= 120 °C/W

3. T

JM-TA=PDMZthJA

(t)

t

1

t

2

4. Surface Mounted

Duty Cycle = 0.5

Single Pulse

0.02

0.05

10

-3

10

-2

01110

-1

10

-4

0.2

0.1

Duty Cycle = 0.5

Square WavePulse Duration (s)

Normalized Effective Transient

Thermal Impedance

1

0.1

0.01

0.05

0.02

Single Pulse

Normalized Thermal Transient Impedance, Junction-to-Ambient

Si4532CDY

Vishay Siliconix

Normalized Thermal Transient Impedance, Junction-to-Foot

Document Number: 64805
S11-0652-Rev. B, 11-Apr-11

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Si4532CDY

VDS- Drain-to-Source Voltage (V)

- Drain Current (A)I

D

VGS=5V

0

3

6

9

12

15

0.0 0.5 1.0 1.5 2.0

VGS=10V thru 6 V

VGS=4V

VGS=3V

ID=2.5A

0

2

4

6

8

10

02468

- Gate-to-Source Voltage (V)

Qg- Total Gate Charge (nC)

V

GS

VDS=22.5V

VDS=7.5V

VDS=15V

0.0

0.5

1.0

1.5

2.0

1.0 1.5 2.0 2.5 3.0 3.5 4.0

V

GS

- Gate-to-Source Voltage (V)

- Drain Current (A)I

D

TC= 25 °C

TC= 125 °C

TC= - 55 °C

0.6

0.8

1.0

1.2

1.4

1.6

1.8

- 50 - 25 0 25 50 75 100 125 150

T

J

-Junction Temperature (°C)

(Normalized)

- On-Resistance

R

DS(on)

VGS=10V

VGS=4.5V

ID=3.2A

Vishay Siliconix

P-CHANNEL TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

Output Characteristics

0.20

0.15

VGS=4.5V

0.10

- On-Resistance (Ω)R

DS(on)

0.05

0.00

VGS=10V

0 3 6 9 12 15

ID- Drain Current (A)

On-Resistance vs. Drain Current and Gate Voltage

Transfer Characteristics

600

450

C

iss

300

C - Capacitance (pF)

150

0

C

oss

C

rss

0 6 12 18 24 30

VDS- Drain-to-Source Voltage (V)

Capacitance

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Gate Charge

This document is subject to change without notice.

On-Resistance vs. Junction Temperature

Document Number: 64805

S11-0652-Rev. B, 11-Apr-11

P-CHANNEL TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

0.0 0.3 0.6 0.9 1.2 1.5

10

V

SD

-Source-to-Drain Voltage (V)

- Source Current (A)I

S

0.1

1

0.01

TJ= 150 °C

0.001

TJ= - 50 °C

TJ= 25 °C

-0.4

-0.2

0.0

0.2

0.4

0.6

- 50 - 25 0 25 50 75 100 125 150

ID= 250 µA

Variance (V)V

GS(th)

TJ- Temperature (°C)

ID=1mA

0.0

0.1

0.2

0.3

0.4

02468 10

- On-Resistance (Ω)R

DS(on)

VGS- Gate-to-Source Voltage (V)

TJ= 25 °C

TJ= 125 °C

ID= 3.5 A

Si4532CDY

Vishay Siliconix

Source-Drain Diode Forward Voltage

Threshold Voltage

100

Limited byR

10

DS(on)

On-Resistance vs. Gate-to-Source Voltage

50

40

30

Power (W)

20

10

0

0.1

Time (s )

011100.0 0.01

Single Pulse Power, Junction-to-Ambient

*

10 µs

100 µs

Document Number: 64805
S11-0652-Rev. B, 11-Apr-11

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1

- Drain Current (A)

D

I

TA= 25 °C

Single Pulse

0.1

BVDSS Limited

0.01

0.1 1 10 100

* V

GS

- Drain-to-Source Voltage (V)

V

DS

> minimum VGSat which R

DS(on)

Safe Operating Area, Junction-to-Ambient

This document is subject to change without notice.

1ms

10 ms

100 ms

1s
10 s
100 s, DC

is specified

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Si4532CDY

0

1

2

3

4

5

0 255075100125150

T

C

- Case Temperature (°C)

I

D

- Drain Current (A)

Vishay Siliconix

P-CHANNEL TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

Current Derating*

3.5

2.8

2.1

Power (W)

1.4

0.7

0.0
0 25 50 75 100 125 150

T

Power Derating, Junction-to-Foot

* The power dissipation PD is based on T

- Case Temperature (°C)

C

J(max)

= 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper

1.5

1.2

0.9

Power (W)

0.6

0.3

0.0
0 25 50 75 100 125 150

T

-Ambient Temperature (°C)

A

Power Derating, Junction-to-Ambient

dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.

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This document is subject to change without notice.

Document Number: 64805

S11-0652-Rev. B, 11-Apr-11

P-CHANNEL TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

10

-3

10

-2

1

10

100010

-1

10

-4

100

0.2

0.1

Square WavePulse Duration (s)

Normalized Effective Transient

Thermal Impedance

1

0.1

0.01

t

1

t

2

Notes:

P

DM

1. Duty Cycle, D =

2. Per Unit Base = R

thJA

= 110 °C/W

3. T

JM-TA=PDMZthJA

(t)

t

1

t

2

4. Surface Mounted

Duty Cycle = 0.5

Single Pulse

0.02

0.05

10

-3

10

-2

01110

-1

10

-4

0.2

0.1

Duty Cycle = 0.5

Square WavePulse Duration (s)

Normalized Effective Transient

Thermal Impedance

1

0.1

0.01

0.05

0.02

Single Pulse

Normalized Thermal Transient Impedance, Junction-to-Ambient

Si4532CDY

Vishay Siliconix

Normalized Thermal Transient Impedance, Junction-to-Foot

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?64805

Document Number: 64805
S11-0652-Rev. B, 11-Apr-11

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.

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SOIC (NARROW): 8-LEAD

JEDEC Part Number: MS-012

Package Information

Vishay Siliconix

D

e

BA

1

DIM

A 1.35 1.75 0.053 0.069

A

1

B 0.35 0.51 0.014 0.020

C 0.19 0.25 0.0075 0.010

D 4.80 5.00 0.189 0.196

E 3.80 4.00 0.150 0.157

e 1.27 BSC 0.050 BSC

H 5.80 6.20 0.228 0.244

h 0.25 0.50 0.010 0.020

L 0.50 0.93 0.020 0.037

q0°8°0°8°

S 0.44 0.64 0.018 0.026

ECN: C-06527-Rev. I, 11-Sep-06
DWG: 5498

8

1

0.25 mm (Gage Plane)

A

6

7

2

5

HE

3

4

S

h x 45

C

L

MILLIMETERS INCHES

Min Max Min Max

0.10 0.20 0.004 0.008

All Leads

q

0.101 mm

0.004"

Document Number: 71192
11-Sep-06

www.vishay.com

1

VISHAY SILICONIX

TrenchFET® Power MOSFETs

Application Note 808

Mounting LITTLE FOOT®, SO-8 Power MOSFETs

Wharton McDaniel
Surface-mounted LITTLE FOOT power MOSFETs use

integrated circuit and small-signal packages which have
been been modified to provide the heat transfer capabilities
required by power devices. Leadframe materials and

0.050

1.27

design, molding compounds, and die attach materials have
been changed, while the footprint of the packages remains
the same.

See Application Note 826, Recommended Minimum Pad

Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/ppg?72286), for the

0.027

0.69

0.07

1.98

Figure 2. Dual MOSFET SO-8 Pad Pattern

basis of the pad design for a LITTLE FOOT SO-8 power
MOSFET. In converting this recommended minimum pad
to the pad set for a power MOSFET, designers must make
two connections: an electrical connection and a thermal
connection, to draw heat away from the package.

In the case of the SO-8 package, the thermal connections
are very simple. Pins 5, 6, 7, and 8 are the drain of the
MOSFET for a single MOSFET package and are connected
together. In a dual package, pins 5 and 6 are one drain, and
pins 7 and 8 are the other drain. For a small-signal device or
integrated circuit, typical connections would be made with
traces that are 0.020 inches wide. Since the drain pins serve
the additional function of providing the thermal connection
to the package, this level of connection is inadequate. The

The minimum recommended pad patterns for the
single-MOSFET SO-8 with copper spreading (Figure 1) and
dual-MOSFET SO-8 with copper spreading (Figure 2) show
the starting point for utilizing the board area available for the
heat-spreading copper. To create this pattern, a plane of
copper overlies the drain pins. The copper plane connects
the drain pins electrically, but more importantly provides
planar copper to draw heat from the drain leads and start the
process of spreading the heat so it can be dissipated into the
ambient air. These patterns use all the available area
underneath the body for this purpose.

total cross section of the copper may be adequate to carry
the current required for the application, but it presents a
large thermal impedance. Also, heat spreads in a circular
fashion from the heat source. In this case the drain pins are
the heat sources when looking at heat spread on the PC
board.

Since surface-mounted packages are small, and reflow
soldering is the most common way in which these are
affixed to the PC board, “thermal” connections from the
planar copper to the pads have not been used. Even if
additional planar copper area is used, there should be no
problems in the soldering process. The actual solder

0.288

7.3

connections are defined by the solder mask openings. By
combining the basic footprint with the copper plane on the

0.050

1.27

0.027

0.69

0.078

1.98

0.2

5.07

0.196

5.0

Figure 1. Single MOSFET SO-8 Pad

Pattern With Copper Spreading

Document Number: 70740 www.vishay.com
Revision: 18-Jun-07 1

drain pins, the solder mask generation occurs automatically.

A final item to keep in mind is the width of the power traces.
The absolute minimum power trace width must be
determined by the amount of current it has to carry. For
thermal reasons, this minimum width should be at least

0.020 inches. The use of wide traces connected to the drain
plane provides a low impedance path for heat to move away
from the device.

0.288

7.3

8

0.2

5.07

With Copper Spreading

0.088

2.25

0.088

2.25

APPLICATION NOTE

Application Note 826

Vishay Siliconix

RECOMMENDED MINIMUM PADS FOR SO-8

0.172

(4.369)

0.028

(0.711)

Return to Index

Return to Index

0.022

(0.559)

0.246
(6.248)

Recommended Minimum Pads

Dimensions in Inches/(mm)

0.050

(1.270)

0.152

0.047

(3.861)

(1.194)

APPLICATION NOTE

www.vishay.com Document Number: 72606
22 Revision: 21-Jan-08

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Document Number: 91000 www.vishay.com
Revision: 11-Mar-11 1